SD56120 RF POWER Transistors, LDMOST plastic family N-Channel enhancement-mode lateral MOSFETs General features ■ Excellent thermal stability ■ Common source configuration Push-pull ■ POUT = 100W with 14dB gain @ 860MHz ■ BeO free package Description The SD56120 is a common source N-Channel enhancement-mode lateral Field-Effect RF power transistor designed for broadband commercial and industrial applications at frequencies up to 1.0GHz. The SD56120 is designed for high gain and broadband performance operating in common source mode at 28 V. It is ideal for broadcast applications from 470 to 860 MHz requiring high linearity. M246 Epoxy sealed Pin connection 1-2 Drain 1 2 5 4 3 Source 4-5 Gate Order codes July 2006 Part number Package Branding SD56120 M246 TSD56120 Rev 3 1/15 www.st.com 15 Contents SD56120 Contents 1 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 SD56120 Electrical data 1 Electrical data 1.1 Maximum ratings Table 1. Absolute maximum ratings (TCASE = 25°C) Symbol Value Unit V(BR)DSS Drain-Source Voltage 65 V VGS Gate-Source Voltage ± 20 V Drain Current 14 A Power Dissipation (@ Tc = 70°C) 217 W Max. Operating Junction Temperature 200 °C -65 to +150 °C Value Unit 0.6 °C/W ID PDISS TJ TSTG 1.2 Parameter Storage Temperature Thermal data Table 2. Symbol RthJC Thermal data Parameter Junction - case thermal resistance 3/15 Electrical characteristics 2 SD56120 Electrical characteristics TCASE = +25 oC 2.1 Static Table 3. Static (per section) Symbol Test conditions Min 65 Unit VGS = 0 V IDS = 1 mA IDSS VGS = 0 V VDS = 28 V 1 µA IGSS VGS = 20 V VDS = 0 V 1 µA VGS(Q) VDS = 28 V ID = 200 mA 5.0 V VDS(ON) VGS = 10 V ID = 3 A 0.7 0.8 V GFS VDS = 10 V ID = 3 A 3 mho CISS VGS = 0 V VDS = 28 V f = 1 MHz 82 pF COSS VGS = 0 V VDS = 28 V f = 1 MHz 48 pF CRSS VGS = 0 V VDS = 28 V f = 1 MHz 2.8 pF REF. 7194566A 2.2 Dynamic Table 4. V 3.0 Dynamic Symbol Test conditions f = 860 MHz Min Typ 100 Max Unit POUT VDD = 28 V IDQ = 400 mA GPS VDD = 28 V IDQ = 400 mA POUT = 100 W f = 860 MHz 14 16 dB ηD VDD = 28 V IDQ = 400 mA POUT = 100 W f = 860 MHz 50 60 % GPS VDD = 28 V IDQ = 400 mA POUT = 100 W PEP 16 dB hD VDD = 28 V IDQ = 400 mA POUT = 100 W PEP 50 % IMD VDD = 28 V IDQ = 400 mA POUT = 100 W PEP -28 dBt Load VDD = 28 V IDQ = 400 mA POUT = 100 W f = 860 MHz 5:1 mismatch All phase angles f1 = 860 MHz PEP f2 = 860.1 MHz 4/15 Max V(BR)DSS Note: Note: Typ W VSWR SD56120 3 Note: Impedances Impedances Figure 1. Current conventions Table 5. Impedance data Freq. (MHz) ZIN (Ω) ZDL(Ω) 860 MHz 1.11 - j 2.63 3.01 + j 5.34 Measured drain to drain and gate to gate respectively. 5/15 Typical performance SD56120 4 Typical performance Figure 2. Capacitance vs drain voltage (per section) Figure 3. Gate-source voltage vs case temperature C (pF) VGS (NORMALIZED) 1000 1.04 f = 1 MHz per section 1.02 Id = 1 A Ciss 100 Id = 2 A Coss 1 Id = 3 A Id = 4 A Id = 5 A 10 0.98 Crss VDS = 10 V per section 0.96 1 0 10 20 30 40 50 -25 0 25 Vds (V) Figure 4. 50 75 100 Tc (°C) Drain current vs gate voltage Figure 5. Id (A) Pout (W) 6 140 Output power vs input power 120 5 100 4 80 3 60 2 40 1 0 0 2.5 3 3.5 4 Vgs (V) 6/15 VDD = 28 V IDQ = 400 mA f = 860 MHz 20 Vds = 10 V per section 4.5 5 0 1 2 Pin (W) 3 4 SD56120 Typical performance Figure 6. Power gain vs input power Figure 7. Pg (dB) Nd (%) 20 70 19 60 18 Efficiency vs output power 50 17 40 16 30 15 20 14 Vdd = 28 V Idq = 400 mA f = 860 MHz 13 f = 860 Mhz Vdd = 28 V Idq = 400 mA 10 0 12 0 1 2 3 4 0 20 40 60 Pin (W) Figure 8. 80 100 120 140 Pout (W) Power gain vs output power Figure 9. Gp (dB) Intermodulation distortion vs output power IMD3 (dBt) 0 22 -5 Idq = 800 mA 20 -10 -15 Idq = 1 A -20 18 -25 Idq = 400 mA 16 -30 Idq = 600 mA -35 Idq = 200 mA -40 14 -45 f1 = 860 MHz f2 = 860.1 MHz Vdd = 28 V Idq = 400 mA -50 12 -55 Vdd = 28V f = 860 MHz -60 10 0 1 10 100 Pout (W) 1000 20 10 40 30 60 50 80 70 100 90 120 110 Pout (WPEP) 7/15 Typical performance SD56120 Figure 10. Output power vs drain voltage Figure 11. Output power vs bias current Pout (W) Pout (W) 130 120 120 110 115 100 90 80 110 70 60 105 50 Vdd = 28 V Pin = 2.5 W f = 860 MHz Pin = 2.5 W Idq= 400 mA f = 860 MHz 40 30 100 12 16 20 24 28 32 36 Figure 12. Output power vs gate-source voltage Pout (W) 140 120 100 80 60 40 Vdd = 28 V Pin = 2.5 W f = 860 MHz 20 0 0 0.5 1 1.5 2 Vgs (V) 8/15 0 0.2 0.4 0.6 0.8 1 Idq (A) Vds (V) 2.5 3 3.5 1.2 1.4 1.6 1.8 2 SD56120 5 Test circuit Test circuit Figure 13. 860MHz test circuit schematic TL1 DIMENSION TABLE Z9 Z5 Z3 Z1 DIM Z11 Z7 IN MM W XL W X L Z1,Z12 0.215 X TYP 5,46 X TYP Z2,Z3 0.215 X 0.850 5,46 X 21,59 Z4,Z5 0.344 X 1.000 8,73 X 25,40 Z6,Z7 0.344 X 0.440 8,73 X 11,17 Z8,Z9 0.700 X 0.870 17,78 X 22,10 Z10,Z11 0.215 X 0.670 5,46 X 17,02 TL1 & TL2 0.100 X 2.37 2,54 X 60,20 DIMENSION OF MCROSTRIP = 1/2 PRINTED BALUN ONLY. Z12 Z6 Z2 Z10 Z4 Z8 TL2 TRANSMISSON LINE DIMENSIONS VGG VDD FB1 + R1 C16 R2 C28 C29 C21 C22 C20 C19 C18 L1 R3 R7 BALUN1 RF INPUT C6 D.U.T. C12 C13 C9 C2 C4 C5 C8 C3 C10 BALUN2 RF OUTPUT C11 C14 C1 R1 R8 C7 C15 R6 VGG R4 + Note: VDD FB2 R5 C31 C17 L2 C27 C30 C26 C25 C24 C23 1 Dimensions at component symbols are reference for component placement. 2 Gap between ground & transmission line = 0.056 [1.42] +0.002 [0.05] -0.000 [0.00] typ. 9/15 Test circuit SD56120 Table 6. 860MHz test circuit component part list Component C32 Description .6 - 4.5 pF VARIABLE CAPACITOR C31, C28 .01 µF ATC 200B SURFACE MOUNT CERAMIC CHIP CAPACITOR C29, C30 62 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR C27, C22 270 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR C26, C21 1200 pF ATC 700B SURFACE MOUNT CERAMIC CHIP CAPACITOR C25 ,C20 0.1 µF 500V SURFACE MOUNT CERAMIC CHIP CAPACITOR C24, C19, C17, C16 C23, C18 10 µF 50V ALUMINUM ELECTROLYTIC RADIAL LEAD SURFACE MOUNT CAPACITOR 100 µF 63V ALUMINUM ELECTROLYTIC RADIAL LEAD CAPACITOR C15, C14, C13, C12 47 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR C11 0.8 - 8 pF GIGATRIM VARIABLE CAPACITOR C10 3.0 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR C9, C8 4.3 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR C7, C6, C5 10 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR C4 2.0 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR C3, C2 20 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR C1 1.3 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR R7, R8 100 OHM 1/4 W SURFACE MOUNT CHIP RESISTOR R6, R3 22 OHM 1/4 W CARBON LEADED RESISTOR R5, R2 4.7 OHM 1/4 W CARBON LEADED RESISTOR R4, R1 82 OHM 1/4 W CARBON LEADED RESISTOR B2, B1 BALUN, 50 OHM SUCOFORM, OD 0.141 2.37 LG COAXIAL CABLE OR EQUIVALENT L2, L1 INDUCTOR, 6 TURN AIR-WOUND #18AWG ID=0.130[3,30] MAGNET WIRE FB2, FB1 PCB 10/15 SURFACE MOUNT EMI SHIELD BEAD ULTRALAM 2000. 0.030” THK εr = 2.55, 2 Oz ED CU BOTH SIDES SD56120 Test circuit Figure 14. 860MHz production test fixture + + + 4 inches Figure 15. 860MHz test circuit photomaster 6.4 inches 11/15 Package mechanical data 6 SD56120 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 12/15 SD56120 Package mechanical data Table 7. M246 (.230 x .650 WIDE 4/L BAL N/HERM W/FLG) mechanical data Dim. mm. Min Typ Inch Max Min Typ Max A 5.33 5.59 .210 .220 B 6.48 6.73 .255 .265 C 17.27 18.29 .680 .720 D 5.72 5.97 .225 .235 E 22.86 .900 F 28.83 29.08 1.135 1.145 G 16.26 16.76 .640 .660 H 4.19 5.08 .165 .200 I 0.08 0.15 .003 .006 J 1.83 2.24 .072 .088 K 1.40 1.65 .055 .065 L 3.18 3.43 .125 .135 Figure 16. Package dimensions Controlling dimension: Inches Ref. 7145054A 13/15 Revision history 7 SD56120 Revision history Table 8. 14/15 Revision history Date Revision Changes 18-Jun-2001 1 First Issue 12-Sep-2004 2 Few updates 13-Jul-2006 3 New template, added lead free info SD56120 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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