ETC U631H256

U631H256
SoftStore 32K x 8 nvSRAM
Features
Description
‡ High-performance CMOS nonvolatile static RAM 32768 x 8 bits
‡ 25 ns Access Times
‡ 10 ns Output Enable Access
Times
‡ Software STORE Initiation
‡ Automatic STORE Timing
‡ 106 STORE cycles to EEPROM
‡ 100 years data retention in
EEPROM
‡ Automatic RECALL on Power Up
‡ Software RECALL Initiation
‡ Unlimited RECALL cycles from
EEPROM
‡ Unlimited Read and Write to
SRAM
‡ Single 5 V ± 10 % Operation
‡ Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
‡ QS 9000 Quality Standard
‡ ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
‡ RoHS compliance and Pb- free
Package: SOP28 (330 mil)
The U631H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disabled.
The U631H256 is a fast static RAM
(25 ns), with a nonvolatile electrically erasable PROM (EEPROM)
element incorporated in each static
memory cell. The SRAM can be
read and written an unlimited number of times, while independent
nonvolatile
data
resides
in
EEPROM. Data transfers from the
SRAM to the EEPROM (the
STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through software sequences.
The U631H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Pin Description
Pin Configuration
A14
1
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U631H256 is pin compatible
with standard SRAMs.
28
VCC
A12
2
27
W
A7
3
26
A13
A6
4
25
A8
A5
5
24
A4
6
A3
7
A2
8
SOP 21
A1
9
20
E
A0
10
19
DQ7
DQ0
11
18
DQ6
DQ1
12
17
DQ5
Signal Name
Signal Description
A9
A0 - A14
Address Inputs
23
A11
DQ0 - DQ7
Data In/Out
22
G
E
Chip Enable
A10
G
Output Enable
W
VCC
Write Enable
Power Supply Voltage
VSS
Ground
DQ2
13
16
DQ4
VSS
14
15
DQ3
Top View
March 31, 2006
STK Control #ML0043
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Rev 1.0
U631H256
Block Diagram
EEPROM Array
512 x (64 x 8)
A5
A6
A7
A8
A9
A11
A12
A13
A14
VCC
Row Decoder
STORE
SRAM
Array
VSS
RECALL
512 Rows x
64 x 8 Columns
Store/
Recall
Control
DQ0
DQ1
VCC
Input Buffers
Column I/O
DQ2
DQ3
DQ4
DQ5
DQ6
Column Decoder
Software
Detect
A0 A1 A2 A3 A4 A10
A0 - A13
G
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
High-Z
Internal Read
L
H
H
High-Z
Read
L
H
L
Data Outputs Low-Z
Write
L
L
*
Data Inputs High-Z
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
VCC
-0.5
7
V
Input Voltage
VI
-0.3
VCC+0.5
V
Output Voltage
VO
-0.3
VCC+0.5
V
Power Dissipation
PD
1
W
Power Supply Voltage
Operating Temperature
Storage Temperature
C-Type
K-Type
Ta
0
-40
70
85
°C
°C
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
STK Control #ML0043
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Rev 1.0
March 31, 2006
U631H256
Recommended
Operating Conditions
Symbol
Power Supply Voltage
VCC
Input Low Voltage
VIL
Input High Voltage
VIH
Conditions
-2 V at Pulse Width
10 ns permitted
Min.
Max.
Unit
4.5
5.5
V
-0.3
0.8
V
2.2
VCC+0.3
V
C-Type
DC Characteristics
Symbol
Unit
Min.
Operating Supply Currentb
ICC1
K-Type
Conditions
Max.
Min.
Max.
VCC
VIL
VIH
= 5.5 V
= 0.8 V
= 2.2 V
tc
= 25 ns
95
100
mA
Average Supply Current during
STOREc
ICC2
VCC
E
W
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
6
7
mA
Average Supply Current
at tcR = 200 nsb
(Cycling CMOS Input Levels)
ICC3
VCC
W
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
20
20
mA
ICC(SB)1
VCC
E
= 5.5 V
≥ VIH
tc
= 25 ns
40
42
mA
VCC
E
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
1
2
mA
Standby Supply Currentd
(Cycling TTL Input Levels)
Standby Supply Curentd
(Stable CMOS Input Levels)
ICC(SB)
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE).
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
March 31, 2006
STK Control #ML0043
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U631H256
Symbol
DC Characteristics
Conditions
Min.
2.4
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
VCC
= 5.5 V
VIH
VIL
= 5.5 V
= 0V
-1
VCC
E or G
VOH
VOL
= 5.5 V
≥ VIH
= 5.5 V
= 0V
-1
Input Leakage Current
High
Low
IIH
IIL
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
Max.
Unit
0.4
V
V
-4
mA
mA
1
μA
μA
8
1
μA
μA
SRAM Memory Operation
No.
e:
f:
g:
h:
Symbol
Switching Characteristics
Read Cycle
Unit
Alt.
IEC
Min. Max.
1
Read Cycle Timef
tAVAV
tcR
2
Address Access Time to Data Validg
tAVQV
ta(A)
25
ns
3
Chip Enable Access Time to Data Valid
tELQV
ta(E)
25
ns
4
Output Enable Access Time to Data
Valid
tGLQV
ta(G)
10
ns
5
E HIGH to Output in High-Zh
tEHQZ
tdis(E)
10
ns
6
G HIGH to Output in High-Zh
tGHQZ
tdis(G)
10
ns
7
E LOW to Output in Low-Z
tELQX
ten(E)
5
ns
8
G LOW to Output in Low-Z
tGLQX
ten(G)
0
ns
9
Output Hold Time after Addr. Changeg
tAXQX
tv(A)
3
ns
10 Chip Enable to Power Activee
tELICCH
tPU
0
ns
11 Chip Disable to Power Standbyd, e
tEHICCL
tPD
25
ns
25
ns
Parameter guaranteed but not tested.
Device is continuously selected with E and G both Low.
Address valid prior to or coincident with E transition LOW.
Measured ± 200 mV from steady state output voltage.
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Rev 1.0
March 31, 2006
U631H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
tcR
Ai
DQi
(1)
Address Valid
ta(A) (2)
Output Data Valid
Previous Data Valid
tv(A) (9)
Output
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR
Ai
Address Valid
ta(A)
ta(E)
E
Output
ICC
(2)
(3)
tdis(E) (5)
tPD (11)
ten(E) (7)
G
DQi
(1)
ta(G)
(4)
tdis(G)
(6)
ten(G) (8)
High Impedance
Output Data Valid
tPU (10)
ACTIVE
STANDBY
No. Switching Characteristics
Write Cycle
Symbol
Unit
Alt. #1
Alt. #2
IEC
Min.
12 Write Cycle Time
tAVAV
tAVAV
tcW
25
ns
13 Write Pulse Width
tWLWH
tw(W)
20
ns
tWLEH
tsu(W)
20
ns
14 Write Pulse Width Setup Time
Max.
15 Address Setup Time
tAVWL
tAVEL
tsu(A)
0
ns
16 Address Valid to End of Write
tAVWH
tAVEH
tsu(A-WH)
20
ns
17 Chip Enable Setup Time
tELWH
tsu(E)
20
ns
tELEH
tw(E)
20
ns
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
tDVWH
tDVEH
tsu(D)
10
ns
20 Data Hold Time after End of
Write
tWHDX
tEHDX
th(D)
0
ns
21 Address Hold after End of Write
tWHAX
tEHAX
th(A)
0
ns
22 W LOW to Output in High-Zh, i
tWLQZ
tdis(W)
23 W HIGH to Output in Low-Z
tWHQX
ten(W)
March 31, 2006
STK Control #ML0043
5
10
5
Rev 1.0
ns
ns
U631H256
Write Cycle #1: W-controlledj
tcW
Ai
(12)
Address Valid
tsu(E)
th(A) (21)
(17)
E
W
tsu(A)
tsu(A-WH) (16)
tw(W) (13)
(15)
th(D) (20)
tsu(D) (19)
DQi
Input Data Valid
Input
tdis(W)
DQi
ten(W) (23)
(22)
High Impedance
Previous Data
Output
Write Cycle #2: E-controlledj
tcW
Ai
E
(12)
Address Valid
tw(E) (18)
th(A) (21)
tsu(A)
(15)
W
tsu(W)
(14)
tsu(D) (19)
DQi
Input
th(D)
(20)
Input Data Valid
DQi
High Impedance
Output
undefined
i:
j:
L- to H-level
H- to L-level
If W is low and when E goes low, the outputs remain in the high impedance state.
E or W must be > VIH during address transitions.
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March 31, 2006
U631H256
Nonvolatile Memory Operations
No.
k:
Symbol
STORE Cycle Inhibit and
Automatic Power Up RECALL
Min.
Alt.
24 Power Up RECALL Durationk
tRESTORE
Low Voltage Trigger Level
VSWITCH
Max.
Unit
650
μs
4.5
V
IEC
4.0
tRESTORE starts from the time VCC rises above VSWITCH.
STORE Cycle Inhibit and Automatic Power Up RECALL
VCC
5.0 V
VSWITCH
t
STORE inhibit
Power Up
RECALL
(24)
tRESTORE
Software Mode Selection
E
W
L
H
L
H
A13 - A0
(hex)
Mode
I/O
Power
Notes
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l, m
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l:
ICC2
l, m
l, m
l, m
l, m
l, m
l, m
The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
m: While there are 15 addresses on the U631H256, only the lower 14 are used to control software modes.
March 31, 2006
STK Control #ML0043
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U631H256
Symbol
No. Software Controlled STORE/RECALL
Cyclel, n
n:
o:
p:
q:
r:
s:
Unit
Alt.
IEC
Min.
Max.
25 STORE/RECALL Initiation Time
tAVAV
tcR
25
26 Chip Enable to Output Inactiveo
tELQZ
tdis(E)SR
600
ns
27 STORE Cycle Timep
tELQXS
td(E)S
10
ms
28 RECALL Cycle Timeq
tELQXR
td(E)R
20
μs
29 Address Setup to Chip Enabler
tAVELN
tsu(A)SR
0
ns
30 Chip Enable Pulse Widthr, s
tELEHN
tw(E)SR
20
ns
31 Chip Disable to Address Changer
tEHAXN
th(A)SR
0
ns
ns
The software sequence is clocked with E controlled READs
Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
Software Controlled STORE/RECALL Cyclet, u (E = HIGH after STORE initiation)
tcR
Ai
ADDREESS 1
ADDRESS 6
t w(E)SR (30)
E
tsu(A)SR (29)
DQi
tcR (25)
(25)
(31)
High Impedance
Output
td(E)S (27)
th(A)SR
VALID
td(E)R
(28)
VALID
tdis(E)SR
(26)
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
tcR (25)
Ai
ADDRESS 1
tw(E)SR
E
Output
(31)
(30)
tsu(A)SR (29)
DQi
ADDRESS 6
tsu(A)SR (29)
th(A)SR
th(A)SR
td(E)S (27)
(31)
High Impedance
td(E)R (28)
VALID
tdis(E)SR (26)
VALID
t:
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the U631H256 performs a STORE
or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
STK Control #ML0043
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Rev 1.0
March 31, 2006
U631H256
Test Configuration for Functional Check
E
W
G
v:
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ment of all 8 output pins
VIL
VCCw
Simultaneous measure-
VIH
relevant test measurement
Input level according to the
5V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
480
VO
30 pF v
255
VSS
In measurement of tdis-times and ten-times the capacitance is 5 pF.
w: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
Capacitancee
Conditions
VCC
VI
f
Ta
Input Capacitance
Output Capacitance
Symbol
= 5.0 V
= VSS
= 1 MHz
= 25 °C
Min.
Max.
Unit
CI
8
pF
CO
7
pF
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
U631H256
S
C
25 G1
Type
Leadfree Option
G1 = Leadfree Green Package
Package
S2 = SOP28 (330mil) Type 2
Access Time
25 = 25 ns
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
Device Marking (example)
Product specification
ZMD
U631H256SC
25 Z 0425
G1
Date of manufacture
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Leadfree Green Package
Internal Code
March 31, 2006
STK Control #ML0043
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U631H256
Device Operation
The U631H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory operates in SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM shadow (the STORE operation) or from
EEPROM to SRAM (the RECALL operation). In this
mode SRAM functions are disabled.
SRAM READ
The U631H256 performs a READ cycle whenever E
and G are LOW while W is HIGH. The address specified on pins A0 - A14 determines which of the 32768
data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid
after a delay of tcR. If the READ is initiated by E or G,
the outputs will be valid at ta(E) or at ta(G), whichever is
later. The data outputs will repeatedly respond to
address changes within the tcR access time without the
need for transition on any control input pins, and will
remain valid until another address change or until E or
G is brought HIGH or W is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE
or tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
Noise Consideration
The U631H256 is a high speed memory and therefore
must have a high frequency bypass capacitor of approximately 0.1 μF connected between VCC and VSS using
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise problems.
Software Nonvolatile STORE
The U631H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U631H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the preSTK Control #ML0043
vious nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE
cycle is initiated, further inputs and outputs are disabled
until the cycle is completed .Because a sequence of
addresses is used for STORE initiation, it is important
that no other READ or WRITE accesses intervene in
the sequence or the sequence
will be aborted and no STORE or RECALL will take
place.
To initiate the STORE cycle the following READ
sequence must be performed:
1.
2.
3.
4.
5.
6.
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
0E38
31C7
03E0
3C1F
303F
0FC0
(hex)
(hex)
(hex)
(hex)
(hex)
(hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE
Cycle
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ operations must be performed:
1.
2.
3.
4.
5.
6.
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
0E38
31C7
03E0
3C1F
303F
0C63
(hex)
(hex)
(hex)
(hex)
(hex)
(hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL
Cycle
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
Automatic Power Up RECALL
On power up, once VCC exceeds the sense voltage of
VSWITCH, a RECALL cycle is automatically initiated.
The voltage on the VCC pin must not drop below
10
Rev 1.0
March 31, 2006
U631H256
RECALL; SRAM operation cannot commence until
tRESTORE after VCC exceeds VSWITCH.
If the U631H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and VCC.
Hardware Protection
The U631H256 offers hardware protection against
inadvertent STORE operation through VCC sense.
For VCC < VSWITCH the software initiated STORE operation will be inhibited.
Low Average Active Power
The U631H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby current.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
March 31, 2006
STK Control #ML0043
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U631H256
LIFE SUPPORT POLICY
SIMTEK products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SIMTEK product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by SIMTEK for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However SIMTEK
Corporation (SIMTEK) makes no guarantee or warranty concerning the accuracy of said information and shall
not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The
information in this document describes the type of component and shall not be considered as assured characteristics.
SIMTEK does not guarantee that the use of any information contained herein will not infringe upon the patent,
trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby.
This document does not in any way extent SIMTEK’s warranty on any product beyond that set forth in its standard terms and conditions of sale.
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March 31, 2006
Simtek Corporation
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Change record
Date/Rev
Name
Change
01.08.2001
Steffen Buschbeck
changed limit for CMOS standby current
Page 3: ICC(SB) = 2 mA for K-Type
01.11.2001
Ivonne Steffens
format revision and release for „Memory CD 2002“
25.09.2002
Matthias Schniebel
adding „Type 1“ to SOP28 (330 mil)
30.10.2002
Matthias Schniebel
combining U631H256 and U631H256SM in one datasheet
04.12.2003
Matthias Schniebel
Operating Supply Current at tcR = 200 ns: ICC3 = 20 mA
21.04.2004
Matthias Schniebel
adding „Leadfree Green Package“ to ordering information
adding „Device Marking“
7.4.2005
Stefan Günther
changing 106 endurance cycles and 100a dataretention, mil.
temperature range and PDIP28 (300mil) deleted, G1 no more on
special request, add S2 = SOP28 (330mil) Type 2 (chip pack)
12.10.2005
Stefan Günther
change -55°C to -40°C and M- to A- type in DC characteristics,
absolute ratings, ordering code
Simtek
Assigned Simtek Document Control Number
1.0