TI UCC29421PW

 SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
D Operation Down to an Input
D
D
D
D
D
D
D
D
D
D
D
D
Voltage of 1.8 V
High Efficiency Boost, SEPIC or
Flyback (Buck-Boost) Topologies
Drives External FETs for
High-Current Applications
Up to 2-MHz Oscillator
Synchronizable Fixed Frequency
Operation
High-Efficiency Low-Power Mode
High-Efficiency at Very Low-Power
with Programmable Variable
Frequency Mode
Pulse-by-Pulse Current Limit
5-µA Supply Current in Shutdown
150-µA Supply Current in Sleep
Mode
Selectable NMOS or PMOS
Rectification
Built-In Power-On Reset
(UCC39422 Only)
Built-In Low-Voltage Detect
(UCC39422 Only)
simplified schematic block diagram and
application circuit
1.8 V(MIN)
VPUMP
+
VIN
7
2 CELL
ALKALINE/
NiCd OR
+
1 LI−ION
9
1.24 V
VREF
8
SYNC/SD
CHARGE
PUMP
13
3
PWM
OSC
RT
14
2
VPUMP
CP
VOUT
RSEN
VOUT
RECT
4
RSEL
ANTI−
CROSS
COND.
19
VGD
6
PWM CIRCUITRY
ISENSE
SLOPE
COMPENSATION
12
+
X10
CURRENT LIMIT
LOW POWER
MODE
CHRG
PGND
50 mV TYP
5
ERROR 1.24 V
AMP
+
FB
17
PFM MODE
CONTROL
COMP
18
PFM
16
GND
15
description
+
1.22V
The UCC39421 family of synchronous
PWM controllers is optimized to operate
from dual alkaline/NiCd cells or a single
Lithium-Ion (Li-Ion) cell, and convert to
adjustable output voltages from 2.5 V to
8 V. For applications where the input
voltage does not exceed the output, a
standard boost configuration is used.
RESET
1
200 mS
RESET/
POR
UCC39422
ONLY
+
1.18 V
RSADJ
LOWBAT
20
10
VDET
11
+
1.24 V
UDG−98122
For other applications where the input voltage can swing above and below the output, a 1:1 coupled inductor
(Flyback or SEPIC) is used in place of the single inductor. Fixed frequency operation can be programmed, or
synchronized to an external clock source. In applications where (at light loads) variable frequency mode is
acceptable, the IC can be programmed to automatically enter PFM (pulse frequency modulation) mode for an
additional efficiency benefit.
Synchronous rectification provides excellent efficiency at high power levels, where N- or P- type MOSFETs can
be used. At lower power levels (between 10% and 20% of full load) where fixed frequency operation is required,
low power mode is entered. This mode optimizes efficiency by cutting back on the gate drive of the charging
FET. At very low power levels, the IC enters a variable frequency mode (PFM). PFM can be disabled by the user.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2 #++ )#!#"($(!%-
POST OFFICE BOX 655303
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1
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
description (continued)
Other features include pulse-by-pulse current limiting, and a low 5-µA quiescent current during shutdown. The
UCC39422 incorporates programmable power-on reset circuitry and an uncommitted comparator for low
voltage detection. The available packages are 20-pin TSSOP or 20-pin N for the UCC39422, and 16-pin TSSOP
or 16-pin N for the UCC39421.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Ĕ}
Supply Voltage (VIN, VOUT,VPUMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
RSEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 12 V
SYNC/SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V
ISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 1 V
Storage Temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are with respect to ground. Currents are positive into and negative out of the specified terminals. Consult the Packaging Section of
the Databook for thermal limitations and considerations of the package.
TSSOP−16, DIL−16
N, PW PACKAGE
TSSOP−20, DIL−20
N, PW PACKAGES
(TOP VIEW)
(TOP VIEW)
RESETB
RSEN
VOUT
RECT
PGND
CHRG
VPUMP
CP
VIN
LOWBAT
2
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
RSADJ
RSEL
COMP
FB
PFM
GND
RT
SYNC/SD
ISENSE
VDET
POST OFFICE BOX 655303
RSEN
VOUT
RECT
PGND
CHRG
VPUMP
CP
VIN
• DALLAS, TEXAS 75265
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
RSEL
COMP
FB
PFM
GND
RT
SYNC/SD
ISENSE
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
electrical characteristics over recommended operating free-air temperature range, TA = −40°C to
85°C for the UCC2942x, 0°C to 70°C for the UCC3942x, RT = 100 kΩ, VVPUMP = 6 V, VVIN = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN Section
Minimum start−up voltage
1.5
1.8
V
Operating current
Not in PFM mode,
No load
35
60
µA
Sleep mode current
PFM mode,
No load
35
60
µA
Shutdown supply current
SYNC/SD = high
Startup frequency
Startup off time
VIN = 1.8 V
VIN = 1.8 V
Startup CS threshold
VIN = 1.8 V
60
Minimum PUMP or VOUT voltage to exit
startup
2.2
1.5
4
µA
120
190
kHz
2
5
µs
36
56
mV
2.5
2.8
V
6.6
V
100
275
µA
5
15
µA
2
5
µA
5.3
5.5
VPUMP Section
Regulation voltage
Operating current
VVOUT=3.3 V,
Outputs OFF
See Note 1
5.0
Sleep mode current
Shutdown supply current
CP voltage to turn-on pump switch
SYNC/SD = High,
VVPUMP = 3 V
VVPUMP = 5 V
VOUT = 3 V,
Pump switch Rds(on)
V
Ω
4
VOUT Section
300
500
650
µA
50
100
150
µA
1
2.2
µA
1.4
1.7
2.0
V
1.205
1.235
1.265
V
100
350
nA
6.5
13
20
µA
–20
–13
–6.5
µA
150
270
370
µs
Unity gain bandwidth
VFB = regulation voltage ±4 mV
CC = 330 pF,
See Note 1
Max output voltage
VFB = 0 V
1.6
1.9
2.3
V
RT = 350 kΩ
RT = 100 kΩ
100
150
190
kHz
375
475
575
kHz
MHz
Operating current
Sleep mode current
Shutdown supply current
SYNC/SD = High
VPUMP to VOUT threshold to enable
N-channel rectifier
VOUT = 3.3 V
Error Amplifier Section
Regulation voltage
2 V < VIN < 5 V
FB input current
VFB = 1.25 V
VCOMP = 1 V,
VFB = regulation roltage +50 mV
VCOMP = 0 V,
VFB = regulation voltage –50 mV
Max sinking current, IOL
Max sourcing current, IOH
Transconductance
100
kHz
Oscillator Section
Frequency stability
RT = 35 kΩ
RT voltage
SYNC/shutdown threshold
SYNC input current
SYNC/SD = 2.5 V
Minimum SYNC pulse width
See Note 1
Maximum SYNC high time
To avoid shutdown
SYNC range
fo = measured frequency at RT = 100 kΩ
0.9
1.2
1.4
0.600
0.625
0.650
V
0.9
1.2
1.6
V
200
nA
50
ns
11
1.1 fo
20
29
1.7 fo
µs
kHz
NOTE 1: Ensured by design. Not production tested.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
electrical characteristics over recommended operating free-air temperature range, TA = −40°C to
85°C for the UCC2942x, 0°C to 70°C for the UCC3942x, RT = 100 kΩ, VVPUMP = 6 V, VVIN = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Current Sense Section
Gain
Overcurrent limit threshold
Unity gain bandwidth
See Note 1
COMP voltage to ISENSE accuracy
ISENSE = 70 mV
8
10
11
120
150
190
25
0.83
1.00
80
88
V/V
mV
MHz
1.23
V
PWM Section
Maximum duty cycle
Minimum duty cycle
VISENSE = 0 V,
VFB = 1.5 V
Low power mode VCOMP threshold
At COMP pin
Slope compensation accuracy
RT = 350 kΩ,
RSEL = GND
Rectifier zero current threshold
VFB = 0 V
RSLOPE = 20 kΩ
RSEL = VIN
RSEL threshold
%
0
%
V
0.53
0.60
0.67
1.4
2.8
4.0
A/s
–2
15
30
mV
–28
–15
2
mV
0.5
0.9
1.3
V
0.17
0.22
0.27
V
0.40
0.47
0.65
V
4
9
µs
1.185
1.220
1.245
V
PFM Section
PFM disable threshold
Comp hold during sleep
Startup delay after sleep
VPFM = 0.4 V
VFB < 1.23 V
FB voltage to sleep off
VGSW Drive Section
Rise time
CO = 1 nF
18
35
ns
Fall time
CO = 1 nF
14
30
ns
0.4
0.65
V
Output high
IOUT = –100 mA,
IOUT = –1 mA,
Output low
IOUT = 100 mA
IOUT = 1 mA
Respect to VPUMP
Respect to VPUMP
Charge off to rectifier on delay
10
4
10
0.2
0.35
mV
V
2
6
mV
40
65
ns
RECT Drive Section
Rise time
CO = 1 nF
20
40
ns
Fall time
CO = 1 nF
14
30
ns
0.2
0.5
V
Output high
IOUT = –100 mA,
IOUT = –1 mA,
5
10
mV
0.2
0.35
Output low rectifier
IOUT = 100 mA
IOUT = 1 mA
Respect to VPUMP
Respect to VPUMP
Rectifier off to charge on delay
V
2
6
mV
40
65
ns
100
250
400
ms
–7
–5.5
–4
%
0.1
0.25
V
0.05
0.2
µA
10
RESET Section (UCC39422 Only)
Reset timeout
CRSADJ = 0.33 µF
Reset threshold
Percentage below regulation voltage
Output low voltage
Reset condition,
Output leakage
RESET = 8 V
I = 5 mA
NOTE 1: Ensured by design. Not production tested.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
electrical characteristics over recommended operating free-air temperature range, TA = −40°C to
85°C for the UCC2942x, 0°C to 70°C for the UCC3942x, RT = 100 kΩ, VVPUMP = 6 V, VVIN = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Detection Section (UCC39422 Only)
Threshold voltage
1.26
1.34
Output low voltage
I = 5 mA
1.18
0.15
0.3
V
V
Output leakage
LOWBAT = 8 V
0.05
0.25
µA
PIN DESCRIPTIONS
COMP: This is the output of the transconductance error amplifier. Connect the compensation components from
this pin to ground.
CHRG: This is the gate drive output for the N-channel charge MOSFET. Connect it to the gate directly, or through
a low-value gate resistor.
CP: This is the input for the charge pump. For applications requiring a charge pump, connect this pin to the
charge pump diode and flying capacitor, as shown in the applications diagram of Figure 4. For applications
where no charge pump is required, this pin should be grounded.
FB: The feedback input is the inverting input to the transconductance error amplifier. Connect this pin to a
resistive divider between VOUT and ground. The output voltage is regulated to:
V
OUT
+ 1.235
(R1 ) R2)
R1
where R1 goes to GND and R2 goes to VOUT.
GND: This is the signal ground pin for the device. It should be tied to the local ground plane.
ISENSE: This is the input to the X10 wide bandwidth current-sense amplifier. Connect this pin to the high side
of the current-sense resistor. An internal current is sourced out this pin for slope compensation. For applications
requiring slope compensation (or filtering of the current-sense signal), use a resistor in series with this pin.
LOWBAT: This is the open drain output of the uncommitted comparator. (UCC39422 only). This output is low
when the VDET pin is above 1.25 V.
PFM: This is the programming pin for the PFM (pulse frequency modulation) mode threshold. Connect this pin
to a resistive divider off of the FB pin (or VOUT) to set the PFM threshold. To disable PFM Mode, connect this
pin to ground (below 0.2 V).
PGND: This is the power ground pin for the device. Connect it directly to the ground return of the current-sense
resistor.
RECT: This is the gate drive output for the synchronous rectifier. Connect it to the gate of the P- or N-channel
MOSFET directly, or through a low value gate resistor.
RSEN: This pin is used to sense the voltage across the synchronous rectifier for commutation. In boost
configurations, connect this pin through a 1-kΩ resistor to the junction of the two MOSFETs and the inductor.
In flyback and SEPIC configurations, connect this pin through a 1-kΩ resistor to the junction of the drain of the
synchronous rectifier and the secondary side winding of the coupled inductor.
RSADJ: A capacitor from this pin to ground sets the reset delay. (UCC39422 only)
RSEL: This pin programs the device for N- or P-channel synchronous rectifiers by inverting the phase of the
RECT gate drive output. Connect this pin to ground for N-channel MOSFETs, connect it to VIN for P-channel
MOSFETs.
POST OFFICE BOX 655303
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5
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
RESET: This is the open drain output of the reset comparator. (UCC39422 only) and is active low.
RT: A resistor from this pin to ground programs the frequency of the pulse width modulator.
Frequency (MHz) ^
50
R (kW)
T
SYNC/SD: This pin has two functions. It may be used to synchronize the UCC39421’s switching frequency to
an external clock, or to shutdown the IC entirely. In shutdown, the quiescent current is reduced to just a few
microamps (both external FETs are turned off). To shutdown the converter, this pin must be held high (above
2.0 V) for a minimum of 29 µs. If not used, this pin should be grounded.
To synchronize the internal oscillator to an external source, the SYNC/SD pin must be driven with a clock pulse,
with a minimum amplitude of 2.0 V. The internal circuitry syncs to the rising edge of the external clock. The clock
pulse width is not critical (must be 50 ns minimum).
Note: When coming out of shutdown (or during power-up), the SYNC/SD pin must be held low for a minimum
of 200 µs before applying an external clock to ensure startup.
VPUMP: This is the output of the charge pump. For applications requiring a charge pump, connect a 1-µF
capacitor from this pin to ground. Otherwise, connect this pin to the higher of VIN or VOUT, and decouple with
a 0.1-µF capacitor.
VOUT: Connect this pin to the output voltage. This input is used for sensing the voltage across the synchronous
rectifier and for supplying power to internal circuitry and should be decoupled with a 0.1-µF capacitor.
VIN: This is the input power pin of the device. Connect this pin to the input voltage source. A 0.1-µF decoupling
capacitor should be connected between this pin and ground.
VDET: This is the non-inverting input to an uncommitted comparator. This input may be used for detecting a
low-battery condition. (UCC39422 only)
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
The UCC39421 is a high frequency, synchronous PWM controller optimized for portable, battery-powered
applications where size and efficiency are of critical importance. It includes high-speed, high-current FET
drivers for those converter applications requiring low Rds(on) external MOSFETs. A detailed block diagram is
shown in Figure 2.
optimizing efficiency
The UCC39421 optimizes efficiency and extends battery life with its low quiescent current and its synchronous
rectifier topology. The additional features of low-power (LP) mode and PFM mode maintain high efficiency over
a wide range of load current. These features are discussed in detail.
power saving modes
Since this is a peak current mode controller, the error amplifier output voltage sets the peak inductor current
required to sustain the load. The UCC39421 incorporates two special modes of operation designed to optimize
efficiency over a wide range of load current. This is done by comparing the error amplifier output voltage (on
the COMP pin) to two fixed thresholds (one of which is user programmable). If the error amplifier output voltage
drops below the first threshold, low power mode is entered. If the error-amplifier output voltage drops even
further, below a second user programmable threshold, PFM mode is entered. These modes of operation are
designed to maintain high efficiency at light loads, and are described in detail in the following text. Refer to the
simplified block diagram of Figure 1 for the control logic.
LPM COMP
+
1 = LP_MODE
0.6 V
70 mV
+
VOUT
SENSE
+
HOLD AMP
PFM
1.24 V
ERROR AMP
+
1=SLEEP
FB
PFM COMP
COMP
+
S
PFM
Q
R
+
PFM DISABLE COMP
1.22
+
0.2 V
UDG−98108
Figure 1. Simplified Block Diagram of Low Power and Pulse Mode Control Logic
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
power saving modes (continued)
VOUT
VDD BIAS
CONTROL
AND UVLO
+
VIN
+
85%
DMAX
PWM
OSC
3
VOUT
2
RSEN
4
RECT
19
RSEL
6
CHRG
12
ISENSE
VPUMP
MUX
A
14
R
B
A/B
ANTI−
CROSS
COND.
Q
S
SLOPECOMP
Q
R
Q
S
VGD
36 mV
START−UP
2.5 µS
+
+
VPUMP >2.5 V
LEB
VIN
VOUT>2.5 V
30 MHz AMP
ILIM COMP
+
0.15 V
1.24 V
VREF
1 = LP_MODE
+
0.6 V
10%−20% OF FULL
LOAD = LP_MODE
GND
CP
IZERO
13
CLK
RT
PUMP
SWITCH
CONTROL ADAPTIVE
ZERO
CURRENT
SENSING
VIN
1=SD
VOUT+2 V
SYNC/SD
8
PGND
20µs
DELAY
+
9
VGD
VIN
1.2 V
VIN
7
VPUMP
VDD
CONTROL
VDD
VPUMP
PWM
COMP
+
+
+
X10
5
0.3 V
1.24 V
ERROR AMP
15
+
+
70 mV
PFM COMP
PFM
PGND
17
FB
18
COMP
16
PFM
20
RSADJ
1=SLEEP
S
+
Q
R
PFM DISABLE
COMP
+
+
0.2 V
RESET
LOWBAT
1
UCC29422
ONLY
RESET/POR
1.22
+
10
1.18 V
11
+
1.24 V
VDET
UDG−98107
Figure 2. Detailed Block Diagram
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
low power mode
During normal operation, at medium to high load currents, the switching frequency remains fixed, programmed
by the resistor on the RT pin. At these higher loads, the gate drive output on the CHRG pin (for the N-channel
charge FET) is the higher of VIN or VPUMP. When the load current drops (sensed by a drop in the error amp
voltage), the UCC39421 automatically enters LP mode, and the gate drive voltage on the CHRG pin is reduced
to lower gate drive losses. This helps to maintain high efficiency at light loads where the gate drive losses begin
to dominate and the lowest possible Rds(on) is not required. If the load increases, normal or “high power” mode
resumes. The expression for gate drive power loss is given by equation (1). It can be seen that the power varies
as a function of the applied gate voltage squared.
P
GATELOSS
+
Q
ǒVGǓ
G
V
2
f
(1)
S
Where QG is the total gate charge and VS is the gate voltage specified in the MOSFET manufacturer’s data
sheet, VG is the applied gate drive voltage, and f is the switching frequency.
The nominal COMP voltage where LP mode is entered is 0.6 V. Given the internal offset and gain of the
current-sense amplifier, this corresponds to a peak switch current of:
I
PEAK
+
(0.6 * 0.3)
+ 0.03
R
K R
SENSE
SENSE
(2)
Where 0.6 V is the threshold for LP mode, 0.3 V is the internal offset, K is the nominal current-sense amplifier
gain of 10, and RSENSE is the value of the current-sense resistor. If the peak inductor current is below this value,
the UCC39421 enters LP mode and the gate drive voltage on the CHRG pin is equal to VIN. At peak currents
higher than this, the gate drive voltage is the higher of VIN or VPUMP.
PFM mode
At very light loads, the UCC39421 enters PFM mode. In this mode, when the error amplifier output voltage drops
below the PFM threshold, the controller goes into sleep mode until VOUT has dropped slightly (30 mV measured
at the feedback pin). At this time, the controller turns back on and operates at fixed frequency for a short duration
(typically a few hundred microseconds) until the output voltage has increased and the error amplifier output
voltage has dropped below the PFM threshold once again. Then the converter turns off and the cycle repeats.
This results in a very low duty cycle of operation, reducing all losses and greatly improving light load efficiency.
During sleep mode, most of the circuitry internal to the UCC39421 is powered down, reducing quiescent current
and maximizing efficiency.
The peak inductor current at which this mode is entered is user programmable by setting the voltage on the PFM
pin. This can be done with a single resistor in series with the feedback divider, as shown in the application
diagrams. The nominal peak current threshold for PFM mode is defined by the equation:
I
PEAK
^
ǒ
Ǔ
1.25 R1 * 0.3
ǒR1)R2Ǔ
K
R
(3)
SENSE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
PFM mode (continued)
Where 0.3 V is the internal offset and K is the nominal current-sense amplifier gain of 10 and RSENSE is the value
of the current-sense resistor. Note that in this case, the PFM pin voltage is set by the R1/R2 resistive divider
off of the FB pin, which is regulated to 1.25 V.
During sleep mode, the COMP pin is forced to 70 mV above the PFM pin voltage. This minimizes error amplifier
overshoot when coming out of sleep mode, and prevents erroneously tripping the PFM comparator.
disabling PFM mode
The user may disable PFM mode by pulling the PFM pin below 0.2 V. In this case, the UCC39421 remains on,
in fixed frequency operation at all load currents. The PFM pin can also be driven, through a resistive divider,
off of an output from the system controller. This allows the system controller to prepare for an expected step
increase in load, improving the converter’s large signal transient response. An example of this is shown in
Figure 3.
UCC39421
ENABLE OUTPUT
FROM CONTROLLER
R2
PFM 7
R1
Figure 3. Driving the PFM Pin From a Controller Output
choosing a topology and optimal synchronous rectifier
The UCC39421 is designed to be very flexible, and can be used in boost, flyback and SEPIC topologies. It can
operate from input voltages between 1.8 V and 8.0 V. Output voltages can be between 2.5 V and 8.0 V. It can
also drive either N- or P-channel MOSFET synchronous rectifiers. Table 1 can be used to select the appropriate
topology for a given combination of input and output voltage requirements. Although it is designed to operate
as a peak current mode controller, it can also be configured for voltage mode control. This is discussed in a later
section.
The user can program the gate drive output on the RECT pin for N-channel MOSFETs by grounding the RSEL
pin, or for P-channel MOSFETs by connecting the RESEL pin to VIN. Table 2 is used to determine whether an
N- or P-channel synchronous rectifier should be used.
Note: In all cases, low-voltage-logic MOSFETs should be used to achieve the lowest possible on-resistance
for the highest efficiency.
The application diagrams in Figures 4 through 8 illustrate the use of the UCC39421 in all the topologies, using
N- and P-channel rectifiers. They are be discussed in detail in the next section.
10
POST OFFICE BOX 655303
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SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
choosing a topology and optimal synchronous rectifier (continued)
Note that the higher the frequency of operation, the more critical the MOSFET gate charge becomes for
efficiency, particularly at light loads. However, high load currents demand lower Rds(on), which tends to
increase gate charge. These two parameters should be balanced. At lower frequencies, the gate charge
becomes less important, at 1 MHz or more, it is critical.
Table 1. SELECTING TOPOLOGY BASED ON INPUT AND OUTPUT VOLTAGE REQUIREMENTS
Cell Type
Nunber of Cells
Alkaline or NiCd, NiMH
Li-Ion
2
VIN Range
1.8 V to 3.0 V
3
2.7 V to 4.5 V
1
2.5 V to 4.2 V
VOUT
3.0 < V < 8.0
Topology
2.5 < V < 3.9
Flyback or SEPIC
Boost
4.5 < V < 8.0
Boost
V > 8.0
Non−synchronous boost
2.5 < V < 3.6
Flyback or SEPIC
4.2 < V < 8.0
Boost
V > 8.0
Non−synchronous boost
boost topology
The boost topology is simple and efficient, and should be used whenever the desired output voltage is greater
than the maximum input voltage.
boost using two n-channel MOSFETs
A boost converter using two N-channel MOSFETs is shown in Figure 4. This configuration is optimal for output
voltages below 4 V, where the output voltage may not be high enough to provide optimal gate drive for a
P-channel MOSFET. Note that in this case, a charge pump is required to provide proper gate drive levels. This
is easily accomplished by adding an external diode and a capacitor, as shown. The diode connects from the
output voltage to the CP pin. It should be an ultrafast or a Schottky diode. A 0.1-µF ceramic capacitor is
connected from the drain of the charge FET to the CP pin. This is the “flying” capacitor that charges to (VOUT
– VDIODE) every time the charge FET is on. A charge pump reservoir capacitor is connected from the VPUMP
pin to ground. It should be at least 1µF. A high-speed active rectifier inside the UCC39421 charges the pump
capacitor from the CP pin. The charge pump voltage is:
V
PUMP
^2
V
(4)
OUT
For a block diagram of the charge pump logic, refer to Figure 12.
Note: A charge pump should not be used at output voltages over 4.0 V to avoid pump voltages exceeding 8 V.
For other applications, where the charge pump is not required, the CP pin should be grounded and the pin
should be connected to either VOUT or VIN, whichever is greater.
POST OFFICE BOX 655303
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SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
boost using two n-channel MOSFETs
+VIN
+1.8 V
3.2 V
L1
COILTRONICS
CTX5−2
+CIN
100 µF
10 V
UCC39421
1k
1
Q2 (N)
VOUT
+3.3 V
0.1µF
DPUMP
1N4148
16
CPOLE
2
COUT
RSEL
RSEN
RCOMP
VOUT
COMP
15
FB
14
PFM
13
RG2 4.7
CFLY 0.1 µF
Q1
(N)
RSENSE
0.025
3
VGRECT
4
PGND
R2
41 k
1%
R1
20 k
1%
RG1
4.7
5
GND
CHRG
12
RT
100 k
CPUMP1 µF
6
+VIN
CCOMP
R3
100 k
1%
RT
11
SYNC/SD
10
ISENSE
9
VPUMP
7
CP
8
VIN
C5
0.1 µF
RSLOPE
1.5 k
UDG−98116
Figure 4. Application Diagram for the Boost Topology Using the N-channel Synchronous Rectifier
Table 2. SELECTING SYNCHRONOUS RECTIFIER BASED ON TOPOLOGY AND OUTPUT VOLTAGE
Topology
Boost
VOUT
3.0 < V < 8.0
V < 4.0
N-channel (low voltage logic)
Note: Requires a diode and a capacitor for the charge pump
V > 8.0
Non-synchronous
Note: Use Schottky rectifier (See Figure 16)
2.5 < V < 3.0
N-channel (low voltage logic)
Note: Requires a diode and a capacitor for the charge pump
3.0 < V < 8.0
N-channel (low voltage logic)
3.0 < V < 8.0
P-channel (low voltage logic)
Flyback
SEPIC
12
Synchronous Rectifier
P-channel (low voltage logic)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
boost using N- and P-channel MOSFETs
For output voltages greater than the input and greater than about 3.0 V, a P-channel may be used for the
synchronous rectifier. This configuration is shown in Figure 5. In this case, the VPUMP pin should be connected
to VOUT. This configuration can be used for a 3.3 V output if a low voltage logic MOSFET is used.
relating peak inductor current to average output current for the boost converter
For a continuous mode boost converter, the average output current is related to the peak inductor current by
the following:
I
PEAK
+
ǒ
I
OUT
(1 * D)
Ǔ
) di
2
(5)
where D is the duty cycle and the inductor ripple current, di, is defined as:
t
di + ON
V
L
IN + D
V
f
IN
L
(6)
where f is the switching frequency and L is the inductor value. The duty cycle is defined as:
D+
ǒ
V
O
*V
V
Ǔ
IN
O
(7)
Substituting equations (6) and (7) into equation (5) yields:
I
PEAK
+
I
ǒ ǒ
1*
OUT
V *V
IN
O
V
O
ǓǓ
)
V
2
IN
f L
ǒ
V
O
*V
V
O
Ǔ
IN
(8)
Note that in these equations, the voltage drop across the rectifier has been neglected.
POST OFFICE BOX 655303
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13
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
relating peak inductor current to average output current for the boost converter
VIN
1.8 V
TO
4.8 V
CIN1
10 µF
16V
L1
2.2 µH
1
+5 V
0A
TO
1A
COUT2
10 µF
16V
COUT1
10 µF
16V
C6
0.1 µF
Q1B
Si6803
(P)
C1
10 pF
UCC39421
R7
1k
Q1A
Si6803
(N)
RSEN
RSEL
16
R4
100 k
2
VOUT
3
VGRECT
4
PGND
5
CHRG
COMP
15
FB
14
PFM
13
GND
C2
470 pF
R1
15 k
1%
R2
15 k
1%
R3
15 k
1%
12
R4
100 k
RS
0.025
6
VPUMP
7
CP
8
VIN
C4
0.1 µF
RT
11
SYNC/SD
10
ISENSE
+VIN
9
R5
1M
SYNC/
SHUDOWN
INPUT
C5
0.1 µF
R6
1.5 k
UDG−98117
Figure 5. Application Diagram for the Boost Topology Using a P-channel Synchronous Rectifier
flyback topology using n-channel MOSFETs
A flyback converter using the UCC39421 is shown in Figure 6. It uses a standard two-winding coupled inductor
with a 1:1 turns ratio. The advantage of this topology is that the output voltage can be greater or less than the
input voltage, as shown in Table 1. For example, this is ideal for generating 3.3 V from a Lithium-Ion cell. Note
that RC snubbers are placed across the primary and secondary windings to reduce ringing due to leakage
inductance. These are optional, and may not be required in the application.
Note that for converters where VIN and VOUT may both be below 3 V, a charge pump is needed to provide
adequate gate drive. This is illustrated in the example if Figure 7.
14
POST OFFICE BOX 655303
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SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
flyback topology using n-channel MOSFETs (continued)
VIN
2.5 V TO 8.0 V
+ CIN
100 µF
10 V
10
470 pF
L1A
COILTRONICS
CTX5−2
UCC39421
1k
1
2
L1B
VOUT
3.3 V
0.1 µF
10
470 pF
COUT
+
RSEN
RSEL
Q1B
Si9802
(N)
CPOLE
RCOMP
VOUT
COMP
15
FB
14
RG2 4.7
Q1A
Si9802
(N)
16
3
VGRECT
4
PGND
R2
41 k
1%
PFM 13
R1
20 k
1%
RG1
4.7
5
CCOMP
R3
100 k
1%
GND 12
CHRG
RT
100 k
RSENSE
0.05 Ω
6
VPUMP
7
CP
8
VIN
RT
11
SYNC/SD 10
ISENSE
0.1 µF
+VIN
9
C5
0.1 µF
RSLOPE
1.5 k
UDG−98113
Figure 6. Application Diagram for the Flyback Topology Using the N-channel Synchronous Rectifier
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
flyback topology using n-channel MOSFETs (continued)
VIN
+1.8 V TO 4.2 V
+
CIN
100µF
10V
L1A
COILTRONICS
CTX5−2
UCC39421
1k
L1B
VOUT
2.5 V
1
RSEN
2
VOUT
3
VGRECT
4
PGND
RSEL 16
RCOMP
470 pF
COUT
+
D1
1N4148
RG2 4.7
Q1A
Si9802
(N)
Q1B
Si9802
(N)
CCOMP
R2
41 k
1%
FB 14
PFM 13
R1
20 k
1%
RG1
4.7
5
R3
100 k
1%
COMP 15
0.1µF
10
CPOLE
CHRG
GND 12
RT
100 k
RSENSE
0.05Ω
6
VPUMP
7
CP
8
VIN
0.1µF
RT 11
SYNC/SD 10
ISENSE 9
+VIN
0.1µF
RSLOPE 1.5 k
RBIAS 180 k
UDG−98211
Figure 7. Flyback Converter Using Charge Pump Input for Low Voltage Operation
relating peak inductor current to average output current for the flyback converter
For a continuous mode flyback converter, the average output current is related to the peak inductor current by
the following:
I
PEAK
+
ǒ
I
OUT
(1 * D)
Ǔ
) di
2
(9)
where D is the duty cycle and the inductor ripple current, dI, is defined as:
t
di + ON
V
L
IN + D
V
f
IN
L
(10)
where f is the switching frequency and L is the inductor value. The duty cycle is defined as:
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
relating peak inductor current to average output current for the flyback converter (continued)
D+
ǒ
V
V
IN
O
)V
Ǔ
(11)
O
Substituting equations (10) and (11) into equation (9) yields:
I
PEAK
+
I
ǒ ǒ
1*
OUT
V
V
O
)V
IN
O
ǓǓ
)
V
2
ǒ
IN
f L
V
V
O
)V
IN
Ǔ
(12)
O
Figure 7 shows an example of a converter where both VIN and VOUT may be quite low in voltage. In this case,
a diode has been added to peak detect the voltage on the drain of the charge FET and use it for the pump input
voltage. This is used to drive the gates of the FETs. To assure that the pump voltage is used (rather than VIN,
which may be low), resistor RBIAS has also been added to the ISENSE input to inhibit LP mode. This technique
is discussed further in the section Changing the Low Power Threshold.
VIN
1.8 TO 6.0V
+ CIN
100µF
10V
L1A
UCC39421
10µF 16V
1k
VOUT
3.3V
1
Q2
(P)
RSEN
RSEL
16
CPOLE
RCOMP
L1B
10µF
+ 10V
2
VOUT
3
VGRECT
4
PGND
COMP
15
FB
14
0.1µF
Q1
Si9802
(N)
5
CHRG
6
VPUMP
CCOMP
R3
100k
1%
R2
41k
1%
PFM 13
R1
20k
1%
GND 12
RT
47k
RT
11
1M
0.1µF
RSENSE
0.05Ω
SYNC/SD 10
7
CP
8
VIN
ISENSE
+VIN
SYNC
INPUT
9
0.1µF
RSLOPE 1.5k
UDG−98214
Figure 8. Application Diagram for the SEPIC Technology Using a P-channel Synchronous Rectifier
POST OFFICE BOX 655303
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17
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
SEPIC topology using N- and P-channel MOSFETs
The UCC39421 may also be used in the SEPIC (single-ended primary inductance converter) topology. This
topology, which is similar to the flyback, uses a capacitor to aid in energy transfer from input to output. This
configuration is shown in Figure 8. The N-channel synchronous rectifier has been changed to a P-channel and
moved to the other end of the inductor’s secondary winding, and a new capacitor has been placed across the
dotted ends of the two windings. The SEPIC topology offers the same advantage of the flyback in that it can
generate an output voltage that is greater or less than the input voltage.
However, it also offers improved efficiency. Although it requires an additional capacitor in the power stage, it
greatly reduces ripple current in the input capacitor and improves efficiency by transferring the energy in the
leakage inductance of the coupled inductor to the output. This also provides snubbing for the primary and
secondary windings, eliminating the need for RC snubbers. Note that the capacitor must have low ESR, with
sufficient ripple current rating for the application. Another advantage of the SEPIC is that the inductors do not
have to be on the same core.
PWM duty cycle and slope compensation
All boost and flyback converters using peak current mode control are susceptible to a phenomenon known as
subharmonic oscillation when operated in the continuous conduction mode beyond 50% duty cycle. Continuous
conduction mode (CCM) means that the inductor current never goes to zero during the switching cycle. For a
CCM boost converter, the required duty cycle for a given input and output voltage (neglecting voltage drops
across the MOSFET switches) is given by equation (7). This is shown graphically for a number of common
output voltages in Figure 9. For example, it can be seen that for a 3.3-V output (using the boost topology) slope
compensation is not required because the duty cycle never exceeds 50%.
For the flyback topology, using a coupled inductor with a 1:1 turns ratio, the duty cycle is defined by
equation (11). This is shown graphically for a number of common output voltages in Figure 10.
To prevent subharmonic oscillation beyond 50% duty cycle, a technique called slope compensation is used,
which modifies the slope of the current ramp. This is accomplished by adding a part of the timing ramp to the
current-sense input. In the UCC39421, this can be done by simply adding a resistor in series with the ISENSE
input. A current is sourced within the IC which is proportional to the internal timing ramp voltage. The value of
the resistor determines the amount of slope compensation added.
The slope compensation output current at the ISENSE pin is equal to:
I
SLOPE
+ 1 Ańm sec
R
T
(13)
where RT is the timing resister in ohms (Ω).
The required slope compensation resistor for a boost configuration is given by the equation:
R
SLOPE
+
ǒ
V
OUT
*2
V
INǒminǓ
Ǔ
R
SENSE
R
T
(14)
L
where RSENSE is the current-sense resistor value in ohms (Ω) and L is the inductor value in microhenries (µH).
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
PWM duty cycle and slope compensation (continued)
For a flyback topology, using a 1:1 turns ratio, the equation becomes:
R
SLOPE
+
ǒ
V
OUT
*V
INǒminǓ
Ǔ
R
SENSE
R
T
15)
L
If the converter is operated in the discontinuous conduction mode (inductor current drops to zero), no slope
compensation is required. The point at which this mode boundary occurs is a function of switching frequency,
input voltage, output voltage, load current, and inductor value. However, in general the converter is more
efficient when operated in the continuous conduction mode due to the lower peak currents.
CCM BOOST CONVERTER DUTY CYCLE
vs
INPUT VOLTAGE
CCM FLYBACK CONVERTER DUTY CYCLE
vs
INPUT VOLTAGE
80%
70%
60%
70%
VOUT = 5.0 V
40%
VOUT = 5 V
Duty Cycle
Duty Cycle
50%
30%
60%
VOUT = 3.3 V
50%
VOUT = 3.0 V
20%
40%
10%
VOUT = 3.3 V
0%
2
3
4
VOUT = 2.5 V
30%
2
2.5
3
3.5
4
4.5
VIN − Input Voltage − V
VIN − Input Voltage − V
Figure 10
Figure 9
voltage mode control
The UCC39421 can be operated as a voltage mode controller by connecting a 5.6-kΩ resistor from the ISENSE
pin to ground. The internal current source generates an artificial ramp voltage on this input. In this case, no slope
compensation is required, and no current-sense resistor is required in series with the source of the N-channel
MOSFET. A typical application diagram is shown in Figure 11. However, in this configuration there is no
overcurrent protection. In addition, the pulse and low power modes, designed to increase efficiency at light
loads, operates at different load currents. This is because the internal error amplifier’s output voltage is no longer
a direct function of load current, but rather of duty cycle. When operating in CCM, the duty cycle is largely a
function of input and output voltage, not load current. At light enough loads however, the converter goes into
discontinuous mode and the error amplifier voltage drops low enough to activate the low power and pulse
modes.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
voltage mode control (continued)
VIN
1.8 V TO 4.5 V
+ CIN
100 µF
10V
L1
UCC39421
VOUT
5.0 V
1k
1
0.1 µF
10V
+
COUT
Q2
(P)
RSEN
RSEL
16
CPOLE
RCOMP
0.1 µF
2
VOUT
3
VGRECT
4
PGND
RG2
4.7
COMP
15
FB
14
PFM
13
CCOMP
R2
41 k
1%
R1
20 k
1%
RG1
4.7
Q1
(N)
5
CHRG
6
VPUMP
7
CP
8
VIN
0.1 µF
+VIN
GND
R3
100 k
1%
12
RT
100 k
RT
11
SYNC/SD
10
ISENSE
9
RSLOPE
5.6 k
0.1 µF
UDG−98215
Figure 11. Typical Boost Configuration Using Voltage Mode Control
start up
The UCC39421 incorporates a unique feature to help it start-up at low input voltages. If the input voltage is below
2.5 V at start-up, a separate control circuit takes over until VOUT or VPUMP gets above 2.5 V. In this mode, the
charge MOSFET is turned on for 5 µs, or until the voltage on the ISENSE pin reaches 36 mV, whichever occurs
first. The charge MOSFET then remains off for a fixed time of 2.5 µs, and the body diode of the synchronous
rectifier MOSFET is used to supply current to the output. This cycle repeats until either VOUT or VPUMP exceeds
2.5 V. This results in constant off time control, with a minimum switching frequency of approximately 120 kHz.
During this low voltage start-up mode, all other internal circuitry is off, including the synchronous rectifier drive
and the slope compensation current source. The peak inductor current during this mode is limited to:
I
20
PEAK
+
0.036
R
(16)
SENSE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
start up (continued)
If input voltages below 2.5 V are expected, it is important to use a low voltage logic N-channel MOSFET (with
a threshold voltage around 1 V or less) to ensure start-up at full load.
A block diagram of the low voltage start-up logic is shown in Figure 12.
VIN
L
VPUMP
UCC39421
−
CPUMP
+
CFLY
2.5 V < VPUMP
2.5 V < V PUMP
2.5 V < VOUT
LPM < V COMP
NORMAL PWM
A
B
MUX
VIN
VPUMP
DBODY
VOUT
COUT
A/B
5−µsec
DELAY
Q
DRIVER
S
RSENSE
+
R
−
2.5−µsec
DELAY
+
Q
36 mV
UDG−98121
Figure 12. Symplified Diagram of Low Voltage Start−Up and Charge Pump Control Logic
anticross-conduction and adaptive synchronous rectifier commutation logic
When operating in the continuous conduction mode (CCM), the charge MOSFET and the synchronous rectifier
MOSFET are simply driven out of phase, so that when one is on the other is off. There is a built-in time delay
of about 30 ns to prevent any cross-conduction.
In the event that the converter is operating in the discontinuous conduction mode (DCM), the synchronous
rectifier needs to be turned off sooner, when the rectifier current drops to zero. Otherwise, the output begins
to discharge as the current reverses and goes back through the rectifier to the input. (This obviously cannot
happen when using a conventional diode rectifier). To prevent this, the UCC39421 incorporates a high-speed
comparator that senses the voltage on the synchronous rectifier (using the RSEN input) for purposes of
commutation. In the boost and SEPIC topologies, the synchronous rectifier is turned off when the voltage on
the RSEN pin goes negative with respect to VOUT. For this reason, it is important to have the VOUT pin well
decoupled.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
anticross-conduction and adaptive synchronous rectifier commutation logic (continued)
In the flyback topology however (using a ground referenced N-channel MOSFET rectifier), the rectifier voltage
is sensed on the MOSFET drain, with respect to ground rather than VOUT. The voltage polarity in this case is
opposite that of the boost and SEPIC topologies. This problem is solved with the adaptive logic within the
UCC39421. During each charge cycle, while the N-channel charge FET is on, a latch is set if the voltage on the
RSEN pin exceeds VIN/2. This indicates a flyback topology, since this node is be equal to or greater than VIN
at this time. In the case of the boost and the SEPIC, the voltage at the RSEN input is near or below ground, and
the latch is not be set. This allows the UCC39421 to sense which topology is in use and adapt the synchronous
rectifier commutation logic accordingly. Note that the RSEN input must have a series resistor to limit the current
when going below ground. Values less than or equal to 1 kΩ are recommended to prevent time delay due to
stray capacitance.
current-sense amplifier and leading edge blanking
The UCC39421 includes a high-speed current-sense amplifier with a nominal gain of 10 to minimize losses
associated with the current-sense resistor. The amplifier was designed to provide good response and minimal
propagation delay, allowing switching frequencies at 2 MHz. The current-sense resistor should be chosen to
provide a maximum peak voltage of 100 mV at full load, with the minimum input voltage.
A leading-edge blanking time of 40 ns is provided to filter out leading-edge spikes in the current-sense
waveform. In most applications, this eliminates the need for a filter capacitor on the ISENSE pin.
overcurrent protection
The UCC39421 includes a peak current limit function. If the voltage on the ISENSE pin exceeds 0.15 V after
the initial blanking period, the pulse is terminated and the charge MOSFET is turned off.
sync/shutdown input
The SYNC/SD pin has two functions; it may be used to synchronize the UCC39421’s switching frequency to
an external clock, or to shutdown the IC entirely. In shutdown, the quiescent current is reduced to just a few
microamps.
To synchronize the internal clock to an external source, the SYNC/SD pin must be driven high, above 2.0 V
minimum. The circuitry syncs to the rising edge of the input, the pulse width is not critical.
To shutdown the converter, the SYNC/SD pin must be held high (above 2.0 V) for a minimum of 29 µs.
This pin should be grounded if not used.
changing the low power mode threshold
For some applications the user may want to lower the low power (LP) mode threshold, or even eliminate this
feature altogether. For example, if a boost topology is being used, and the input voltage is below 2.5 V, the gate
drive to the charge FET may want to be derived from the pump (or output) voltage under all load conditions,
rather than from VIN. This means the converter would never be allowed to operate in LP mode.
22
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SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
changing the low power mode threshold (continued)
Although the LP mode threshold is internally fixed at 0.6 V (referenced to the pin), the point at which the LP
mode is entered can be easily modified by adding a single resistor, as shown in Figure 13. Resistor RBIAS forms
a divider with RSLOPE (used for slope compensation) and adds a dc offset to the current-sense input, raising
the output voltage of the sense amplifier and fooling the LP mode comparator into thinking the load is higher
than it is. The required bias resistor to transition out of LP mode for a given peak current can be calculated using
the following equation:
R
BIAS
+
R
SLOPE
0.03 * I
PEAK
V
OUT
R
SENSE
(17)
UCC39421
600 mV
FB
LP MODE
+
VIN
17
1.24 V
CONTROL
LOGIC
+
COMP 18
VOUT
CHRG
DRIVE
RSLOPE
+
+
PWM
COUT
6
X10
300 mV
12
ISENSE
RBIAS
RSENSE
UDG−98213
Figure 13. Modifying Low Power (LP) Mode Threshold
Due to the current-sense amplifier gain of 10 and the internal offset of 300 mV, an offset of just 30 mV or more
at the ISENSE pin inhibits the LP mode altogether. Note that inhibiting LP mode does not prevent PFM from
working, as long as the PFM pin is set to a voltage higher than:
ǒ10
V
Ǔ ) 0.3V
18)
ISENSE
programming the PWM frequency
Some applications may want to remain in a fixed frequency mode of operation, even at light load, rather than
going into PFM mode. This lowers efficiency at light load. One way to improve the efficiency while maintaining
fixed frequency operation is to lower the PWM frequency under light load conditions. This can be easily done,
as shown in Figure 14. By adding a second timing resistor and a small MOSFET switch, the host can switch
between two discrete frequencies at any time.
POST OFFICE BOX 655303
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23
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
non-synchronous boost for higher output voltage applications
The UCC39421 can also be used in non-synchronous applications to provide output voltages greater than 8
volts from low voltage inputs. An example of a 12-V boost application is shown in Figure 16. Since none of the
IC pins are exposed to the boosted voltage, the output voltage is limited only by the ratings of the external
MOSFET, rectifier, and filter capacitor. At these higher output voltages, good efficiency is maintained since the
rectifier drop is small compared to the output voltage. Note that PFM mode can still be used to maintain high
efficiency at light load. Typical efficiency causes are shown in Figure 15.
Since all the power supply pins (VIN, VOUT, VPUMP) operate off the input voltage, it must be >2.5 V and high
enough to assure proper gate drive to the charge FET.
VOUT
UCC39421
1
RSEN
RSEL
16
2
VOUT
COMP
15
3
VGRECT
FB
14
4
PGND
5
CHRG
6
VPUMP
7
8
R1
R2
PFM
13
GND
12
RT
11
CP
SYNC/SD
10
VIN
ISENSE
9
RT2
RT1
2N7002
FREQUENCY
CONTROL
Figure 14. Changing the PWM Frequency
24
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UDG−98216
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
non−synchronous boost for higher output voltage applications (continued)
NON-SYNCHRONOUS BOOST EFFICIENCY
95%
VIN = 5 V
90%
Efficiency
85%
VIN = 3.3 V
80%
75%
70%
f = 550 kHz
L = 6.8 mH
DT3316P−682 (IRF7601) MBR0530
VPFM = 0.5 V
65%
60%
0.001
0.01
0.1
IOUT − Output Current − A
1
Figure 15
POST OFFICE BOX 655303
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25
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
non−synchronous boost for higher output voltage applications (continued)
3.0 V TO 8.0V
CIN
100 µF
16V
+
L1
6.8 µH
R3
249 K
1%
UCC39421
1
RSEL 16
RSEN
CPOLE
12V
COUT
100 µF
16V
+
2
D1
MBR0530T
1.25 V
COMP 15
VOUT
R2
17.8 K
1%
RCOMPC
COMP
N/C
3
FB 14
VGRECT
4 PGND
PFM 13
5
GND 12
R1
11 K
1%
RG1
4.7
Q1
(N)
RSENSE
0.05 Ω
6
+VIN
VGCHRG
VPUMP
7
CP
8
VIN
RT
RT
100 K
11
SYNC/SD 10
ISENSE
9
0.1 µF
RSLOPE
1.5 K
UDG−98212
Figure 16. Non-Synchronous Boost Converter for Higher Output Voltages
UCC39422 features
The UCC39422 is a 20-pin device that adds a reset function and an uncommitted comparator to the UCC39421.
A simplified diagram of the reset circuit is shown in Figure 17.
g m=1/26 k
FB
1
RESET
17
+
+
S
Q
R
Q
V IN
8 pF
1.175 V
1.175 V
1 µA
RSADJ
20
C RESET
+
1.175 V
Figure 17. Reset Circuitry
26
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UDG−98206
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
The reset circuit monitors the voltage at the feedback (FB) pin and issues a reset if the feedback voltage drops
below 1.175 V. This represents a 6% drop in output voltage. Monitoring the voltage internally at the FB pin
eliminates the need for another external voltage divider. The RESET output is an open-drain output that is active
low during reset. It stays low until the feedback voltage is above 1.175 V for a period of time called the reset
pulse width, which is user programmable. An external capacitor on the RSADJ pin and an internal 1-µA current
source determine the reset pulse width, according to the following equation:
t
RESET
+C
RESET
(19)
1.18
where tRESET is the reset pulse width in seconds, and CRESET is the capacitor value in microFarads (µF).
An adaptive glitch filter is included to prevent nuisance trips. This is implemented using a gm amplifier to charge
an 8-pF capacitor to 1.175 V before declaring a reset. This provides a delay which is inversely proportional to
the magnitude of the feedback voltage error. The delay time is approximated by the following equation:
t
DELAY
^
0.25
1.175 * V
(20)
ms
FB
where tDELAY is the filter delay time in microseconds. Note that the maximum current from the gm amplifier is
limited to 2 µA, limiting the minimum time delay to 4.8 µs.
A typical application schematic using the UCC39422 is shown in Figure 18. In this example, R1 and R2 have
been selected to trip the LOWBAT output when VIN drops below 2.0 V. Note that the RESET and LOWBAT
outputs are open drain and require a pullup.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
UCC39422 features (continued)
VIN
RESET* (ACTIVE LOW)
+CIN
UCC39422
L1
1
RSETB
2
RSEN
3
VOUT
CRESET
RSADJ
20
RSEL
19
COMP
18
FB
17
PFM
16
GND
15
1k
Q1 (P)
+VOUT
+ C OUT
RCOMP
RG
4
5
PGND
6
CHRG
RG
RT
100 k
RSENSE 0.1 µF
7
VPUMP
8
CP
9
VIN
RT
12
R2
150 k
VDET
0.1 µF
10
14
SYNC/SD 13
ISENSE
+VIN
CCOMP
VGRECT
0.1 µF
Q1 (N)
CPOLE
11
+VIN
R1
250 k
LOWBAT
47 pF
LOWBAT (ACTIVE HIGH)
THRESHOLD = 2.0 V
RSLOPE
Figure 18. Typical UCC39422 Application
28
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UDG−99034
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
selecting the inductor
The inductor must be chosen based on the desired operating frequency and the maximum load current. Higher
frequencies allow the use of lower inductor values, reducing component size. Higher load currents require larger
inductors with higher current ratings and less winding resistance to minimize losses. The inductor must be rated
for operation at the highest anticipated peak current. Refer to equation (8) and equation (12) to calculate the
peak inductor current for a boost or flyback design, based on VIN, VOUT, maximum load, frequency, and inductor
value. Some manufacturers rate their parts for maximum energy storage in microjoules (µJ). This is expressed
by:
E + 0.5
L
I
2
(21)
PEAK
where E is the required energy rating in microjoules. L is the inductor value in microhenries (µH) (with current
applied), and IPEAK is the peak current in amps that the inductor sees in the application. Another way in which
inductor ratings are sometimes specified is the maximum volt-seconds applied. This is given simply by:
E
V
T + IN
D
(22)
f
where ET is the required rating in V-µs, D is the duty cycle for a given VIN and VOUT, and f is the switching
frequency in MHz. Refer to equations (7) and (11) to calculate the duty cycle for a CCM boost or flyback
converter.
In any case, the inductor must use a low loss core designed for high-frequency operation. High-frequency ferrite
cores are recommended. Some manufacturers of off-the-shelf surface-mount designs are listed in Table 3. For
flyback and SEPIC topologies, use a two-winding coupled inductor. SEPIC designs can also use two discrete
inductors.
Table 3. MT COMMERCIAL INDUCTOR MANUFACTURERS
Coilcraft Inc. ⋅ (800) 322−2645.1102 Silver Lake RD, Cary, IL 60013
Coiltronics Inc. ⋅ (407) 241−7876 6000 Park of Commerce Blvd, Boca Raton, FL 33487
Dale Electronics, Inc. ⋅ (605) 665−9301East Highway 50, Yankton, SD 57078
Pulse Engineering Ltd. ⋅ (204) 633−4321300 Keewatin Street, Winnipeg, MB R2X 2R9
Sumida ⋅ Voice (65) 296−3388 ⋅ Fax (65) 293−3390 Block 996, Bendemeer Rd., #04−05/06 Singapore 33944
BH Electronics ⋅ (612) 894−9590 12219 Wood Lake Drive, Burnsville, MN 55337
Tokin America Inc. ⋅ (408) 432−8020155 Nicholson Lane, San Jose CA 95134
POST OFFICE BOX 655303
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29
SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
selecting the filter capacitor
The input and output filter capacitors must have low ESR and low ESL. Surface-mount tantalum, OSCONs or
multilayer ceramics (MLCs) are recommended. The capacitor selected must have the proper ripple current
rating for the application. Some recommended capacitor types are listed in Table 4.
Table 4. RECOMMENDED SMT FILTER CAPACITORS
Manufacturer
Part Number
Features
AVX
TPS series
Low ESR tantalum
Kemet
T410 series
Low ESR tantalum
Murata
GRM series
Low ESR ceramic
Sanyo
OSCON series
Low ESR organic
Sprague
591D series
Low ESR, low profile tantalum
594D series
Low ESR tantalum
Tokin
Y5U, Y5V Type
Low ESR ceramic
Taiyo Yuden
X5R Type
Low ESR ceramic
circuit layout and grounding
As with any high frequency switching power supply, circuit layout, hookup, and grounding are critical for proper
operation. Although this may be a relatively low-power, low-voltage design, these issues are still very important.
The MOSFET turn-on and turn-off times necessary to maintain high efficiency at high switching frequencies of
1 MHz or more result in high dv/dt and di/dts. This makes stray circuit inductance especially critical. In addition,
the high impedances associated with low-power designs, such as in the feedback divider, make them especially
susceptible to noise pickup.
layout
The component layout should be as tight as possible to minimize stray inductance. This is especially true of the
high-current paths, such as in series with the MOSFETs and the input and output filter capacitors.
The components associated with the feedback, compensation and timing should be kept away from the power
components (MOSFETs, inductor). Keep all components as close to the IC pins as possible. Nodes that are
especially noise sensitive are the FB and RT pins. Other sensitive pins are COMP and PFM.
grounding
A ground plane is highly recommended. The PGND pin of the UCC39421 should be close to the grounded end
of the current-sense resistor, the input filter cap, and the output filter cap. The GND pin should be close to the
grounded end of the RT resistor, the feedback divider resistor, the ISENSE capacitor (if used), and the
compensation network.
MOSFET gate resistors
The UCC39421 includes low-impedance CMOS output drivers for the two external MOSFET switches. The
CHRG output has a nominal resistance of 4 Ω, and the RECT has a nominal resistance of 2 Ω. For
high-frequency operation using low gate charge MOSFETs, no gate resistors are required. To reduce
high-frequency ringing at the MOSFET gates, low-value series gate resistors may be added. These should be
non-inductive resistors, with a value of 2 Ω to 10 Ω, depending on the frequency of operation. Lower values
results in better switching times, improving efficiency.
30
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APPLICATION INFORMATION
minimizing output ripple and noise spikes
The amount of output ripple is determined primarily by the type of output filter capacitor and how it is connected
in the circuit. In most cases, the ripple is be dominated by the ESR (equivalent series resistance) and ESL
(equivalent series inductance) of the capacitor, rather than the actual capacitance value. Low ESR and ESL
capacitors are mandatory in achieving low output ripple. Surface-mount packages greatly reduce the ESL of
the capacitor, minimizing noise spikes. To further minimize high frequency spikes, a surface mount ceramic
capacitor should be placed in parallel with the main filter capacitor. For best results, a capacitor should be
chosen whose self-resonant frequency is near the frequency of the noise spike. For high switching frequencies,
ceramic capacitors alone may be used, reducing size and cost.
For applications where the output ripple must be extremely low, a small LC filter may be added to the output.
The resonant frequency should be below the selected switching frequency, but above that of any dynamic loads.
The filter’s resonant frequency is given by:
f
RES
+
1
Ǹ
2p L
(23)
C
Where f is the frequency in Hz, L is the filter inductor value in Henries, and C is the filter capacitor value in Farads.
It is important to select an inductor rated for the maximum load current and with minimal resistance to reduce
losses. The capacitor should be a low-impedance type, such as a tantalum.
If an LC ripple filter is used, the feedback point can be taken before or after the filter, as long as the filter’s
resonant frequency is well above the loop crossover frequency. Otherwise, the additional phase lag makes the
loop unstable. The only advantage to connecting the feedback after the filter is that any small voltage drop
across the filter inductor is corrected for in the loop, providing the best possible voltage regulation. However,
the resistance of the inductor is usually low enough that the voltage drop is negligible.
POST OFFICE BOX 655303
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31
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
UCC29421N
ACTIVE
PDIP
N
16
20
None
CU SNPB
UCC29421PW
ACTIVE
TSSOP
PW
16
90
None
CU NIPDAU
Level-NA-NA-NA
Level-2-220C-1 YEAR
UCC29421PWTR
ACTIVE
TSSOP
PW
16
1
None
CU NIPDAU
Level-2-220C-1 YEAR
UCC29422N
ACTIVE
PDIP
N
20
18
None
CU SNPB
UCC29422PW
ACTIVE
TSSOP
PW
20
70
None
CU NIPDAU
Level-2-220C-1 YEAR
UCC29422PWTR
ACTIVE
TSSOP
PW
20
2000
None
CU NIPDAU
Level-2-220C-1 YEAR
UCC39421N
ACTIVE
PDIP
N
16
25
None
CU SNPB
UCC39421PW
ACTIVE
TSSOP
PW
16
90
None
CU NIPDAU
Level-2-220C-1 YEAR
UCC39421PWTR
ACTIVE
TSSOP
PW
16
2000
None
CU NIPDAU
Level-2-220C-1 YEAR
UCC39422N
ACTIVE
PDIP
N
20
18
None
CU SNPB
UCC39422PW
ACTIVE
TSSOP
PW
20
70
None
CU NIPDAU
Level-2-220C-1 YEAR
UCC39422PWTR
ACTIVE
TSSOP
PW
20
2000
None
CU NIPDAU
Level-2-220C-1 YEAR
Level-NA-NA-NA
Level-NA-NA-NA
Level-NA-NA-NA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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