INTEGRATED CIRCUITS DATA SHEET UMA1015M Low-power dual frequency synthesizer for radio communications Product specification Supersedes data of October 1994 File under Integrated Circuits, IC03 1995 Jun 22 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M FEATURES GENERAL DESCRIPTION • Two fully programmable RF dividers up to 1.1 GHz The UMA1015M is a low-power dual frequency synthesizer for radio communications which operates in the 50 to 1100 MHz frequency range. Each synthesizer consists of a fully programmable main divider, a phase and frequency detector and a charge pump. There is a fully programmable reference divider common to both synthesizers which operates up to 35 MHz. The device is programmed via a 3-wire serial bus which operates up to 10 MHz. The charge pump currents (gains) are fixed by an external resistance at pin 20 (ISET). The BiCMOS device is designed to operate from 2.6 V (3 Ni-Cd cells) to 5.5 V at low current. Digital supplies VDD1 and VDD2 must be at the same potential. The charge pump supply (VCC) can be provided by an external source or on-chip voltage doubler. VCC must be equal to or higher than VDD1. Each synthesizer can be powered-down independently via the serial bus to save current. It is also possible to power-down the device via the HPD input (pin 5). • Fully programmable reference divider up to 35 MHz • 2 : 1 or 1 : 1 ratio of selectable reference frequencies • Fast three-line serial bus interface • Adjustable phase comparator gain • Programmable out-of-lock indication for both loops • On-chip voltage doubler • Low current consumption from 3 V supply • Separate power-down mode for each synthesizer • Up to 4 open-drain output ports. APPLICATIONS • Cordless telephone • Hand-held mobile radio. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD1, VDD2 digital supply voltage VDD1 = VDD2 2.6 − 5.5 V VCC charge pump supply voltage external supply; doubler disabled; VCC ≥ VDD 2.6 − 6.0 V VCCvd charge pump supply from voltage doubler doubler enabled − 2VDD1 − 0.6 6.0 V IDDO1 +IDDO2 + ICCO operating supply current both synthesizers ON; doubler disabled; VDD1 = VDD2 = 5.5 V − 9.6 − mA IDD1pd + IDD2pd + ICCpd current in power-down mode per supply doubler disabled; VDD1 = VDD2 = 5.5 V − 0.01 − mA IDD1pd current in power-down mode from supply VDD doubler enabled; VDD1 = VDD2 = 3 V − 0.15 − mA fRFA, fRFB RF input frequency for each synthesizer 50 − 1100 MHz fXTALIN crystal input frequency 3 − 35 MHz fpc(min) minimum phase comparator frequency fRF = 50 to 1100 MHz; fXTALIN = 3 to 35 MHz − 10 − kHz fpc(max) maximum phase comparator frequency fRF = 50 to 1100 MHz; fXTALIN = 3 to 35 MHz − 750 − kHz Tamb operating ambient temperature synthesizer A 2.6 V ≤ VDD ≤ 5.5 V −30 − +85 °C synthesizer B 2.6 V ≤ VDD ≤ 4.5 V −30 − +85 °C synthesizer B 2.6 V ≤ VDD ≤ 5.0 V 0 − +85 °C 1995 Jun 22 2 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M ORDERING INFORMATION PACKAGE TYPE NUMBER UMA1015M/C2 PINS PIN POSITION MATERIAL CODE 20 SSOP20 plastic SOT266-1 BLOCK DIAGRAM BB BB Fig.1 Block diagram. 1995 Jun 22 3 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M PINNING SYMBOL PIN DESCRIPTION P1 1 output Port 1 P2 2 output Port 2 CPA 3 charge-pump output synthesizer A VDD1 4 digital supply voltage 1 HPD 5 hardware power-down (input LOW = power-down) RFA 6 RF input synthesizer A DGND 7 digital ground fXTALIN 8 common crystal frequency input from TCXO P3 9 output Port 3 fXTALO 10 open-drain output of fXTAL signal CLK 11 programming bus clock input DATA 12 programming bus data input E 13 programming bus enable input (active LOW) VDD2 14 digital supply voltage 2 RFB 15 RF input synthesizer B AGND 16 analog ground to charge pumps CPB 17 charge pump output synthesizer B VCC 18 analog supply to charge pump; external or voltage doubler output P0/OOL 19 Port output 0/out-of-lock output ISET 20 regulator pin to set charge-pump currents Fig.2 Pin configuration. pre-amplifier to provide the clock input for the reference divider. This clock signal is also buffered and output on pin fXTALO (open drain). An extra divide-by-2 block allows a reference comparison frequency for synthesizer B to be half that of synthesizer A. This feature is selectable using the program bit SR. If the programmed reference divider ratio is R then the ratio for each synthesizer is as given in Table 1. FUNCTIONAL DESCRIPTION Main dividers Each synthesizer has a fully programmable 17-bit main divider. The RF input drives a pre-amplifier to provide the clock to the first divider bit. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from below 50 mV (RMS) up to 250 mV (RMS), and at frequencies up to 1.1 GHz. The high frequency sections of the divider are implemented using bipolar transistors, while the slower section uses CMOS technology. The range of division ratios is 512 to 131071. The range for the division ratio R is 8 to 4095. Opposite edges of the divider output are used to drive the phase detectors to ensure that active edges arrive at the phase detectors of each synthesizer at different times. This minimizes the potential for interference between the charge pumps of each loop. The reference divider consists of CMOS devices operating beyond 35 MHz. Reference divider There is a common fully programmable 12-bit reference divider for the two synthesizers. The input fXTALIN drives a 1995 Jun 22 4 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications Table 1 output is forced LOW). The lock condition output is software selectable (see Table 4). An out-of-lock condition is flagged when the phase error is greater than T00L, the value of which is approximately equal to 80 cycles of the relevant RF input. The out-of-lock flag is only released after 8 consecutive reference cycles where the phase error is less than T00L. The out-of-lock function can be disabled, via the serial bus, and the pin P0/OOL can be used as an output port. Three other port outputs P1, P2 and P3 (open-drain transistors) are also available. Synthesizer ratio of reference divider SR SYNTHESIZER A SYNTHESIZER B 0 R R 1 R 2R Phase comparators For each synthesizer, the outputs of the main and reference dividers drive a phase comparator where a charge pump produces phase error current pulses for integration in an external loop filter. The charge pump current is set by an external resistance RSET at pin ISET, where a temperature-independent voltage of 1.2 V is generated. RSET should be between 12 kΩ and 60 kΩ (to give an ISET of 100 µA and 20 µA respectively). The charge-pump current, ICP, can be programmed to be either (12 × ISET) or (24 × ISET) with the maximum being 2.4 mA. The dead zone, caused by finite switching of current pulses, is cancelled by an internal delay in the phase detector thus giving improved linearity. The charge pump has a separate supply, VCC, which helps to reduce the interference on the charge pump output from other parts of the circuit. Also, VCC can be higher than VDD1 if a wider range on the VCO input is required. VCC must not be less than VDD1. Serial programming bus A simple 3-line unidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLK and E (enable). The data sent to the device is loaded in bursts framed by E. Programming clock edges are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns inactive HIGH. This is allowed when CLK is in either state without causing any consequences to the register data. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programming data even during power-down of both synthesizers. Voltage doubler However when either synthesizer A or synthesizer B or both are powered-on, the presence of a TCXO signal is required at pin 8 (fXTALIN) for correct programming. If required, there is a voltage doubler on-chip to supply the charge pumps at a higher level than the nominal available supply. The doubler operates from the digital supply VDD1, and is internally limited to a maximum output of 6 V. An external capacitor is required on pin VCC for smoothing, the capacitor required to develop the extra voltage is integrated on-chip. To minimize the noise being introduced to the charge pump output from the voltage doubler, the doubler clock is suppressed (provided both loops are in-lock) for the short time that the charge pumps are active. The doubler clock (RF/64) is derived from whichever main divider is operating (synthesizer A has priority). While both synthesizers are powered down (and the doubler is enabled), the doubler clock is supplied by a low-current internal oscillator. The doubler can be disabled by programming the bit VDON to logic 0, in order to allow an external charge pump supply to be used. Data format Data is entered with the most significant bit first. The leading bits make up the data field, while the trailing four bits are an address field. The address bits are decoded on the rising edge of E. This produces an internal load pulse to store the data in the addressed latch. To ensure that data is correctly loaded on first power-up, E should be held LOW and only taken HIGH after having programmed an appropriate register. To avoid erroneous divider ratios, the pulse is inhibited during the period when data is read by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer. The data format and register bit allocations are shown in Table 2. Out-of-lock indication/output ports There is a lock detector on-chip for each synthesizer. The lock condition of each, or both loops, is output via an open-drain transistor which drives the pin P0/OOL (when out-of-lock, the transistor is turned on and therefore the 1995 Jun 22 UMA1015M 5 FIRST REGISTER BIT ALLOCATION p1 p2 p3 p4 p5 p6 dt16 dt15 dt14 X X VDON PO OLA OLB 0 0 SR p8 p13 p14 p15 p16 p17 dt4 dt3 dt2 dt1 dt0 sPDA sPDB P3 P2 P1 X X 0 0 0 1 SYNTHESIZER A MAIN DIVIDER COEFFICIENT MA0 0 1 0 0 R11 R0 0 1 0 1 MB0 0 1 1 0 0 0 0 0 dt13 dt12 MA16 0 p7 0 MB16 p9 p10 p11 p12 LAST DATA FIELD CRA CRB X X REFERENCE DIVIDER COEFFICIENT SYNTHESIZER B MAIN DIVIDER COEFFICIENT RESERVED FOR TEST(1) p18 p19 p20 p21 ADDRESS Note 1. The test register should not be programmed with any other values except all zeros for normal operation. Table 3 Bit allocation description SYMBOL DESCRIPTION 6 sPDA, sPDB software power-down for synthesizers A and B (0 = power-down) P3, P2, P1 and P0 bits output to pins 1, 2, 9 and 19 (1 = high impedance) VDON voltage doubler enable (1 = doubler enabled) OLA, OLB out-of-lock select; selects signal output to pin 19 (see Table 4) CRA, CRB charge pump A/B current to ISET ratio select (see Table 5) SR reference frequency ratio select (see Table 6) Table 4 Out-of-lock select OLA OLB OUTPUT AT PIN 19 0 0 P0 0 1 lock status of loop B; OOLB 1 0 lock status of loop A; OOLA 1 1 logic OR function of loops A and B Table 6 Reference division ratio CRA/CRB CURRENT AT PUMP SR SYNTHESIZER A SYNTHESIZER B 0 ICP = 12 × ISET 0 R R 1 ICP = 24 × ISET 1 R 2R Product specification Charge pump current ratio UMA1015M Table 5 Philips Semiconductors Bit allocation Low-power dual frequency synthesizer for radio communications 1995 Jun 22 Table 2 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M switched off, only the voltage doubler (if enabled) will remain active drawing a reduced current. An internal oscillator will drive the doubler in this situation. If both synthesizers have been in a power-down condition, then when one or both synthesizers are reactivated, the reference and main dividers restart in such a way as to avoid large random phase errors at the phase comparator. Power-down modes The device can be powered down either via pin HPD (active LOW = power-down) or via the serial bus (bits SPDA and SPDB, logic 0 = power-down). The synthesizers are powered up when both hardware and software Power-down signals are at logic 1. When only one synthesizer is powered down, the functions common to both will be maintained. When both synthesizers are LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD1, VDD2 DC range of digital power supply voltage with respect to DGND −0.3 +6.0 V VCC DC charge pump supply voltage with respect to AGND −0.3 +6.0 V ∆VCC-DD difference in voltage between VCC and VDD1, VDD2 −0.3 +6.0 V Vn DC voltage at pins 1, 2, 5, 6, 8 to 15, 19 and 20 with respect to DGND −0.3 VDD1 + 0.3 V V3, 17 DC voltage at pins 3 and 17 with respect to AGND −0.3 VCC + 0.3 V ∆VGND difference in voltage between AGND and DGND (these pins should be connected together) −0.3 +0.3 V Tstg storage temperature −55 +125 °C Tamb operating ambient temperature −30 +85 °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 1995 Jun 22 7 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M CHARACTERISTICS VDD1 = VDD2 = 2.6 to 5.5 V; VCC = 2.6 to 6.0 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply; (VDD1, VDD2 and VCC) voltage doubler disabled, external supply on VCC VDD1, VDD2 digital supply voltage VDD1 = VDD2 2.6 − 5.5 V IDD1 + IDD2 fXTAL = 12.8 MHz; both synthesizers on; VDD1 = VDD2 = 3 V − 8.5 − mA fXTAL = 12.8 MHz; both synthesizers on; VDD1 = VDD2 = 5.5 V − − 12.5 mA fXTAL = 12.8 MHz; one synthesizer powered down; VDD1 = VDD2 = 3 V − 5.5 − mA fXTAL = 12.8 MHz; one synthesizer powered down; VDD1 = VDD2 = 5.5 V − − 7.5 mA IDDpda, IDDpdb total digital supply current from VDD1 and VDD2 total digital supply current from VDD1 and VDD2 with one synthesizer in power-down mode IDDpd digital supply current in power-down mode both synthesizers powered down; VHPD = 0 V − − 60 µA VCC charge pump supply voltage VCC ≥ VDD 2.6 − 6.0 V ICC charge pump supply current both synthesizers on and in lock; fref = 12.5 kHz − − 25 µA ICCpd charge pump supply current in power-down mode both synthesizers powered down − − 25 µA 8.5 12 mA 0.25 0.4 mA Voltage doubler enabled fXTAL = 12.8 MHz; both − synthesizers on and in lock; VDD1 = 3 V; fdoubler = 16 MHz IDD total digital supply current from VDD1 and VDD2 IDDpd total digital supply current both synthesizers powered in power-down mode from down; VDD1 = 3 V; VDD1 and VDD2 VHPD = 0 V − VCCvd charge pump supply voltage 2VDD1 − 1.2 2VDD1 − 0.6 6.0 1995 Jun 22 DC current drawn from VCC = 50 µA 8 V Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications SYMBOL PARAMETER UMA1015M CONDITIONS MIN. TYP. MAX. UNIT RF main divider input; RFA and RFB fRF RF input frequency VRF(rms) RF input signal voltage (RMS value; AC coupled) 50 − 1100 MHz Rs = 50 Ω; VDD1 = VDD2 = 2.6 to 3.5 V; fRF = 400 to 1100 MHz 50 − 250 mV Rs = 50 Ω; VDD1 = VDD2 = 3.5 to 5.5 V; fRF = 400 to 1100 MHz 100 − 250 mV Rs = 50 Ω; VDD1 = VDD2 = 2.6 to 5.5 V; fRF = 50 to 400 MHz 150 − 400 mV − 300 − Ω pF ZI input impedance (real part) fRF = 1 GHz; indicative, not tested CI input capacitance indicative, not tested Rpm principle main divider ratio − 1 − 512 − 131071 3 − 35 MHz 100 − 500 mV Reference divider input; fXTALIN fXTALIN reference input frequency from crystal VXTALIN(rms) sinusoidal input voltage (RMS value) ZI input impedance (real part) fXTALIN = 12.8 MHz; indicative, not tested − 10 − kΩ CI input capacitance indicative, not tested − 1 − pF Rrd reference divider ratio 8 − 4095 RSET = 12 to 60 kΩ − 1.2 − V RSET = 15 kΩ; CRA/CRB = logic 1; Icp = ISET × 24; Vcp = 0.4 V to VCC − 0.5 V 1.4 1.9 2.4 mA RSET = 15 kΩ; CRA/CRB = logic 0; Icp = ISET × 12; Vcp = 0.4 V to VCC − 0.5 V 0.7 0.96 1.2 mA Vcp = 0.5VCC −5 − +5 nA Charge pump current setting resistor input; ISET VSET voltage output on ISET Charge pump outputs; CPA and CPB ICP ILI 1995 Jun 22 charge pump sink or source current charge pump off leakage current 9 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications SYMBOL PARAMETER UMA1015M CONDITIONS MIN. TYP. MAX. UNIT Logic input signal levels; DATA, CLK, E and HPD VIH HIGH level input voltage at logic 1 0.7VDD1 − VDD1 + 0.3 V VIL LOW level input voltage at logic 0 −0.3 − 0.3VDD1 V Ibias input bias currents at logic 1 or logic 0 −5 − +5 µA CI input capacitance indicative, not tested − 1 − pF − 0.4 V Port outputs/Out-of-lock; P0/OOL, P1, P2, P3 and fXTALO - open drain outputs VOL LOW level output voltage − Isink = 0.4 mA SERIAL TIMING CHARACTERISTICS VDD1 = 3 V; Tamb = 25 °C unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT Serial programming clock; CLK tr, tf input rise and fall times − 10 40 ns tcy clock period 100 − − ns Enable programming; E tSTART delay to rising clock edge 40 − − ns tEND delay from last falling clock edge −20 − − ns tW minimum inactive pulse width 4000 − − ns tSU;E enable set-up time to next clock edge 20 − − ns Register serial input data; DATA tSU;DAT input data to clock set-up time 20 − − ns tHD;DAT input data to clock hold time 20 − − ns Fig.3 Serial bus timing diagram. 1995 Jun 22 10 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M TYPICAL PERFORMANCE CHARACTERISTICS (1) Tamb = +85 °C. (2) Tamb = +25 °C. (3) Tamb = −30 °C. Fig.4 IDD as a function of VDD with both synthesizers on and voltage doubler disabled. RSET = 15 kΩ; CRA = 1. (1) VCC = 2.7 V. (2) VCC = 6.0 V. Fig.5 Charge pump current as a function of CPA voltage. 1995 Jun 22 11 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications RSET = 15 kΩ; CRA = 1. (1) Tamb = +85 °C. (2) Tamb = +25 °C. (3) Tamb = −30 °C. Fig.6 Charge pump 3-state current as a function of CPA voltage. fXTALIN externally terminated by 50 Ω load; AC-coupled. (1) VDD = 5.5 V. (2) VDD = 2.7 V. Fig.7 Crystal input sensitivity as a function of input frequency. 1995 Jun 22 12 UMA1015M Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M fXTALIN externally terminated by 50 Ω load; AC-coupled. (1) Tamb = −30 °C. (2) Tamb = +25 °C. (3) Tamb = +85 °C. Fig.8 Crystal input sensitivity as a function of input frequency with VDD = 5.5 V. RF input externally terminated by 50 Ω load; AC-coupled. (1) VDD = 5.5 V. (2) VDD = 2.7 V. Fig.9 RF input sensitivity as a function of input frequency. 1995 Jun 22 13 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M RF input externally terminated by 50 Ω load; AC-coupled. (1) Tamb = −30 °C. (2) Tamb = +25 °C. (3) Tamb = +85 °C. Fig.10 RF input sensitivity as a function of input frequency with VDD = 5.5 V. (1) Tamb = −30 °C. (2) Tamb = +25 °C. (3) Tamb = +85 °C. Fig.11 Typical charge pump supply voltage as a function of VDD voltage with voltage doubler enabled. 1995 Jun 22 14 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M 1 handbook, full pagewidth 0.5 2 0.2 5 10 +j 0.2 0 0.5 1 5 10 ∞ 4 –j 3 1 0.2 5 2 0.5 (1) (2) (3) (4) 10 2 68.316 Ω, −92.457 Ω at 1.1 GHz. 85.914 Ω, −152.08 Ω at 800 MHz. 102.83 Ω, −354.66 Ω at 400 MHz. 853.75 Ω, −2.7735 kΩ at 50 MHz. MBE019 1 Fig.12 Input impedance as a function of input frequency; synthesizer A. 1 handbook, full pagewidth 0.5 2 0.2 5 10 +j 0 0.2 0.5 1 5 10 ∞ 4 –j 3 10 2 1 5 0.2 2 0.5 (1) (2) (3) (4) 69.293 Ω, −78.027 Ω at 1.1 GHz. 100.2 Ω, −148.37 Ω at 800 MHz. 128.22 Ω, −378.81 Ω at 400 MHz. 674.25 Ω, −3.06 kΩ at 50 MHz. 1 MBE020 Fig.13 Input impedance as a function of input frequency; synthesizer B. 1995 Jun 22 15 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications APPLICATION INFORMATION Fig.14 Typical application block diagram. 1995 Jun 22 16 UMA1015M BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBB BBB BB BB BB BB BB BB BB BB B B B B B B B B B BB B B B B B B B B BB BB BB BB BB BB BB BB BB B B B BBBBBBBBBB B BBB BB BB BB BB BB BB BB BB B BBB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B BBBBBBBBBB B BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB B BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBB B B B B B B B B B B B B B B B B B B B B B B B B B BBBBBBBBBBBBBBBBBBBBBBBBBBB BB B BBBBBBBBBBBBBBBBBBBBB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB B 17 Philips Semiconductors Product specification UMA1015M Fig.15 Typical CT1 application. Low-power dual frequency synthesizer for radio communications 1995 Jun 22 Transmit frequency = 959 MHz. Receive frequency = 914 MHz. 1st IF = 58.1125 MHz. 2nd IF = 455 MHz. VCO sensitivity = 2 MHz/V. Channel spacing = 12.5 kHz. Charge pump gain (CPA = CPB) = 1 mA/cycle. Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M PACKAGE OUTLINE SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm D SOT266-1 E A X c y HE v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0 1.4 1.2 0.25 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-04-05 95-02-25 SOT266-1 1995 Jun 22 EUROPEAN PROJECTION 18 o Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M SOLDERING SO or SSOP SSOP Introduction Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these cases reflow soldering is often used. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Reflow soldering Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. METHOD (SO OR SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering SO Repairing soldered joints Wave soldering techniques can be used for all SO packages if the following conditions are observed: Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated G, all other leads can be soldered in one operation within 2 to 5 seconds at 270 to 320 °C. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. 1995 Jun 22 19 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications UMA1015M DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Jun 22 20 Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications NOTES 1995 Jun 22 21 UMA1015M Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications NOTES 1995 Jun 22 22 UMA1015M Philips Semiconductors Product specification Low-power dual frequency synthesizer for radio communications NOTES 1995 Jun 22 23 UMA1015M Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. 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Printed in The Netherlands 413061/1500/03/pp24 Document order number: Date of release: 1995 Jun 22 9397 750 00177