DATA SHEET MOS INTEGRATED CIRCUIT µPD16738 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES ) DESCRIPTION The µPD16738 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2+0.1 V to VDD2–0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 45 MHz when driving at 2.7 V, this driver is applicable to XGA-standard TFT-LCD panels. FEATURES • CMOS level input • 384 Outputs • Input of 6 bits (gradation data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter • Logic power supply voltage (VDD1) : 3.3 V • Driver power supply voltage (VDD2) : 8.5 V • +0.3 –0.6 +0.5 –1.0 V V • High-speed data transfer : f CLK = 45 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V) • Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V • Apply for dot-line inversion, n-line inversion and column line inversion • Output Voltage polarity inversion function (POL) • Display data inversion function (POL2) • Single bank arrangement is possible (Loaded with slim or bending TCP) ORDERING INFORMATION Part Number µPD16738N -××× Package TCP (TAB package) Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13813EJ1V0DS00 (1st edition) Data Published January 2000 NS CP(K) Printed in Japan The mark • shows major revised points. NEC Corporation 1999 µ PD16738 BLOCK DIAGRAM STHR R,/L CLK STB STHL VDD1 VSS1 64-bit bidirectional shift register C1 C2 C63 D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 POL2 C64 Data register Latch POL VDD2 Level shifter VSS2 V0 - V9 D/A converter Voltage follower output VSEL S1 S2 S3 S384 Remark /xxx indicates active low signal. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 V5 S383 5 V0 V4 S2 Multiplexer 6-bit D/A converter 5 V9 POL 2 Data Sheet S13813EJ1V0DS00 S384 µ PD16738 PIN CONFIGURATION (µPD16738N-××× ××× : TCP (TAB package) ) VSS2 VDD2 R,/L POL STB D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 STHL V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 VDD1 CLK VSEL VSS1 STHR D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 POL2 VSS1 VDD2 VSS2 S384 S383 S382 S381 Copper Foil Surface S4 S3 S2 S1 Remark This figure does not specify the TCP package. Data Sheet S13813EJ1V0DS00 3 µ PD16738 1. PIN FUNCTIONS (1/2) Pin Symbol Pin Name Description S1 to S384 Driver output The D/A converted 64-gray scale analog voltage is output. D00 to D05 Display data input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). D10 to D15 DX0 : LSB, DX5: MSB D20 to D25 D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction control These refer to the start pulse input/output pins when driver ICs are connected in input cascade. The shift directions of the shift registers are as follows. R,/L = H : STHR input, S1 → S384, STHL output R,/L = L : STHL input, S384 → S1, STHR output STHR STHL CLK Right shift start pulse R,/L = H : Becomes the start pulse input pin. input/output R,/L = L : Becomes the start pulse output pin. Left shift start pulse R,/L = H : Becomes the start pulse output pin. input/output R,/L = L : Becomes the start pulse input pin. Shift clock input Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 64th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. STB Latch input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input POL = L : The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge. POL2 Data inversion POL2 = H : Display data is inverted. POL2 = L : Display data is not inverted VSEL Driver voltage selection Selects driver voltage. VSEL = H or open : VDD2 = 8.5 V (TYP.) • VSEL = L : VDD2 = 7.5 V ± 0.5 V 4 Data Sheet S13813EJ1V0DS00 µ PD16738 (2/2) Pin Symbol V0 to V9 Pin Name Description γ -corrected power Input the γ -corrected power supplies from outside by using operational amplifier. supplies Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 0.5 VDD2 – 0.3 V > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V VDD1 Logic power supply 3.3 V + 0.3 − 0.6 V + 0.5 − 1.0 V VDD2 Driver power supply 8.5 V VSS1 Logic ground Grounding VSS2 Driver ground Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is possible.) 2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply terminals (V0, V1, V2, ···, V9) and VSS2. Data Sheet S13813EJ1V0DS00 5 µ PD16738 2. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’ and V0” to V63” is almost equivalent. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated power supplies V1 to V3 and V6 to V8. Figure 2−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 0.5 VDD2 – 0.3 V > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V Figures 2−2 and 2−3 show the relationship between the input data and the output data and the resistance values of the resistor strings. This driver IC is designed for only single-sided mounting. Therefore, please do not use it for γ -corrected power supply level inversion in double-sided mounting. Figure 2− −1. Relationship Between Input Data and γ - corrected Power Supply VDD2 0.1 V Split interval V0 16 V1 16 V2 16 V3 15 V4 0.5 VDD2 0.3 V V5 15 V6 16 V7 16 V8 16 V9 0.1 V VSS2 00 10 20 30 3F Input Data (HEX) 6 Data Sheet S13813EJ1V0DS00 µ PD16738 Figure 2− −2. Relationship between Input Data and Output Voltage (1/2) VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 V0’ V0 r0 V1’ r1 V2’ r2 V3’ r3 r14 V15’ r15 V16’ V1 r16 V17’ r17 r46 V47’ r47 V48’ V3 r48 V49’ r49 r60 V61’ r61 V62’ r62 V4 V63’ Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17' V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' V63' Output Voltage V0 V1+(V0-V1) × 7170 V1+(V0-V1) × 6670 V1+(V0-V1) × 6170 V1+(V0-V1) × 5670 V1+(V0-V1) × 5170 V1+(V0-V1) × 4670 V1+(V0-V1) × 4170 V1+(V0-V1) × 3670 V1+(V0-V1) × 3170 V1+(V0-V1) × 2670 V1+(V0-V1) × 2170 V1+(V0-V1) × 1670 V1+(V0-V1) × 1220 V1+(V0-V1) × 770 V1+(V0-V1) × 370 V1 V2+(V1-V2) × 3810 V2+(V1-V2) × 3480 V2+(V1-V2) × 3150 V2+(V1-V2) × 2830 V2+(V1-V2) × 2530 V2+(V1-V2) × 2250 V2+(V1-V2) × 1980 V2+(V1-V2) × 1720 V2+(V1-V2) × 1470 V2+(V1-V2) × 1230 V2+(V1-V2) × 1000 V2+(V1-V2) × 780 V2+(V1-V2) × 570 V2+(V1-V2) × 370 V2+(V1-V2) × 180 V2 V3+(V2-V3) × 2590 V3+(V2-V3) × 2415 V3+(V2-V3) × 2245 V3+(V2-V3) × 2075 V3+(V2-V3) × 1910 V3+(V2-V3) × 1745 V3+(V2-V3) × 1580 V3+(V2-V3) × 1415 V3+(V2-V3) × 1245 V3+(V2-V3) × 1075 V3+(V2-V3) × 905 V3+(V2-V3) × 730 V3+(V2-V3) × 555 V3+(V2-V3) × 380 V3+(V2-V3) × 200 V3 V5+(V3-V4) × 4050 V5+(V3-V4) × 3830 V5+(V3-V4) × 3600 V5+(V3-V4) × 3360 V5+(V3-V4) × 3110 V5+(V3-V4) × 2850 V5+(V3-V4) × 2580 V5+(V3-V4) × 2290 V5+(V3-V4) × 1990 V5+(V3-V4) × 1680 V5+(V3-V4) × 1360 V5+(V3-V4) × 1020 V5+(V3-V4) × 680 V5+(V3-V4) × 340 V4 / / / / / / / / / / / / / / / 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 / / / / / / / / / / / / / / / 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 / / / / / / / / / / / / / / / 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 / / / / / / / / / / / / / / 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 (Ω) rn r0 500 r1 500 r2 500 r3 500 r4 500 r5 500 r6 500 r7 500 r8 500 r9 500 r10 500 r11 500 r12 450 r13 450 r14 400 r15 370 r16 330 r17 330 r18 330 r19 320 r20 300 r21 280 r22 270 r23 260 r24 250 r25 240 r26 230 r27 220 r28 210 r29 200 r30 190 r31 180 r32 175 r33 175 r34 170 r35 170 r36 165 r37 165 r38 165 r39 165 r40 170 r41 170 r42 170 r43 175 r44 175 r45 175 r46 180 r47 200 r48 210 r49 220 r50 230 r51 240 r52 250 r53 260 r54 270 r55 290 r56 300 r57 310 r58 320 r59 340 r60 340 r61 340 r62 340 r total 18835 Caution Between V4 and V5 terminal is not connected in the chip. Data Sheet S13813EJ1V0DS00 7 µ PD16738 Figure 2− −3. Relationship between Input Data and Output Voltage (2/2) 0.5 VDD2 – 0.3 V > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V V63’’ V5 r62 V62’’ r61 V61’’ r60 V60’’ r59 r49 V49’’ r48 V48’’ V6 r47 V47’’ r46 r17 V17’’ r16 V16’’ V8 r15 V15’’ r14 r2 V2’’ r1 V1’’ r0 V0’’ V9 Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0E H 0F H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1E H 1F H 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2E H 2F H 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3E H 3F H DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0" V1" V2" V3" V4" V5" V6" V7" V8" V9" V10" V11" V12" V13" V14" V15" V16" V17" V18" V19" V20" V21" V22" V23" V24" V25" V26" V27" V28" V29" V30" V31" V32" V33" V34" V35" V36" V37" V38" V39" V40" V41" V42" V43" V44" V45" V46" V47" V48" V49" V50" V51" V52" V53" V54" V55" V56" V57" V58" V59" V60" V61" V62" V63" Output voltage V9 500 V9+(V8-V9) × 1000 V9+(V8-V9) × 1500 V9+(V8-V9) × 2000 V9+(V8-V9) × 2500 V9+(V8-V9) × 3000 V9+(V8-V9) × 3500 V9+(V8-V9) × 4000 V9+(V8-V9) × 4500 V9+(V8-V9) × 5000 V9+(V8-V9) × 5500 V9+(V8-V9) × 6000 V9+(V8-V9) × 6450 V9+(V8-V9) × 6900 V9+(V8-V9) × 7300 V9+(V8-V9) × V8 330 V8+(V7-V8) × 660 V8+(V7-V8) × 990 V8+(V7-V8) × 1310 V8+(V7-V8) × 1610 V8+(V7-V8) × 1890 V8+(V7-V8) × 2160 V8+(V7-V8) × 2420 V8+(V7-V8) × 2670 V8+(V7-V8) × 2910 V8+(V7-V8) × 3140 V8+(V7-V8) × 3360 V8+(V7-V8) × 3570 V8+(V7-V8) × 3770 V8+(V7-V8) × 3960 V8+(V7-V8) × V7 175 V7+(V6-V7) × 350 V7+(V6-V7) × 520 V7+(V6-V7) × 690 V7+(V6-V7) × 855 V7+(V6-V7) × 1020 V7+(V6-V7) × 1185 V7+(V6-V7) × 1350 V7+(V6-V7) × 1520 V7+(V6-V7) × 1690 V7+(V6-V7) × 1860 V7+(V6-V7) × 2035 V7+(V6-V7) × 2210 V7+(V6-V7) × 2385 V7+(V6-V7) × 2565 V7+(V6-V7) × V6 210 V6+(V5-V6) × 430 V6+(V5-V6) × 660 V6+(V5-V6) × 900 V6+(V5-V6) × 1150 V6+(V5-V6) × 1410 V6+(V5-V6) × 1680 V6+(V5-V6) × 1970 V6+(V5-V6) × 2270 V6+(V5-V6) × 2580 V6+(V5-V6) × 2900 V6+(V5-V6) × 3240 V6+(V5-V6) × 3580 V6+(V5-V6) × 3920 V6+(V5-V6) × V5 Caution Between V4 and V5 terminal is not connected in the chip. 8 Data Sheet S13813EJ1V0DS00 / / / / / / / / / / / / / / 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 7670 / / / / / / / / / / / / / / 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 4140 / / / / / / / / / / / / / / / 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 2765 / / / / / / / / / / / / / / 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 4260 (Ω) rn r0 500 r1 500 r2 500 r3 500 r4 500 r5 500 r6 500 r7 500 r8 500 r9 500 r10 500 r11 500 r12 450 r13 450 r14 400 r15 370 r16 330 r17 330 r18 330 r19 320 r20 300 r21 280 r22 270 r23 260 r24 250 r25 240 r26 230 r27 220 r28 210 r29 200 r30 190 r31 180 r32 175 r33 175 r34 170 r35 170 r36 165 r37 165 r38 165 r39 165 r40 170 r41 170 r42 170 r43 175 r44 175 r45 175 r46 180 r47 200 r48 210 r49 220 r50 230 r51 240 r52 250 r53 260 r54 270 r55 290 r56 300 r57 310 r58 320 r59 340 r60 340 r61 340 r62 340 r total 18835 µ PD16738 3. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format: 6 bits × 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) R,/L = H (Right shift) Output S1 S2 S3 S4 xxx S383 S384 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 xxx D40 to D45 D50 to D55 R,/L = L (Left shift) Output S1 S2 S3 S4 xxx S383 S384 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 xxx D40 to D45 D50 to D55 POL S2n–1 Note Note S2n L V0 to V4 V5 to V9 H V5 to V9 V0 to V4 Note S2n-1 (Odd output), S2n (Even output) 4. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. STB POL S2n-1 Selected voltage of V0 to V4 Selected voltage of V0 to V4 Selected voltage of V5 to V9 S2n Selected voltage of V5 to V9 Hi-Z Selected voltage of V0 to V4 Hi-Z Data Sheet S13813EJ1V0DS00 Selected voltage of V5 to V9 Hi-Z 9 µ PD16738 5. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C, VSS1 = VSS2 = 0 V) Parameter Symbol Ratings Unit Logic Part Supply Voltage VDD1 –0.5 to +4.0 V Driver Part Supply Voltage VDD2 –0.5 to +10.0 V Logic Part Input Voltage VI1 –0.5 to VDD1 + 0.5 V Driver Part Input Voltage VI2 –0.5 to VDD2 + 0.5 V Logic Part Output Voltage VO1 –0.5 to VDD1 + 0.5 V Driver Part Output Voltage VO2 –0.5 to VDD2 + 0.5 V Operating Ambient Temperature TA –10 to +75 °C Storage Temperature Tstg –55 to +125 °C Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range (TA = –10 to +75 °C, VSS1 = VSS2 = 0 V) Parameter Logic Part Supply Voltage Symbol MIN. TYP. MAX. Unit 2.7 3.3 3.6 V VSEL = H or open 7.5 8.5 9.0 V VSEL = L 7.0 7.5 8.0 V VDD1 Driver Part Supply Voltage VDD2 • Conditions High-Level Input Voltage VIH 0.7 VDD1 VDD1 V Low-Level Input Voltage VIL 0 0.3 VDD1 V V0 to V4 0.5 VDD2 VDD2 − 0.1 V V5 to V9 VSS2 + 0.1 0.5 VDD2− 0.3 V Driver Part Output Voltage VO VSS2 + 0.1 VDD2 − 0.1 V Clock Frequency fCLK 45 MHz γ -Corrected Voltage 10 Data Sheet S13813EJ1V0DS00 µ PD16738 Electrical Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V +0.3 –0.6 V, VDD2 = 8.5 V +0.5 –1.0 V (VSEL = H or open), VSS1 = VSS2 = 0 V) Parameter Input Leak Current • • Symbol Condition MIN. TYP. IIL MAX. Unit ±1.0 µA High-Level Output Voltage VOH STHR (STHL), IOH = 0 mA VDD1 − 0.1 VDD1 V Low-Level Output Voltage VOL STHR (STHL), IOL = 0 mA 0 0.1 V V0 to V4 = V0 pin, V5 pin 80 160 320 µA V5 to V9 = 3.0 V V4 pin, V9 pin –320 –160 –80 µA –0.17 –0.1 mA γ -Corrected Supply Current Driver Output Current Output Voltage Deviation Iγ IVOH VX = 7.5 V, VOUT = 7.0 V VDD2 = 8.0 V Note IVOL VX = 0.5 V, VOUT = 1.0 V VDD2 = 8.0 V Note ∆VO Input data , , 0.1 V0 = 0.1 V to 1.2 V, 0.23 mA ±20 ±30 mV ±10 ±20 mV ±20 ±30 mV ±10 ±20 mV ±3 ±10 mV V0 = VDD2 – 1.2 V to VDD2 – 0.1 V V0 = 1.2 V to 0.5 VDD2 – 0.3 V, V0 = 0.5 VDD2 to VDD2 – 1.2 V Output Swing Voltage Difference Deviation ∆Vp–p1 V0 = 0.1 V to 0.8 V, V0 = VDD2 – 0.8 V to VDD2 – 0.1 V ∆Vp–p2 V0 = 0.8 V to 1.2 V, V0 = VDD2 – 1.2 V to VDD2 – 0.8 V ∆Vp–p3 V0 = 1.2 V to 0.5 VDD2 – 0.3 V , V0 = 0.5 VDD2 to VDD2 –1.2 V • • Output Voltage Range VO All Input data 0.1 VDD2 – 0.1 V Logic Part Dynamic Current Consumption IDD1 VDD1, with no load 0.8 4.5 mA Driver Part Dynamic Current Consumption IDD2 VDD2 = 9.0 V, with no load 5.5 12 mA Note VX refers to the output voltage of analog output pins S1 to S384. VOUT refers to the voltage applied to analog output pins S1 to S384. Cautions 1. The STB cycle is defined to be 20 µ s at fCLK = 45 MHz. 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of XGA single-sided mounting (8 units). Data Sheet S13813EJ1V0DS00 11 µ PD16738 Switching Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V +0.3 V, –0.6 VDD2 = 8.5 V +0.5 –1.0 V (VSEL = H or open), VSS1 = VSS2 = 0 V) Parameter Symbol Condition Unit CL = 25 pF 8 20 ns Driver Output Delay Time tPLH2 VDD2 = 8.5 V ± 0.5 V 4 8 µs tPLH3 RL = 10 kΩ ,CL = 80 pF 5.5 11 µs tPHL2 4 8 µs tPHL3 5.5 11 µs Parameter Clock Pulse Width CI1 STHR (STHL) excluded, TA = 25°C 4.8 10 pF CI2 STHR (STHL),TA = 25°C 8.6 15 pF MAX. Unit Symbol +0.3 –0.6 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns) Condition MIN. TYP. PWCLK 22 ns Clock Pulse High Period PWCLK(H) 4 ns Clock Pulse Low Period PWCLK(L) 4 ns Data Setup Time tSETUP1 0 ns Data Hold Time tHOLD1 4 ns Start Pulse Setup Time tSETUP2 2 ns Start Pulse Hold Time tHOLD2 2 ns POL2 Setup Time tSETUP3 0 ns POL2 Hold Time tHOLD3 4 ns tSPL 1 CLK PWSTB 3 CLK tINV 1 CLK Start Pulse Low Period STB Pulse Width Data Invalid Period • MAX. tPLH1 Timing Requirement (TA = –10 to +75 °C, VDD1 = 3.3 V • • TYP. Start Pulse Delay Time Input Capacitance • • MIN. CLK-STB Time tCLK-STB CLK ↑ → STB ↑ 0 ns STB-CLK Time tSTB-CLK STB ↑ → CLK ↑ 10 ns Time Between STB and Start Pulse tSTB-STH STB ↑ → STHR(STHL) ↑ 3 CLK POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑ 6 ns STB-POL Time tSTB-POL STB ↓ → POL ↓ or ↑ 3 CLK Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. 12 Data Sheet S13813EJ1V0DS00 INVALID POL2 Data Sheet S13813EJ1V0DS00 VOUT POL STB STHL (1st Dr.) INVALID tSETUP2 Dn0 to Dn5 STHR (1st Dr.) CLK tHOLD1 3 tSETUP3 tHOLD3 D7 to D12 tSETUP1 2 D1 to D6 tHOLD2 1 PWCLK(H) tPLH1 D373 to D378 64 D379 to D384 65 D385 to D390 66 D3067 to D3072 513 tINV Hi-Z PWSTB tCLK-STB tSTB-CLK tPOL-STB 514 tPLH3 tPHL3 tPHL2 tPLH2 tSTB-POL INVALID INVALID tSTB-STH tSPL D1-D6 2 10% D7-D12 90% tr tf Target Voltage +0.1 VDD2 6-bit accuracy 1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 • PWCLK(L) PWCLK µ PD16738 6. SWITCHING CHARACTERISTICS WAVEFORM (R,/L = H) Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. 13 µ PD16738 7. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met for soldering conditions of the µPD16738. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. Type of Surface Mount Device ××× : TCP (TAB package) µ PD16738N-××× Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350°C, heating for 2 to 3 seconds: pressure 100g (per solder) ACF (Adhesive Conductive Film) 2 Temporary bonding 70 to 100°C: pressure 3 to 8 kg/cm : time 3 to 5 seconds. 2 Real bonding 165 to 180°C: pressure 25 to 45 kg/cm : time 30 to 40 seconds. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. 14 Data Sheet S13813EJ1V0DS00 µ PD16738 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S13813EJ1V0DS00 15 µ PD16738 Reference Documents NEC Semiconductor Device Reliability / Quality Control System (C10983E) Quality Grades to NEC’s Semiconductor Devices (C11531E) • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8