NEC UPD16805GS

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16805
MONOLITHIC H BRIDGE DRIVER CIRCUIT
DESCRIPTION
The µPD16805 is a monolithic H bridge driver IC which uses low-ON resistance power MOS FETs in its driver stage.
This driver has a forward, reverse, and brake functions and is ideal for the driver circuit of motors for camera that
advance or rewind the film, and for auto focusing or zooming.
This IC supports a drive current of up to 1.0 A (DC).
FEATURES
PIN CONFIGURATION (Top View)
• High drive current
IDR = 4.2 A MAX. at PW ≤ 200 ms (single pulse)
IDR = 1.0 A (DC)
• Low-ON resistance (sum of ON resistances of top
and bottom MOS FET)
RON = 0.4 Ω TYP. at IDR = 1.0 A
• Standby function that turns OFF charge pump circuit
• Compact surface mount package
16-pin plastic SOP (300 mil)
ORDERING INFORMATION
Part Number
µPD16805GS
C2L
1
16 C2H
C1H
2
15 VG
C1L
3
14 STBY
VM
4
13 OUT2
VDD
5
12 PGND
IN1
6
11 OUT1
IN2
7
10 VM
INC
8
9
DGND
Package
16-pin plastic SOP (300 mil)
BLOCK DIAGRAM
C1
C2
VDD
STBY
C3
VG
C1 = C2 = C3: External capacitors (10 nF)
Charge pump
circuit
Contorol
circuit
INC
VM
IN1
OUT1
Contorol
circuit
IN2
Level shift
circuit
D MOS FET
H bridge circuit
Load motor
OUT2
50 kΩ
DGND
PGND
The information in this document is subject to change without notice.
Document No. G11032EJ3V0DS00 (3rd edition)
Date Published July 1997 N
Printed in Japan
©
1997
µPD16805
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage
Symbol
Conditions
VDD
VM
Rating
Unit
–0.5 to +6.5/+8.0
Note
–0.5 to +6.5/+8.0
Note
V
VG pin applied voltage
VG
15
V
Input voltage
VIN
–0.5 to VDD + 0.5
V
H bridge drive current
IDR1
DC
1.0
A
IDR2
PW ≤ 200 ms (single pulse)
4.2
A
Power consumption
PT
TA = 25 °C
1.0
W
Operating temperature range
TA
–30 to +60
°C
TJ (MAX)
150
°C
Tstg
–55 to +150
°C
Operating junction temperature
Storage temperature range
Note VDD when the charge pump is used/VDD and VM when VG is supplied from an external source
RECOMMENDED OPERATING CONDITIONS
Ratings
Parameter
Symbol
Conditions
Unit
MIN.
Supply voltage
VDD
During normal operation
3.0
All input pins are low
2.5
VM
Charge pump capacitance
VG pin applied voltage
Note 1
Operating temperature
0.5
C1 to C3
6.0/7.5Note 2
V
7.5
V
Ambient temperature
nF
11
14
V
–30
60
°C
Notes 1. When a voltage is applied from an external source to the VG pin
2. When the charge pump is used/when VG is supplied from an external source
2
MAX.
10
VG
TA
TYP.
µPD16805
ELECTRICAL SPECIFICATIONS (Unless otherwise specified, TA = 25 °C, VDD = recommended
operating condition, VM = 0.5 to 7.5 V)
Ratings
Parameter
Symbol
Conditions
Unit
MIN.
VDD pin current
TYP.
MAX.
IDD1
VDD = 5 V, TA = recommended
conditions
Control pins at high level
0.6
2.0
mA
IDD2
VDD = 5 V, TA = recommended
conditions
Control pins at low level
0.3
10
µA
IM1
Control pins at low level,
TA = recommended conditions
0.1
10
µA
IM2
Control pins at low level
1.0
µA
RON
IDR = 1.0 A, VDD = VM = 5 V
0.6
Ω
Control pin high-level input voltage
VIH
TA = recommended condition
Control pin low-level input voltage
VIL
TA = recommended condition
Charge pump circuit turn-ON time
tONG
VDD = VM = 5 V,
VM pin current
H bridge ON
resistanceNote
H bridge output circuit turn-ON time
tONH
H bridge output circuit turn-OFF time
tOFFH
Control pin input pull-down resistor
RIND
0.4
VDD × 0.6
V
0.5
TA = recommended conditions
C1 = C2 = C3 = 10 nF
IDR = 1.0 A
35
TA = recommended condition
25
50
VDD × 0.2
V
1.0
ms
10
µs
5.0
µs
65
kΩ
75
kΩ
Note Sum of ON resistances of top and bottom MOS FETs
3
µPD16805
FUNCTION TABLE
Input Signal
Function
IN1
IN2
INC
STB
H
L
H
H
Forward mode
L
H
H
H
Reverse mode
H
H
H
H
Brake mode
L
L
H
H
Stop mode
×
×
L
H
Stop mode
×
×
×
L
Standby mode
Forward mode
Reverse mode
VM
ON
OFF
OUT1
OUT2
OFF
OFF
OUT1
ON
4
VM
ON
OFF
ON
OUT1
OUT2
ON
OFF
Brake mode
Stop mode
VM
VM
OFF
OUT2
ON
OFF
OUT1
OFF
OFF
OUT2
OFF
APPLICATION CIRCUIT 1
VM = 0.5 V to 7.5 V
VDD = 3.0 V to 6.0 V
DC-DC
convertor
C1 = C2 = C3 = 10 = nF
C2
C1
C3
Battery
VDD
5
STBY 14
CPU
INC
8
IN1
6
IN2
7
VM
2
3
16
1
15
10
4
OSC
circuit
VM
Charge pump circuit
C4 Note
1 to 10 µ F
11 OUT1
Control circuit
D MOS FET
H bridge
circuit
Level shift
circuit
13
OUT2
M
Film
take-up motor
Pull-down resistor
50 kΩ TYP.
9
DGND
H
IN1
Note It is recommended to connect a capacitor of 1 to 10
µF between VM and GND to protect the gate of the
L
H
DMOS FET from surge voltage.
L
Forward
mode
Brake
mode
Reverse
mode
Stop mode
5
µPD16805
IN2
12
PGND
APPLICATION CIRCUIT 2
6
VM = 0.5 V to 7.5 V
VG = 11 V to 14 V
DC-DC
convertor
VDD = 3.0 V to 7.5 V
Battery
VDD
5
STBY 14
CPU
INC
8
IN1
6
IN2
7
VM
2
OSC
circuit
3
16
1
15
10
VM
Charge pump circuit
C4 Note
1 to 10 µ F
11 OUT1
Control circuit
D MOS FET
H bridge
circuit
Level shift
circuit
13
OUT2
M
Film
take-up motor
Pull-down resistor
50 kΩ TYP.
9
DGND
Note It is recommended to connect a capacitor of 1 to 10
H
IN1
12
PGND
µF between VM and GND to protect the gate of the
L
DMOS FET from surge voltage.
H
IN2
L
Brake
mode
Reverse
mode
Stop mode
µPD16805
Forward
mode
µPD16805
TYPICAL CHARACTERISTICS (TA = 25 °C)
PT vs. TA Characteristics
RON vs. TA Characteristics
1.2
H bridge ON resistance RON (Ω)
Total power dissipation PT (W)
1.4
1.0
0.8
0.6
0.4
0.2
0
10
20
30
40
50
60
70
IDR = 1.0 A
VDD = VM = 5 V
1.2
1.0
0.8
0.6
0.4
0.2
0
– 50 – 25
80
Ambient temperature TA (˚C)
0
25
50
75
100
Ambient temperature TA (˚C)
VG vs. RON Characteristics
VG vs. IG Characteristics
VDD = 5 V
VDD = 5 V
H bridge ON resistance RON (Ω)
Gate current IG ( µ A)
60
50
40
30
20
10
0
5
10
15
Gate applied voltage VG (V)
20
1.2
1.0
0.8
0.6
0.4
0.2
0
5
10
15
20
Gate applied voltage VG (V)
7
µPD16805
PACKAGE DIMENSION
16 PIN PLASTIC SOP (300 mil)
16
9
P
detail of lead end
1
8
A
H
J
E
K
F
G
I
C
N
D
M
B
L
M
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
INCHES
A
10.46 MAX.
0.412 MAX.
B
0.78 MAX.
0.031 MAX.
C
1.27 (T.P.)
0.050 (T.P.)
D
0.40 +0.10
–0.05
0.016 +0.004
–0.003
E
0.1±0.1
0.004±0.004
F
1.8 MAX.
0.071 MAX.
G
1.55
0.061
H
7.7±0.3
0.303±0.012
I
5.6
0.220
J
1.1
0.043
K
0.20 +0.10
–0.05
0.008 +0.004
–0.002
L
0.6±0.2
M
0.12
0.005
N
0.10
0.004
P
3 ° +7°
–3°
3° +7°
–3°
0.024 +0.008
–0.009
P16GM-50-300B-4
8
µPD16805
RECOMMENDED SOLDERING CONDITIONS
It is recommended to solder this product under the conditions described below.
For soldering methods and conditions other than those listed below, consult NEC.
Surface mount type
For the details of the recommended soldering conditions of this type, refer to Semiconductor Device Mounting
Technology Manual (C10535E).
µPD16805GS
Soldering Method
Soldering Conditions
Symbol of
Recommended
Soldering
Infrared reflow
Peak package temperature: 235 °C, Time: 30 seconds MAX. (210 °C MIN.),
Number of times: 2 MAX.
IR35-00-2
VPS
Peak package temperature: 215 °C, Time: 40 seconds MAX. (200 °C MIN.),
Number of times: 2 MAX.
VP15-00-2
Note The number of storage days at 25 °C, 65% RH after the dry pack has been opened
9
µPD16805
[MEMO]
10
µPD16805
[MEMO]
11
µPD16805
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this document.
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Anti-radioactive design is not implemented in this product.
M4 96.5
2