DATA SHEET MOS INTEGRATED CIRCUIT µPD442000L-X 2M-BIT CMOS STATIC RAM 256K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION Description The µPD442000L-X is a high speed, low power, 2,097,152 bits (262,144 words by 8 bits) CMOS static RAM. The µPD442000L-X has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. B, C and D versions are low voltage versions. ★ The µPD442000L-X is packed in 32-pin plastic TSOP (I) (8×13.4 mm) and (8×20 mm). Features • 262,144 words by 8 bits organization ★ • Fast access time : 70, 85, 100, 120, 150, 180 ns (MAX.) • Low voltage operation (B version : VCC = 2.7 to 3.6 V, C version : VCC = 2.2 to 3.6 V, D version : VCC = 1.8 to 3.6 V) • Low VCC data retention : 1.5 V (MIN.) • Operating ambient temperature : TA = –25 to +85 °C • Output Enable input for easy application • Two Chip Enable inputs : /CE1, CE2 Part number Access time ns (MAX.) ★ Operating supply Operating ambient Supply current voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) −25 to +85 35 2 2 µPD442000L-BxxX 70 , 85, 100 2.7 to 3.6 µPD442000L-CxxX 100, 120, 150 2.2 to 3.6 30 µPD442000L-DxxX 150, 180 1.8 to 3.6 25 Note Note Under development The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M12509EJ7V0DSJ1 (7th edition) Date Published December 2000 NS CP (K) Printed in Japan The mark • shows major revised points. © 1997 µPD442000L-X ★ Ordering Information Part number µPD442000LGU-B70X-9JH Package Note µPD442000LGU-B85X-9JH Operating Operating ns (MAX.) supply voltage temperature V °C 2.7 to 3.6 −25 to +85 32-pin Plastic TSOP (I) 70 (8×13.4) (Normal bent) 85 µPD442000LGU-B10X-9JH Note µPD442000LGU-B85X-9KH 32-pin Plastic TSOP (I) 70 (8×13.4) (Reverse bent) 85 µPD442000LGU-B10X-9KH B version 100 Note µPD442000LGZ-B85X-KJH 32-pin Plastic TSOP (I) 70 (8×20) (Normal bent) 85 µPD442000LGZ-B10X-KJH µPD442000LGZ-B70X-KKH µPD442000LGZ-B85X-KKH 100 Note 32-pin Plastic TSOP (I) (8×20) (Reverse bent) µPD442000LGZ-B10X-KKH 70 85 100 µPD442000LGU-C10X-9JH 32-pin Plastic TSOP (I) 100 µPD442000LGU-C12X-9JH (8×13.4) (Normal bent) 120 µPD442000LGU-C10X-9KH 32-pin Plastic TSOP (I) 100 µPD442000LGU-C12X-9KH (8×13.4) (Reverse bent) 120 µPD442000LGZ-C10X-KJH 32-pin Plastic TSOP (I) 100 µPD442000LGZ-C12X-KJH (8×20) (Normal bent) 120 µPD442000LGU-C15X-9JH 2.2 to 3.6 C version 1.8 to 3.6 D version 150 µPD442000LGU-C15X-9KH 150 µPD442000LGZ-C15X-KJH 150 µPD442000LGZ-C10X-KKH 32-pin Plastic TSOP (I) 100 µPD442000LGZ-C12X-KKH (8×20) (Reverse bent) 120 µPD442000LGZ-C15X-KKH 150 µPD442000LGU-D15X-9JH 32-pin Plastic TSOP (I) 150 µPD442000LGU-D18X-9JH (8×13.4) (Normal bent) 180 µPD442000LGU-D15X-9KH 32-pin Plastic TSOP (I) 150 µPD442000LGU-D18X-9KH (8×13.4) (Reverse bent) 180 µPD442000LGZ-D15X-KJH 32-pin Plastic TSOP (I) 150 µPD442000LGZ-D18X-KJH (8×20) (Normal bent) 180 µPD442000LGZ-D15X-KKH 32-pin Plastic TSOP (I) 150 µPD442000LGZ-D18X-KKH (8×20) (Reverse bent) 180 Note Under development 2 Remark 100 µPD442000LGU-B70X-9KH µPD442000LGZ-B70X-KJH Access time Data Sheet M12509EJ7V0DS µPD442000L-X Pin Configurations (Marking Side) /xxx indicates active low signal. 32-pin Plastic TSOP (I) (8× ×13.4) (Normal bent) [ µPD442000LGU-BxxX-9JH ] [ µPD442000LGU-CxxX-9JH ] [ µPD442000LGU-DxxX-9JH ] 32-pin Plastic TSOP (I) (8× ×20) (Normal bent) [ µPD442000LGZ-BxxX-KJH ] [ µPD442000LGZ-CxxX-KJH ] [ µPD442000LGZ-DxxX-KJH ] ★ A11 A9 A8 A13 /WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A0 - A17 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M12509EJ7V0DS 3 µPD442000L-X 32-pin Plastic TSOP (I) (8× ×13.4) (Reverse bent) [ µPD442000LGU-BxxX-9KH ] [ µPD442000LGU-CxxX-9KH ] [ µPD442000LGU-DxxX-9KH ] 32-pin Plastic TSOP (I) (8× ×20) (Reverse bent) [ µPD442000LGZ-BxxX-KKH ] [ µPD442000LGZ-CxxX-KKH ] [ µPD442000LGZ-DxxX-KKH ] /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 ★ 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A0 - A17 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground Remark Refer to Package Drawings for the 1-pin index mark. 4 Data Sheet M12509EJ7V0DS A11 A9 A8 A13 /WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 µPD442000L-X Block Diagram A0 Address buffer A17 Row decoder I/O1 Input data controller I/O8 Memory cell array 2,097,152 bits Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CE1 CE2 /OE /WE VCC GND Truth Table /CE1 CE2 /OE /WE Mode I/O Supply current H × × × Not selected High impedance ISB × L × × Not selected High impedance L H H H Output disable High impedance L H L H Read DOUT L H × L Write DIN ICCA Remark × : VIH or VIL Data Sheet M12509EJ7V0DS 5 µPD442000L-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Condition Rating VCC –0.5 –0.5 Note Note Unit to +4.6 V to VCC+0.5 V Input / Output voltage VT Operating ambient temperature TA –25 to +85 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Supply voltage VCC High level input voltage VIH Low level input voltage VIL Operating ambient temperature TA µPD442000L-BxxX Condition µPD442000L-CxxX µPD442000L-DxxX Unit MIN. MAX. MIN. MAX. MIN. MAX. 2.7 3.6 2.2 3.6 1.8 3.6 V 2.7 V ≤ VCC ≤ 3.6 V 2.4 VCC+0.5 2.4 VCC+0.5 2.4 VCC+0.5 V 2.2 V ≤ VCC < 2.7 V – – 2.0 VCC+0.5 2.0 VCC+0.5 1.8 V ≤ VCC < 2.2 V – – – – 1.6 VCC+0.5 –0.3 Note –25 +0.5 +85 –0.3 Note –25 +0.3 –0.3 +85 Note –25 +0.2 V +85 °C Note –1.5 V (MIN.) (Pulse width : 30 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. 6 Data Sheet M12509EJ7V0DS µPD442000L-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition µPD442000L-BxxX µPD442000L-CxxX µPD442000L-DxxX Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Input leakage ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 µA ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 µA mA current I/O leakage current CE2 = VIL or /WE = VIL or /OE = VIH Operating ICCA1 supply current /CE1 = VIL, CE2 = VIH, 30 35 25 30 20 25 Minimum cycle time, VCC ≤ 2.7 V – – 20 25 15 20 VCC ≤ 2.2 V – – – – 10 15 II/O = 0 mA ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA ICCA3 10 10 10 VCC ≤ 2.7 V – 8 8 VCC ≤ 2.2 V – – 5 8 8 8 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VCC ≤ 2.7 V – 6 6 VIH ≥ VCC – 0.2 V VCC ≤ 2.2 V – – 5 0.3 0.3 0.3 mA µA Standby ISB /CE1 = VIH or CE2 = VIL supply current ISB1 /CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V ISB2 High level VOH VOL 2 0.1 2 0.1 2 VCC ≤ 2.7 V – – 0.08 2 0.08 2 VCC ≤ 2.2 V – – – – 0.05 1.5 0.1 2 0.1 2 0.1 2 VCC ≤ 2.7 V – – 0.08 2 0.08 2 VCC ≤ 2.2 V – – – – 0.05 1.5 CE2 ≤ 0.2 V IOH = –0.5 mA output voltage Low level 0.1 2.4 2.4 2.4 VCC ≤ 2.7 V – 1.8 1.8 VCC ≤ 2.2 V – – 1.5 IOL = 1.0 mA 0.4 0.4 V 0.4 V output voltage Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types and access time. Data Sheet M12509EJ7V0DS 7 µPD442000L-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD442000L-B70X, µPD442000L-B85X, µPD442000L-B10X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.4 V 1.5 V Test Points 1.5 V Test Points 1.5 V 0.5 V Output Waveform 1.5 V Output Load 1TTL + 50 pF [ µPD442000L-C10X, µPD442000L-C12X, µPD442000L-C15X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.0 V 1.1 V Test Points 1.1 V 1.1 V Test Points 1.1 V 0.9 V Test Points 0.9 V 0.9 V Test Points 0.9 V 0.3 V Output Waveform Output Load 1TTL + 50 pF ★ [ µPD442000L-D15X, µPD442000L-D18X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 1.6 V 0.2 V Output Waveform Output Load 1TTL + 50 pF 8 Data Sheet M12509EJ7V0DS µPD442000L-X Read Cycle (1/3) (B version) Parameter Symbol µPD442000L-B70X µPD442000L-B85X µPD442000L-B10X MIN. MAX. 70 MIN. MAX. 85 MIN. Unit Condition MAX. Read cycle time tRC 100 ns Address access time tAA 70 85 100 ns /CE1 access time tCO1 70 85 100 ns CE2 access time tCO2 70 85 100 ns /OE to output valid tOE 35 40 50 ns Output hold from address change tOH 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /CE1 to output in high impedance tHZ1 25 30 35 ns CE2 to output in high impedance tHZ2 25 30 35 ns /OE to output in high impedance tOHZ 25 30 35 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Read Cycle (2/3) (C version) Parameter Symbol µPD442000L-C10X µPD442000L-C12X µPD442000L-C15X MIN. MAX. 100 MIN. MAX. 120 MIN. Unit Condition MAX. Read cycle time tRC 150 ns Address access time tAA 100 120 150 ns /CE1 access time tCO1 100 120 150 ns CE2 access time tCO2 100 120 150 ns /OE to output valid tOE 50 60 70 ns Output hold from address change tOH 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /CE1 to output in high impedance tHZ1 35 40 45 ns CE2 to output in high impedance tHZ2 35 40 45 ns /OE to output in high impedance tOHZ 35 40 45 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Data Sheet M12509EJ7V0DS 9 µPD442000L-X ★ Read Cycle (3/3) (D version) Parameter Symbol µPD442000L-D15X MIN. MAX. 150 µPD442000L-D18X MIN. Unit Read cycle time tRC 180 Address access time tAA 150 180 ns /CE1 access time tCO1 150 180 ns CE2 access time tCO2 150 180 ns /OE to output valid tOE 70 80 ns Output hold from address change tOH 10 10 ns /CE1 to output in low impedance tLZ1 10 10 ns CE2 to output in low impedance tLZ2 10 10 ns /OE to output in low impedance tOLZ 5 5 ns /CE1 to output in high impedance tHZ1 45 50 ns CE2 to output in high impedance tHZ2 45 50 ns /OE to output in high impedance tOHZ 45 50 ns ns Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Read Cycle Timing Chart tRC Address (Input) tAA tOH /CE1 (Input) tHZ1 tCO1 tLZ1 CE2 (Input) tCO2 tHZ2 tLZ2 /OE (Input) tOE tOHZ tOLZ I/O (Output) Remark 10 High impedance In read cycle, /WE should be fixed to high level. Data Sheet M12509EJ7V0DS Condition MAX. Data out Note 1 Note 2 µPD442000L-X Write Cycle (1/3) (B version) Parameter Symbol µPD442000L-B70X µPD442000L-B85X µPD442000L-B10X MIN. MAX. MIN. MAX. MIN. Unit Write cycle time tWC 70 85 100 ns /CE1 to end of write tCW1 55 70 80 ns CE2 to end of write tCW2 55 70 80 ns Address valid to end of write tAW 55 70 80 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 50 60 60 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 30 35 40 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 25 5 30 5 Condition MAX. 35 5 ns Note ns Note The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Write Cycle (2/3) (C version) Parameter Symbol µPD442000L-C10X µPD442000L-C12X µPD442000L-C15X MIN. MAX. MIN. MAX. MIN. Unit MAX. Write cycle time tWC 100 120 150 ns /CE1 to end of write tCW1 80 100 120 ns CE2 to end of write tCW2 80 100 120 ns Address valid to end of write tAW 80 100 120 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 60 80 100 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 40 50 60 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 35 5 40 5 50 5 Condition ns Note ns Note The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Data Sheet M12509EJ7V0DS 11 µPD442000L-X ★ Write Cycle (3/3) (D version) Parameter Symbol µPD442000L-D15X MIN. MAX. µPD442000L-D18X MIN. Unit Write cycle time tWC 150 180 ns /CE1 to end of write tCW1 120 150 ns CE2 to end of write tCW2 120 150 ns Address valid to end of write tAW 120 150 ns Address setup time tAS 0 0 ns Write pulse width tWP 100 120 ns Write recovery time tWR 0 0 ns Data valid to end of write tDW 60 75 ns Data hold time tDH 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 50 5 60 5 Note The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. 12 Data Sheet M12509EJ7V0DS Condition MAX. ns ns Note µPD442000L-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance Data in tDH High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M12509EJ7V0DS 13 µPD442000L-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance Data in I/O (Input) tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. 14 Data Sheet M12509EJ7V0DS µPD442000L-X Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2. Data Sheet M12509EJ7V0DS 15 µPD442000L-X Low VCC Data Retention Characteristics (TA = –25 to +85 °C) Parameter Data retention supply voltage Data retention supply current Symbol Test Condition MIN. TYP. MAX. Unit V VCCDR1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 1.5 3.6 VCCDR2 CE2 ≤ 0.2 V 1.5 3.6 ICCDR1 VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, 0.1 2 0.1 2 µA CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V ICCDR2 Chip deselection to data retention mode Operation recovery time VCC = 3.0 V, CE2 ≤ 0.2 V tCDR 0 tRC tR Note tRC : Read cycle time. 16 Data Sheet M12509EJ7V0DS Note ns ns µPD442000L-X Data Retention Timing Chart (1) /CE1 Controlled tCDR ★ Data retention mode tR VCC VCC (MIN.) Note /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. (2) CE2 Controlled tCDR ★ Data retention mode tR VCC VCC (MIN.) Note VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in high impedance state. Data Sheet M12509EJ7V0DS 17 µPD442000L-X Package Drawings ★ 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 S T R L 16 17 U Q P I J A G S H K B C N S NOTES D M M ITEM 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) A MILLIMETERS 8.0±0.1 B 0.45 MAX. C D 0.5 (T.P.) 0.22±0.05 G 1.0±0.05 H 12.4±0.2 I 11.8±0.1 J 0.8±0.2 K 0.145 +0.025 −0.015 L M 0.5 0.08 N 0.08 P 13.4±0.2 Q 0.1±0.05 R +5° 3° −3° S 1.2 MAX. T 0.25 U 0.6±0.15 P32GU-50-9JH-2 18 Data Sheet M12509EJ7V0DS µPD442000L-X ★ 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 U Q L R T 16 17 N K S D S M M C H B S G I J A P NOTES ITEM 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) A MILLIMETERS 8.0±0.1 B 0.45 MAX. C 0.5 (T.P.) D 0.22±0.05 G 1.0±0.05 H 12.4±0.2 I 11.8±0.1 J 0.8±0.2 K 0.145 +0.025 −0.015 L M 0.5 0.08 N 0.08 P 13.4±0.2 Q 0.1±0.05 R 3° +5° −3° S 1.2 MAX. T 0.25 U 0.6±0.15 P32GU-50-9KH-2 Data Sheet M12509EJ7V0DS 19 µPD442000L-X ★ 32-PIN PLASTIC TSOP(I) (8x20) detail of lead end 1 32 F G R Q 16 L 17 S E P I J A S B C D K N M M S NOTES ITEM MILLIMETERS 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. A 8.0±0.1 B 0.45 MAX. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 0.97±0.08 I 18.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 20.0±0.2 Q +5° 3°−3° R S 0.25 0.60±0.15 S32GZ-50-KJH1-2 20 Data Sheet M12509EJ7V0DS µPD442000L-X ★ 32-PIN PLASTIC TSOP(I) (8x20) detail of lead end E 1 32 S L Q R 16 G 17 F M M D K N S C B S I J A P NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM MILLIMETERS A 8.0±0.1 B 0.45 MAX. C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 0.97±0.08 I 18.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 20.0±0.2 Q +5° 3° −3° R S 0.25 0.60±0.15 S32GZ-50-KKH1-2 Data Sheet M12509EJ7V0DS 21 µPD442000L-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD442000L-X. ★ Types of Surface Mount Device µPD442000LGU-BxxX-9JH : 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) µPD442000LGU-CxxX-9JH : 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) µPD442000LGU-DxxX-9JH : 32-pin Plastic TSOP (I) (8×13.4) (Normal bent) µPD442000LGU-BxxX-9KH : 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) µPD442000LGU-CxxX-9KH : 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) µPD442000LGU-DxxX-9KH : 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent) µPD442000LGZ-BxxX-KJH : 32-pin Plastic TSOP (I) (8×20) (Normal bent) µPD442000LGZ-CxxX-KJH : 32-pin Plastic TSOP (I) (8×20) (Normal bent) µPD442000LGZ-DxxX-KJH : 32-pin Plastic TSOP (I) (8×20) (Normal bent) µPD442000LGZ-BxxX-KKH : 32-pin Plastic TSOP (I) (8×20) (Reverse bent) µPD442000LGZ-CxxX-KKH : 32-pin Plastic TSOP (I) (8×20) (Reverse bent) µPD442000LGZ-DxxX-KKH : 32-pin Plastic TSOP (I) (8×20) (Reverse bent) 22 Data Sheet M12509EJ7V0DS µPD442000L-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M12509EJ7V0DS 23 µPD442000L-X • The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4