DATA SHEET MOS INTEGRATED CIRCUIT µPD720100A USB2.0 HOST CONTROLLER The µPD720100A complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The µPD720100A is integrated three host controller cores with PCI interface and USB2.0 transceivers into a single chip. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. µPD720100A User’s Manual: S15534E FEATURES • Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps) • Compliant with Open Host Controller Interface Specification for USB Rev 1.0a • Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95 • PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling. • Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core • All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. • Configurable number of downstream facing ports (2 to 5) • 32-bit 33 MHz host interface compliant to PCI Specification release 2.2. • Supports PCI Mobile Design Guide Revision 1.1. • Supports PCI-Bus Power Management Interface Specification release 1.1. • PCI Bus bus-master access • System clock is generated by 30 MHz X’tal or 48 MHz clock input. • Operational registers direct-mapped to PCI memory space • Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation. • 3.3 V power supply, PCI signal pins have 5 V tolerant circuit. ORDERING INFORMATION Part Number Package µPD720100AGM-8ED 160-pin plastic LQFP (Fine pitch) (24 × 24) µPD720100AGM-8EY 160-pin plastic LQFP (Fine pitch) (24 × 24) µPD720100AS1-2C 176-pin plastic FBGA (15 × 15) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15535EJ2V0DS00 (2nd edition) Date Published October 2002 NS CP (K) Printed in Japan The mark shows major revised points. © 2001 µPD720100A BLOCK DIAGRAM PCI Bus PME0 INTA0 INTB0 INTC0 PCI Bus Interface WakeUp_Event WakeUp_Event WakeUp_Event Arbiter OHCI Host Controller #1 OHCI Host Controller #2 EHCI Host Controller SMI0 Root Hub PHY Port 1 Port 2 Port 3 USB Bus 2 Data Sheet S15535EJ2V0DS Port 4 Port 5 µPD720100A PCI Bus Interface :handles 32-bits 33 MHz PCI Bus master and target function which comply with PCI specification release 2.2. The number of enabled ports are set by bit in configuration space. Arbiter :arbitrates among two OHCI Host controller cores and one EHCI Host controller core. OHCI Host Controller #1 :handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5. OHCI Host Controller #2 :handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4. EHCI Host Controller :handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5. Root Hub :handles USB hub function in Host controller and controls connection (routing) PHY :consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer, INTA0 :is the PCI interrupt signal for OHCI Host Controller #1. between Host controller core and port. etc INTB0 :is the PCI interrupt signal for OHCI Host Controller #2. INTC0 :is the PCI interrupt signal for EHCI Host Controller. SMI0 :is the interrupt signal which is specified by Open Host Controller Interface Specification for USB Rev 1.0a. The SMI signal of each OHCI Host Controller appears at this signal. PME0 :is the interrupt signal which is specified by PCI-Bus Power Management Interface Specification release 1.1. Wakeup signal of each host controller core appears at this signal. Data Sheet S15535EJ2V0DS 3 µPD720100A PIN CONFIGURATION • 160-pin plastic LQFP (Fine pitch) (24 × 24) µPD720100AGM-8ED µPD720100AGM-8EY 121 125 130 135 140 145 150 155 1 120 5 115 10 110 15 105 20 100 25 95 30 90 35 85 40 80 75 70 65 60 55 50 45 41 81 VSS VSS AD23 SMC SIN/TIN SOT/TOUT AD22 AD21 AD20 AD19 VDD AD18 AD17 AD16 CBE20 FRAME0 IRDY0 TRDY0 DEVSEL0 VDD_PCI STOP0 PERR0 SERR0 PAR CBE10 VSS AD15 AD14 AD13 VDD AD12 AD11 AD10 AD9 AD8 CBE00 AD7 AD6 VSS VSS VDD NTEST1 NTEST2 TEST XT1/SCLK XT2 LEGC VDD VSS VCCRST0 SMI0 IRI1 IRI2 IRO1 IRO2 A20S PME0 PCLK VBBRST0 VDD VSS VDD_PCI INTA0 INTB0 INTC0 PIN_EN GNT0 REQ0 AD31 AD30 VSS AD29 AD28 AD27 AD26 AD25 AD24 CBE30 IDSEL VDD 160 VSS VSS RSDP4 DP4 VDD DM4 RSDM4 VSS RSDP3 DP3 VDD DM3 RSDM3 VSS VDD AVSS RREF AVSS(R) AVDD N.C. PC1 AVSS PC2 AVDD AVSS VDD VSS RSDP2 DP2 VDD DM2 RSDM2 VSS RSDP1 DP1 VDD DM1 RSDM1 VSS VSS Top View 4 Data Sheet S15535EJ2V0DS VDD SELCLK N.C. SELDAT VSS RSDP5 DP5 VDD DM5 RSDM5 VSS CLKSEL VSS PPON5 TEB PPON4 SCK/TCLK PPON3 PPON2 VSS VDD OCI3 AMC OCI4 OCI2 OCI5 PPON1 OCI1 SRMOD SRCLK SRDTA VDD_PCI CRUN0 AD0 AD1 AD2 AD3 AD4 AD5 VDD µPD720100A Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VDD 41 VSS 81 VDD 121 VSS 2 NTEST1 42 VSS 82 AD5 122 VSS 3 NTEST2 43 AD23 83 AD4 123 RSDM1 4 TEST 44 SMC 84 AD3 124 DM1 5 XT1/SCLK 45 SIN/TIN 85 AD2 125 VDD 6 XT2 46 SOT/TOUT 86 AD1 126 DP1 7 LEGC 47 AD22 87 AD0 127 RSDP1 8 VDD 48 AD21 88 CRUN0 128 VSS 9 VSS 49 AD20 89 VDD_PCI 129 RSDM2 10 VCCRST0 50 AD19 90 SRDTA 130 DM2 11 SMI0 51 VDD 91 SRCLK 131 VDD 12 IRI1 52 AD18 92 SRMOD 132 DP2 13 IRI2 53 AD17 93 OCI1 133 RSDP2 14 IRO1 54 AD16 94 PPON1 134 VSS 15 IRO2 55 CBE20 95 OCI5 135 VDD 16 A20S 56 FRAME0 96 OCI2 136 AVSS 17 PME0 57 IRDY0 97 OCI4 137 AVDD 18 PCLK 58 TRDY0 98 AMC 138 PC2 19 VBBRST0 59 DEVSEL0 99 OCI3 139 AVSS 20 VDD 60 VDD_PCI 100 VDD 140 PC1 21 VSS 61 STOP0 101 VSS 141 N.C. 22 VDD_PCI 62 PERR0 102 PPON2 142 AVDD 23 INTA0 63 SERR0 103 PPON3 143 AVSS (R) 24 INTB0 64 PAR 104 SCK/TCLK 144 RREF 25 INTC0 65 CBE10 105 PPON4 145 AVSS 26 PIN_EN 66 VSS 106 TEB 146 VDD 27 GNT0 67 AD15 107 PPON5 147 VSS 28 REQ0 68 AD14 108 VSS 148 RSDM3 29 AD31 69 AD13 109 CLKSEL 149 DM3 30 AD30 70 VDD 110 VSS 150 VDD 31 VSS 71 AD12 111 RSDM5 151 DP3 32 AD29 72 AD11 112 DM5 152 RSDP3 33 AD28 73 AD10 113 VDD 153 VSS 34 AD27 74 AD9 114 DP5 154 RSDM4 35 AD26 75 AD8 115 RSDP5 155 DM4 36 AD25 76 CBE00 116 VSS 156 VDD 37 AD24 77 AD7 117 SELDAT 157 DP4 38 CBE30 78 AD6 118 N.C. 158 RSDP4 39 IDSEL 79 VSS 119 SELCLK 159 VSS 40 VDD 80 VSS 120 VDD 160 VSS Remark AVSS (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. Data Sheet S15535EJ2V0DS 5 µPD720100A • 176-pin plastic FBGA (15 × 15) µPD720100AS1-2C Bottom View 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 30 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 46 16 29 88 141 142 143 144 145 146 147 148 149 150 151 152 153 104 47 15 28 87 140 171 172 173 154 105 48 14 27 86 139 155 106 49 13 26 85 138 156 107 50 12 25 84 137 157 108 51 11 24 83 136 170 174 158 109 52 10 23 82 135 169 175 159 110 53 9 22 81 134 168 176 160 111 54 8 21 80 133 161 112 55 7 20 79 132 162 113 56 6 19 78 131 163 114 57 5 18 77 130 164 115 58 4 17 76 129 128 127 126 16 75 74 73 72 15 14 13 T R P U 6 17 167 166 165 125 124 123 122 121 120 119 118 117 116 59 3 71 70 69 68 67 66 65 64 63 62 61 60 2 12 11 10 9 8 7 6 5 4 3 2 1 N M L K J H G F E D C B Data Sheet S15535EJ2V0DS 1 A µPD720100A Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 45 VDD 89 SELCLK 133 PPON1 2 VSS 46 NTEST1 90 VSS 134 OCI4 3 SMC 47 NANDTEST 91 RSDM1 135 VSS 4 AD20 48 TEST 92 RSDP1 136 SCK/TCLK 5 AD18 49 VSS 93 DM2 137 PPON5 6 CBE20 50 IRI1 94 RSDP2 138 VSS 7 DEVSEL0 51 IRO2 95 AVSS 139 VDD 8 VDD_PCI 52 VBBRST0 96 PC2 140 RSDP5 9 SERR0 53 VDD 97 AVSS 141 VDD 10 VSS 54 INTA0 98 DM3 142 DP1 11 AD14 55 PIN_EN 99 DP3 143 VSS 12 AD11 56 REQ0 100 RSDM4 144 VDD 13 CBE00 57 AD29 101 DP4 145 VSS 14 AD6 58 AD25 102 VSS 146 AVDD 15 VSS 59 CBE30 103 VSS 147 N.C. 16 AD5 60 N.C. 104 VDD 148 RREF 17 N.C. 61 IDSEL 105 NTEST2 149 VSS 18 AD3 62 VSS 106 LEGC 150 VDD 19 VDD_PCI 63 AD23 107 VCCRST0 151 VSS 20 SRMOD 64 AD22 108 IRI2 152 DM4 21 OCI5 65 AD19 109 A20S 153 XT1/SCLK 22 OCI3 66 AD17 110 PCLK 154 XT2 23 VDD 67 FRAME0 111 INTC0 155 VDD 24 PPON3 68 TRDY0 112 AD31 156 SMI0 25 TEB 69 CBE10 113 VSS 157 IRO1 26 VSS 70 AD13 114 AD27 158 PME0 27 DM5 71 AD12 115 AD24 159 VSS 28 VSS 72 AD9 116 VDD 160 INTB0 29 N.C. 73 AD7 117 SIN/TIN 161 GNT0 30 N.C. 74 VSS 118 SOT/TOUT 162 AD30 31 VSS 75 VSS 119 AD21 163 AD28 32 N.C. 76 VDD 120 VDD 164 AD26 33 DM1 77 AD4 121 AD16 165 VSS 34 RSDM2 78 AD0 122 IRDY0 166 VDD 35 DP2 79 SRDTA 123 STOP0 167 PERR0 36 VDD 80 OCI1 124 PAR 168 VSS 37 AVSS 81 OCI2 125 AD15 169 VSS 38 PC1 82 AMC 126 VDD 170 PPON2 39 AVSS (R) 83 PPON4 127 AD10 171 VSS 40 VDD 84 CLKSEL 128 AD8 172 VSS 41 RSDM3 85 RSDM5 129 AD2 173 AVDD 42 RSDP3 86 DP5 130 AD1 174 VSS 43 N.C.(VDD) 87 SELDAT 131 CRUN0 175 VDD 44 RSDP4 88 VDD 132 SRCLK 176 VDD_PCI Remarks 1. Pin 43 can be opened. But this signal is connected to pin 45 in the package. Should not be connected to GND. 2. AVSS (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ. Data Sheet S15535EJ2V0DS 7 µPD720100A 1. PIN INFORMATION (1/2) Pin Name I/O Buffer Type Active Function Level 8 AD (31 : 0) I/O 5 V PCI I/O PCI “AD [31 : 0]” signal CBE (3 : 0)0 I/O 5 V PCI I/O PCI “C/BE [3 : 0]” signal PAR I/O 5 V PCI I/O PCI “PAR” signal FRAME0 I/O 5 V PCI I/O PCI “FRAME#” signal IRDY0 I/O 5 V PCI I/O PCI “IRDY#” signal TRDY0 I/O 5 V PCI I/O PCI “TRDY#” signal STOP0 I/O 5 V PCI I/O PCI “STOP#” signal IDSEL I 5 V PCI Input PCI “IDSEL” signal DEVSEL0 I/O 5 V PCI I/O PCI “DEVSEL#” signal REQ0 O 5 V PCI Output PCI “REQ#” signal GNT0 I 5 V PCI Input PCI “GNT#” signal PERR0 I/O 5 V PCI I/O PCI “PERR#” signal SERR0 O 5 V PCI N-ch Open Drain PCI “SERR#” signal INTA0 O 5 V PCI N-ch Open Drain Low PCI “INTA#” signal INTB0 O 5 V PCI N-ch Open Drain Low PCI “INTB#” signal INTC0 O 5 V PCI N-ch Open Drain Low PCI “INTC#” signal PCLK I 5 V PCI Input VBBRST0 I 5 V PCI Input PCI “CLK” signal Low Hardware Reset for Chip CRUN0 I/O 5 V PCI I/O PCI “CLKRUN#” signal PME0 O 5 V PCI N-ch Open Drain Low PCI “PME#” signal VCCRST0 I 5 V tolerant Input Low RESET for Power Management SMI0 O 5 V tolerant N-ch Open Drain Low System management interrupt output PIN_EN I 5 V tolerant Input High PCI Interface enable XT1/SCLK I Input System clock input or Oscillator In XT2 O Output Oscillator Out DP (5 : 1) I/O USB high speed D+I/O USB’s high speed D+ signal DM (5 : 1) I/O USB high speed D−I/O USB’s high speed D− signal RSDP (5 : 1) O USB full speed D+ O USB’s full speed D+ signal RSDM (5 : 1) O USB full speed D− O USB’s full speed D− signal OCI (5 : 1) I (I/O) 5 V tolerant Input Low USB Root Hub Port’s overcurrent status input PPON (5 : 1) O (I/O) 5 V tolerant Output High USB Root Hub Port’s power supply control output LEGC I (I/O) Input High Legacy support switch IRI1 I (I/O) 5 V tolerant Input High INT input from keyboard IRI2 I (I/O) 5 V tolerant Input High INT input from mouse IRO1 O 5 V tolerant Output High INT output from keyboard IRO2 O 5 V tolerant Output High INT output from mouse A20S O 5 V tolerant 3-state Output Data Sheet S15535EJ2V0DS GateA20 State output µPD720100A (2/2) Pin Name I/O Buffer Type Active Function Level RREF A Analog Reference resistor PC1 A Analog Capacitor for PLL PC2 A Analog Capacitor for PLL NTEST(2:1) I Input with 12 kΩ Pull down R High Test pin SMC I Input with 50 kΩ Pull down R High Scan mode control SIN/TIN I Input with 50 kΩ Pull down R Scan input or RAM BIST input SOT/TOUT O Output Scan output or RAM BIST output TEB I Input with 50 kΩ Pull down R High BIST enable AMC I Input with 50 kΩ Pull down R High ATG mode control SCK/TCLK I Input with 50 kΩ Pull down R Scan clock or RAM BIST clock CLKSEL I Input with 50 kΩ Pull down R Clock select signal TEST I Input with 50 kΩ Pull down R High Test Control NANDTEST I Input with 50 kΩ Pull down R High NAND Tree Test enable SELDAT O Output Test signal SELCLK O Output Test signal SRCLK O Output Serial ROM Clock Out SRDTA I/O I/O Serial ROM Data SRMOD I Input with 50 kΩ Pull down R High Serial ROM Input Enable AVDD VDD for Analog circuit VDD VDD VDD_PCI 5 V (5 V PCI) or 3.3 V (3.3 V PCI) AVSS VSS for Analog circuit VSS VSS N.C. Not connect Remarks 1. “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit. 2. “5 V PCI” indicates a PCI buffer, which complies with the 3 V PCI standard, has a 5 V tolerant circuit. It does not indicate a buffer that fully complies with 5 V PCI standard. However, this function can be used for evaluating the operation of a device on a 5V add-in card. 3. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use. Data Sheet S15535EJ2V0DS 9 µPD720100A 2. ELECTRICAL SPECIFICATIONS 2.1 Buffer List • 3 V input buffer with Pull down resister • 3 V output buffer • 3 V bi-directional buffer • 3 V Oscillator interface • 5 V input buffer • 5 V IOL = 12 mA N-ch Open Drain buffer • 5 V IOL = 6 mA 3-state Output buffer • 5 V IOL = 12 mA 3-state Output buffer • 5 V PCI Input buffer with enable (OR type) • 5 V PCI IOL = 12 mA 3-state Output buffer • 5 V PCI IOL = 12 mA bi-directional buffer with input enable (OR-type) NTEST1, NTEST2, TEST, SMC, SIN/TIN, SRMOD, AMC, SCK/TCLK, CLKSEL, TEB SOT/TOUT (IOL = 9 mA), SRCLK (IOL = 3 mA) LEGC (IOL = 9 mA), SRDTA (IOL = 3 mA) XT1/SCLK, XT2 VCCRST0, PIN_EN SMI0, PME0, INTA0, INTB0, INTC0, SERR0 A20S IRO1, IRO2 PCLK, VBBRST0, GNT0, IDSEL REQ0 AD(31:0), CBE(3:0)0, PAR, FRAME0, IRDY0, TRDY0, STOP0, DEVSEL0, PERR0, CRUN0, IRI(1:2), PPON(1:5), OCI(1:5) • USB interface DP(1:5), DM(1:5), RSDP(1:5), RSDM(1:5), PC1, PC2, RREF, SELDAT, SELCLK Above, “5 V” refers to a 3-V buffer with 5-V tolerant circuit. Therefore, it is possible to have a 5-V connection for an external bus, but the output level will be only up to 3 V, which is the VDD voltage. Similarly, “5 V PCI” above refers to a PCI buffer that has a 5-V tolerant circuit, which meets the 3-V PCI standard; it does not refer to a PCI buffer that meets the 5-V PCI standard. 10 Data Sheet S15535EJ2V0DS µPD720100A 2.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Power supply voltage Symbol VDD Meaning Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Input voltage VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Operating temperature TA Indicates the ambient temperature range for normal logic operations. Storage temperature Tstg Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. Terms Used in Recommended Operating Range Parameter Symbol Meaning Power supply voltage VDD Indicates the voltage range for normal logic operations occur when VSS = 0V. High-level input voltage VIH Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “MIN.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “MAX.” value is applied, the input voltage is guaranteed as low level voltage. Terms Used in DC Characteristics Parameter Off-state output leakage current Symbol IOZ Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Output short circuit current IOS Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Input leakage current II Indicates the current that flows when the input voltage is supplied to the input pin. Low-level output current IOL Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. High-level output current IOH Indicates the current that flows from the output pins when the rated highlevel output voltage is being applied. Data Sheet S15535EJ2V0DS 11 µPD720100A 2.3 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Power supply voltage VDD Input voltage, 5 V buffer VI Condition 3.0 V ≤ VDD ≤ 3.6 V Rating Unit −0.5 to +4.6 V −0.5 to +6.6 V −0.5 to +4.6 V −0.5 to +6.6 V −0.5 to +4.6 V VI < VDD + 3.0 V Input voltage, 3.3 V buffer 3.0 V ≤ VDD ≤ 3.6 V VI VI < VDD + 0.5 V Output voltage, 5 V buffer 3.0 V ≤ VDD ≤ 3.6 V VO VO < VDD + 3.0 V Output voltage, 3.3 V buffer 3.0 V ≤ VDD ≤ 3.6 V VO VO < VDD + 0.5 V Operating temperature TA 0 to +70 °C Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Recommended Operating Ranges Parameter Symbol Operating voltage VDD High-level input voltage VIH MIN. TYP. MAX. Unit 3.0 3.3 3.6 V 3.3 V High-level input voltage 2.0 VDD V 5.0 V High-level input voltage 2.0 5.5 V 3.3 V Low-level input voltage 0 0.8 V 5.0 V Low-level input voltage 0 0.8 V Low-level input voltage 12 Condition VIL Data Sheet S15535EJ2V0DS µPD720100A DC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70°°C) Control Pin Block Parameter Off-state output current Symbol IOZ Output short circuit current IOS Low-level output current IOL Condition MIN. VO = VDD or VSS Note MAX. Unit ±10 µA −250 mA 3.3 V Low-level output current VOL = 0.4 V 9.0 mA 3.3 V Low-level output current VOL = 0.4 V 3.0 mA 5.0 V Low-level output current VOL = 0.4 V 12.0 mA 5.0 V Low-level output current VOL = 0.4 V 6.0 mA 3.3 V High-level output current VOH = 2.4 V −9.0 mA 3.3 V High-level output current VOH = 2.4 V −3.0 mA 5.0 V High-level output current VOH = 2.4 V −2.0 mA 5.0 V High-level output current VOH = 2.4 V −2.0 mA High-level output current Input leakage current IOH II 3.3 V buffer VI = VDD or VSS ±10 µA 3.3 V buffer with 50 kΩ PD VI = VDD 191 µA 5.0 V buffer VI = VDD or VSS ±10 µA MIN. MAX. Unit Note The output short circuit time is one second or less and is only for one pin on the LSI. PCI Interface Block Parameter Symbol Condition High-level input voltage Vih 2.0 5.25 V Low-level input voltage Vil 0 0.8 V Low-level output current IOL VOL = 0.4 V 12.0 mA High-level output current IOH VOH = 2.4 V −2.0 mA Input high leakage current Iih Vin = 2.7 70 µA Input low leakage current Iil Vin = 0.5 −70 µA PME0 leakage current Ioff VO < 3.6 V 1 µA VCC off or floating Data Sheet S15535EJ2V0DS 13 µPD720100A USB Interface Block Parameter Serial Resistor between DP (DM) and Symbol Conditions RS MIN MAX Unit 35.64 36.36 Ω 40.5 49.5 Ω RSDP (RSDM). Output pin impedance ZHSDRV Includes RS resistor Input Levels for Low-/full-speed: High-level input voltage (drive) VIH 2.0 V High-level input voltage (floating) VIHZ 2.7 Low-level input voltage VIL Differential input sensitivity VDI (D+) − (D−) 0.2 Differential Common mode Range VCM Includes VDI range 0.8 2.5 V High-level output voltage VOH RL of 14.25 kΩ to GND 2.8 3.6 V Low-level output voltage VOL RL of 1.425 kΩ to 3.6 V 0.0 0.3 V SE1 VOSE1 0.8 Output signal crossover point voltage VCRS 1.3 2.0 V VHSSQ 100 150 mV VHSDSC 525 625 mV VHSCM −50 +500 mV 3.6 0.8 V V Output Levels for Low-/full-speed: V Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling See Figure 2-4. level Output Levels for High-speed: High-speed idle state VHSOI −10.0 +10 mV High-speed data signaling high VHSOH 360 440 mV High-speed data signaling low VHSOL −10.0 +10 mV Chirp J level (different signal) VCHIRPJ 700 1100 mV Chirp K level (different signal) VCHIRPK −900 −500 mV 14 Data Sheet S15535EJ2V0DS µPD720100A Figure 2-1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range Differential Output Crossover Voltage Range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6 Input Voltage Range (Volts) Figure 2-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver VDD-3.3 VDD-2.8 VDD-2.3 VDD-1.8 VDD-1.3 VDD-0.8 VDD-0.3 VDD 0 Iout (mA) -20 -40 Min. -60 Max. -80 Vout (V) Figure 2-3. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver 80 Max. 60 Iout (mA) -1.0 Min. 40 20 0 0 0.5 1 1.5 2 2.5 3 Vout (V) Data Sheet S15535EJ2V0DS 15 µPD720100A Figure 2-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 2-5. Receiver Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 50 Ω Coax 15.8 Ω 143 Ω 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Pin Capacitance Parameter Symbol Condition MIN. MAX. Unit Input capacitance CI VDD = 0 V, TA = 25°C 6 8 pF Output capacitance CO fC = 1 MHz 10 12 pF I/O capacitance CIO Unmeasured pins 10 12 pF 8 pF 8 pF 8 pF PCI input pin capacitance Cin PCI clock input pin capacitance Cclk PCI IDSEL input pin capacitance CIDSEL 16 returned to 0 V 6 Data Sheet S15535EJ2V0DS µPD720100A Power Consumption Parameter Symbol Power Consumption PWD0-0 Condition TYP. Unit 168.0 mA EHCI host controller is inactive. 186.2 mA EHCI host controller is active. 301.6 mA EHCI host controller is inactive. 195.3 mA EHCI host controller is active. 368.4 mA EHCI host controller is inactive. 204.4 mA EHCI host controller is active. 435.2 mA EHCI host controller is inactive. 213.5 mA EHCI host controller is active. 502.0 mA 136.2 mA 113.0 mA The power consumption under the state without suspend. Device state = D0, All the ports does not connect to any Note 1 function. PWD0-2 The power consumption under the state without suspend. Device state = D0, The number of active ports is 2. PWD0-3 PWD0-4 The power consumption under the state without suspend. Note 2 Device state = D0, The number of active ports is 3. The power consumption under the state without suspend. Device state = D0, The number of active ports is 4. PWD0-5 PWD0_S Note 2 The power consumption under the state without suspend. Note 2 Device state = D0, The number of active ports is 5. The power consumption under suspend state. Device state = D0, The internal clock is stopped. PWD0_C Note 2 Note 3 The power consumption under suspend state during PCI clock is stopped by CRUN0. Device state = D0, Note 3 The internal clock is stopped. PWD1 PWD2 PWD3H Device state = D1, Analog PLL output is stopped. Note 3, 4 24.7 mA Device state = D2, Analog PLL output is stopped. Note 3, 4 10.9 mA 10.9 mA 650 µA Device state = D3hot, PIN_EN = High Analog PLL output is stopped. PWD3C Notes Note 3, 4 Device state = D3cold , PIN_EN = Low Note 3, 4, 5 Oscillator output is stopped. 1. When any device is not connected to all the ports of HC, the power consumption for HC does not depend on the number of active ports. 2. The number of active ports is set by the value of Port No field in PCI configuration space EXT register. 3. For the condition of clock stop, see µPD720100A User’s Manual 7.3 Control for System Clock Operation. 4. When the device state = D1, PCI clock is defined as it is running. When the device state = D2 or D3, PCI clock is defined as it is stopped. 5. If 48 MHz oscillator clock-in is used, power consumption for oscillator block + HC chip will be more than 15 mA. Data Sheet S15535EJ2V0DS 17 µPD720100A System Clock Ratings Parameter Clock frequency Symbol fCLK Condition X’tal MIN. TYP. MAX. Unit −500 30 +500 MHz ppm Oscillator block −500 ppm 48 ppm Clock Duty cycle tDUTY 40 +500 MHz ppm 50 60 % Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or Oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply voltage, temperature, and aging, etc. 18 Data Sheet S15535EJ2V0DS µPD720100A AC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70°°C) PCI Interface Block Parameter Symbol Conditions MIN. MAX. Unit PCI clock cycle time tcyc 30 ns PCI clock pulse, high-level width thigh 11 ns PCI clock pulse, low-level width tlow 11 ns PCI clock, rise slew rate Scr 0.2 VDD to 0.6 VDD 1 4 V/ns PCI clock, fall slew rate Scf 0.2 VDD to 0.6 VDD 1 4 V/ns PCI reset active time trst 1 ms 100 µs (vs. power supply stability) PCI reset active time (vs. CLK Start) trst-clk Output float delay time (vs. RST0↓) trst-off PCI reset rise slew rate Srr 50 PCI bus signal output time (vs. PCLK↑) tval 2 11 ns PCI point-to-point signal output time tval (ptp) 2 12 ns 40 REQ0 ns mV/ns (vs. PCLK↑) Output delay time (vs. PCLK↑) ton 2 Output float delay time (vs. PCLK↑) toff Input setup time (vs. PCLK↑) tsu Point-to-point input setup time (vs. PCLK↑) tsu (ptp) Input hold time th ns 28 GNT0 Data Sheet S15535EJ2V0DS ns 7 ns 10 ns 0 ns 19 µPD720100A USB Interface Block (1/2) Parameter Symbol Conditions MIN. MAX. Unit 75 300 ns 75 300 ns 80 125 % 1.49925 1.50075 Mbps Low Source Electrical Characteristics Rise time (10% - 90%) tLR CL = 50 pF – 150 pF, RS = 36 Ω Fall time (90% - 10%) tLF CL = 50 pF – 150 pF, RS = 36 Ω Differential Rise and Fall Time matching tLRFM (tLR/tLF) Low-speed Data Rate tLDRATHS Average bit rate Source Jitter Total (including frequency tolerance): To Next Transition tDDJ1 −25 +25 ns For Paired Transitions tDDJ2 −14 +14 ns tLDEOP -40 +100 ns To Next Transition tUJR1 −152 +152 ns For Paired Transitions tUJR2 −200 +200 ns Source SE0 interval of EOP tLEOPT 1.25 1.50 µs Receiver SE0 interval of EOP tLEOPR 670 Width of SE0 interval during differential tFST Source Jitter for Differential Transition to SE0 transition Receiver Jitter: ns 210 ns 4 20 ns 4 20 ns 90 111.11 % 11.9940 12.0060 Mbps 0.9995 1.0005 ms 42 ns transition Full-speed Source Electrical Characteristics Rise time (10% - 90%) tFR CL = 50 pF, RS = 36 Ω Fall time (90% - 10%) tFF CL = 50 pF, RS = 36 Ω Differential Rise and Fall Time matching tFRFM (tFR/tFF) Full-speed Data Rate tFDRATHS Average bit rate Frame Interval tFRAME Consecutive Frame Interval Jitter tRFI No clock adjustment Source Jitter Total (including frequency tolerance): To Next Transition tDJ1 −3.5 +3.5 ns For Paired Transitions tDJ2 −4.0 +4.0 ns −2 +5 ns Source Jitter for Differential Transition to tFDEOP SE0 transition Receiver Jitter: To Next Transition tJR1 −18.5 +18.5 ns For Paired Transitions tJR2 −9 +9 ns Source SE0 interval of EOP tFEOPT 160 175 ns Receiver SE0 interval of EOP tFEOPR 82 Width of SE0 interval during differential tFST 14 transition 20 ns Data Sheet S15535EJ2V0DS ns µPD720100A (2/2) Parameter Symbol Conditions MIN. MAX. Unit High-speed Source Electrical Characteristics Rise time (10% - 90%) tHSR 500 ps Fall time (90% - 10%) tHSF 500 ps Driver waveform See Figure 2-6. High-speed Data Rate tHSDRAT 479.760 480.240 Mbps Microframe Interval tHSFRAM 124.9375 125.0625 µs Consecutive Microframe Interval Difference tHSRFI Data source jitter See Figure 2-6. Receiver jitter tolerance See Figure 2-4. 4 high- Bit speed times Hub event Timings Time to detect a downstream facing port tDCNN 2.5 2000 µs tDDIS 2.0 2.5 µs connect event Time to detect a disconnect event at a downstream facing port: Duration of driving resume to a tDRSMDN Nominal 20 ms downstream port Time from detecting downstream resume 1.0 tURSM ms to rebroadcast. Inter-packet Delay for packets traveling in tHSIPDSD Bit 88 times same direction for high-speed Inter-packet Delay for packets traveling in tHSIPDOD 8 Bit opposite direction for high-speed Inter-packet delay for root hub response for times tHSRSPIPD1 192 high-speed Time for which a Chirp J or Chirp K must Bit times µs 2.5 tFILT be continuously detected during Reset handshake Time after end of device Chirp K by which tWTDCH 100 µs hub must start driving first Chirp K Time for which each individual tDCHBIT 40 60 µs tDCHSE0 100 500 µs Chirp J or Chirp K in the chirp sequence is driven downstream during reset Time before end of reset by which a hub must end its downstream chirp sequence Data Sheet S15535EJ2V0DS 21 µPD720100A Figure 2-6. Transmit Waveform for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 2-7. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 15.8 Ω 143 Ω 22 50 Ω Coax 50 Ω Coax 143 Ω Data Sheet S15535EJ2V0DS + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − µPD720100A Timing Diagram PCI Clock tcyc thigh tlow 0.6VDD 0.5VDD 0.4VDD 0.3VDD 0.2VDD 0.4VDD(ptp:min) PCI Reset PCLK 100 ms (typ.) PWR_GOOD trst-clk trst VBBRST0 trst-off PCI Signals Valid PCI Output Timing Measurement Condition 0.6VDD PCLK 0.4VDD 0.2VDD tval , tval(ptp) 0.615VDD (for falling edge) output delay output 0.285VDD (for falling edge) ton toff Data Sheet S15535EJ2V0DS 23 µPD720100A PCI Input Timing Measurement Condition 0.6VDD 0.4VDD PCLK 0.2VDD tsu, tsu(ptp) th 0.6VDD input 0.4VDD 0.2VDD USB Differential Data Jitter for Low-/full-speed tPERIOD Differential Data Lines Crossover Points Consecutive Transitions N × tPERIOD + tDJ1, tDDJ1 Paired Transitions N × tPERIOD + tDJ2, tDDJ2 USB Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed tPERIOD Differential Data Lines Crossover Point Extended Crossover Point Diff. Data-toSE0 Skew N × tPERIOD + tFDEOP, tLDEOP Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR 24 Data Sheet S15535EJ2V0DS µPD720100A USB Receiver Jitter Tolerance for Low-/full-speed tPERIOD Differential Data Lines tJR, tUJR tJR1, tUJR1 tJR2, tUJR2 Consecutive Transitions N × tPERIOD + tJR1, tUJR1 Paired Transitions N × tPERIOD + tJR2, tUJR2 Low-/full-speed Disconnect Detection D+/DVIZH (min) VIL D-/D+ VSS tDDIS Device Disconnected Disconnect Detected Full-/high-speed Device Connect Detection D+ VIH DVSS tDCNN Device Connected Connect Detected Data Sheet S15535EJ2V0DS 25 µPD720100A Low-speed Device Connect Detection DVIH D+ VSS tDCNN Device Connected 26 Connect Detected Data Sheet S15535EJ2V0DS µPD720100A 3. PACKAGE DRAWING 160-PIN PLASTIC LQFP (FINE PITCH) (24x24) A B 81 80 120 121 detail of lead end S C D R Q 41 40 160 1 F G H I J M P K N S S L M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 26.0±0.2 B 24.0±0.2 C 24.0±0.2 D 26.0±0.2 F 2.25 G 2.25 H 0.22 +0.05 −0.04 I J 0.10 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.145+0.055 −0.045 N 0.10 P 1.4±0.1 Q 0.125±0.075 R 3° +7° −3° S 1.7 MAX. S160GM-50-8ED-3 Data Sheet S15535EJ2V0DS 27 µPD720100A 160-PIN PLASTIC LQFP (FINE PITCH) (24x24) A B 120 121 81 80 detail of lead end S P C D T R L Q U 41 40 160 1 F G H I J M K S ITEM MILLIMETERS A B 26.0±0.2 24.0±0.2 NOTE C D 24.0±0.2 26.0±0.2 Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. F 2.25 G 2.25 H 0.22 +0.05 −0.04 N S M I 0.08 J K 0.5 (T.P.) 1.0±0.2 L 0.5 M 0.17 +0.03 −0.07 N 0.08 P Q 1.4±0.05 0.10±0.05 R 3° +4° −3° S 1.6 MAX. T U 0.25 (T.P.) 0.16±0.15 P160GM-50-8EY 28 Data Sheet S15535EJ2V0DS µPD720100A 176-PIN PLASTIC FBGA (15x15) A W S B B B 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A C D U T RP NM L K J H G F E D C B A P Index mark Q W S A J I Y1 S H R ITEM S K F S L E φM M G S A B MILLIMETERS A 15.00±0.10 B 14.40 C 14.40 D 15.00±0.10 E 1.10 F G 0.8 (T.P.) 0.35±0.1 H 0.36 I 1.16 J 1.51±0.15 K 0.10 L φ 0.50+0.05 −0.10 M P 0.08 C1.0 Q R0.3 R W 25° 0.20 Y1 0.20 S176S1-80-2C-1 Data Sheet S15535EJ2V0DS 29 µPD720100A 4. RECOMMENDED SOLDERING CONDITIONS The µPD720100A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. µPD720100AGM-8ED: 160-pin plastic LQFP (Fine pitch) (24 × 24) µPD720100AGM-8EY: 160-pin plastic LQFP (Fine pitch) (24 × 24) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Symbol IR35-103-3 Count: Three times or less Exposure limit: 3 days Partial heating Note (after that, prebake at 125°C for 10 hours) Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. µPD720100AS1-2C: 176-pin plastic FBGA (15 × 15) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Symbol IR35-107-3 Count: Three times or less Exposure limit: 7 days Partial heating Note (after that, prebake at 125°C for 10 hours) Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. 30 Data Sheet S15535EJ2V0DS µPD720100A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC l2C components conveys a license under the Philips l2C Patent Rights to use these components in an l2C system, provided that the system conforms to the l 2C Standard Specification as defined by Philips. Data Sheet S15535EJ2V0DS 31 µPD720100A USB logo is a trademark of USB Implementers Forum, Inc. • The information in this document is current as of October, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4