NEC UPD75116HGC

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75116H,75117H
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75117H is a 75X Series 4-bit single-chip microcomputer.
The µPD75117H is a product which has the same functions as those of the µPD751××F, with the minimum
operating voltage reduced from the previous 2.7 V to 1.8 V, and achieving 1.91 µs operation at 1.8 V. Therefore, it facilitates low-voltage operation for a set requiring high-speed operation.
Functions are described in detail in the following User’s Manual, which should be read when carrying out
design work.
µPD75117H User’s Manual : IEU-799
FEATURES
• Memory capacity
ROM : 24448 × 8 bits (µPD75117H)
: 16256 × 8 bits (µPD75116H)
RAM : 768 × 4 bits
• High-speed low voltage operation
Minimum instruction execution time :
• Operating voltage range
• Input/output ports : 58
• Timer/counter
: 3 channels
• Timer/event counter × 2 channels
• Basic interval timer × 1 channel
• 8-bit serial interface on chip
• Programmable threshold port
• On-chip PROM product available
1.91 µs (VDD = 1.8 V)
0.95 µs (VDD = 2.7 V)
:
1.8 to 5.5 V (Ta = –40 to +60 °C)
:
:
4-bit resolution × 4 channels
µPD75P117H (One-time PROM)
★
APPLICATIONS
Cordless telephone subsets, portable radio equipment, pager, etc.
"Unless there are any particular functional differences, the µPD75117H is described in this document as a
representative product."
The information in this document is subject to change without notice.
Document No. IC-3120
(O.D.No. IC-8502)
Date Published May 1994P
Printed in Japan
The mark ★ shows major revised points.
© NEC Corporation 1994
µPD75116H,75117H
ORDERING INFORMATION
Ordering Code
Package
µPD75116HGC-×××-AB8
µPD75116HGK-×××-8A8
µPD75117HGC-×××-AB8
µPD75117HGK-×××-8A8
Remarks
64-pin
64-pin
64-pin
64-pin
plastic
plastic
plastic
plastic
QFP
QFP
QFP
QFP
Quality Grade
(
(
(
(
14
12
14
12
mm)
mm)
mm)
mm)
Standard
Standard
Standard
Standard
×××: ROM code number
OVERVIEW OF FUNCTIONS
Item
Contents
Basic instructions
43
Instruction cycle
0.95 µs, 1.91 µs, 15.3 µs (4.19 MHz operation)
3-stage switching capability
ROM
24448 × 8 bits (µPD75117H), 16256 × 8 bits (µPD75116H)
RAM
768 × 4 bits
On-chip memory
General register
4 bits × 8 × 4 banks (memory mapping)
Total 58
• CMOS input pins
• CMOS input/output pins
Input/output port
★
: 10
: 32 (pins with LED direct drive
capability*1)
• N-ch open-drain input/output pins
: 12 (pins with LED direct drive
capability*2)
(A pull-up resistor can be incorporated bit-wise.)
• Comparator input pins (4-bit precision) : 4
Timer/counter
• 8-bit timer/event counter × 2
• 8-bit basic interval timer (watchdog timer applicable)
Serial interface
• 8 bits
• LSB-first/MSB-first switchable
• 2 transfer modes (transmission/reception and dedicated reception modes)
Vectored interrupt
• External :
• Internal :
3
4
Test input
• External :
2
Standby
• STOP/HALT mode
Instruction set
•
•
•
•
Others
• Bit manipulation memory (bit sequential buffer: 16 bits) on chip
Package
• 64-pin plastic QFP ( 14 mm)
• 64-pin plastic QFP ( 12 mm)
Various bit manipulation instructions (set, reset, test, Boolean operation)
8-bit data transfer, comparison, operation, increment/decrement instructions
1-byte relative branch instruction
GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1
byte
★ * 1. When VDD = 5 V, IOL = 15 mA.
★
2. When VDD = 5 V, IOL = 10 mA.
2
µPD75116H,75117H
DIFFERENCES BETWEEN µPD75116H AND µPD75117H
Item
ROM
★
µPD75116H
µPD75117H
16256 × 8 bits
(Mask ROM)
24448 × 8 bits
(Mask ROM)
768 × 4 bits
RAM
SBS register
No
Yes
Memory bank 0
Memory banks 0, 1, 2
2-byte stack
3-byte stack
CALL instruction machine cycle
3 machine cycles
4 machine cycles
CALLF instruction machine cycle
2 machine cycles
3 machine cycles
Undefined operation
Normal operation
Stack
Stack area
Stack operation when subroutine call
instruction is executed
BRA instruction
CALLA instruction
MOVT XA, BCDE
MOVT XA, BCXA
BR BCDE
BR BCXA
3
µPD75116H,75117H
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) ......................................................................................................
6
2.
BLOCK DIAGRAM ...................................................................................................................................
8
3.
PIN FUNCTIONS .....................................................................................................................................
9
3.1
3.2
3.3
3.4
PORT PINS ....................................................................................................................................................... 9
OTHER PINS ..................................................................................................................................................... 10
PIN INPUT/OUTPUT CIRCUITS ..................................................................................................................... 11
RECOMMENDED CONNECTION OF UNUSED PINS ................................................................................... 12
4.
MEMORY CONFIGURATION ................................................................................................................. 13
5.
PERIPHERAL HARDWARE FUNCTIONS ............................................................................................... 18
5.1
5.2
5.3
PORT ................................................................................................................................................................. 18
CLOCK GENERATOR ....................................................................................................................................... 19
CLOCK OUTPUT CIRCUIT ............................................................................................................................... 20
5.4
5.5
5.6
5.7
BASIC INTERVAL TIMER ................................................................................................................................
TIMER/EVENT COUNTER ...............................................................................................................................
SERIAL INTERFACE .........................................................................................................................................
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) ..............................................................
5.8
BIT SEQUENTIAL BUFFER ............................................................................................................................. 26
21
21
23
25
6.
INTERRUPT FUNCTION ........................................................................................................................ 27
7.
STANDBY FUNCTION ............................................................................................................................ 29
8.
RESET FUNCTION .................................................................................................................................. 30
9.
INSTRUCTION SET ................................................................................................................................. 33
10. APPLICATION EXAMPLE ....................................................................................................................... 43
10.1 CORDLESS TELEPHONE (SUBSET) .............................................................................................................. 43
10.2 DISPLAY PAGER .............................................................................................................................................. 44
11. MASK OPTION SELECTION ................................................................................................................... 45
12. ELECTRICAL SPECIFICATIONS ............................................................................................................. 46
13. PACKAGE INFORMATION ..................................................................................................................... 57
14. RECOMMENDED SOLDERING CONDITIONS ...................................................................................... 59
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG µPD751×× SERIES PRODUCTS ......................... 60
4
µPD75116H,75117H
APPENDIX B. DEVELOPMENT TOOLS ........................................................................................................ 62
APPENDIX C. RELATED DOCUMENTS ........................................................................................................ 63
5
µPD75116H,75117H
P70
P71
P72
P73
P60
P61
P62
P63
X1
X2
RESET
P50
P51
P52
P53
P40
1. PIN CONFIGURATION (TOP VIEW)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
1
P41
P82
2
47
P42
P81
3
46
P43
P80
4
45
P30
P93
5
44
P31
P92
6
43
P32
P91
7
42
P33
P90
8
41
V DD
V SS
9
40
IC*
39
P140
38
P141
P130
PTH02
15
34
P131
PTH01
16
17
P132
6
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
32
P133
35
P120
14
P121
PTH03
P122
P143
P123
36
P00/INT4
13
P01/SCK
P10/INT0
P02/SO
P142
P03/SI
37
P20/PTO0
12
P21/PTO1
P11/INT1
P22/PCL
11
P23
P12/INT2
TI1
10
TI0
P13/INT3
PTH00
*
µPD75116HGC-×××-AB8
µPD75116HGK-×××-8A8
µPD75117HGC-×××-AB8
µPD75117HGK-×××-8A8
P83
Connect the IC (Internally Connected ) pin to VDD directly.
µPD75116H,75117H
Pin Name
P00-P03
:
Port 0
PCL
:
Programmable Clock Output
P10-P13
P20-P23
P30-P33
P40-P43
:
:
:
:
Port
Port
Port
Port
1
2
3
4
SCK
SO
SI
PTH00-PTH03
:
:
:
:
Serial Clock
Serial Data Output
Serial Data Input
Programmable Treshold Input
P50-P53
P60-P63
P70-P73
P80-P83
:
:
:
:
Port
Port
Port
Port
5
6
7
8
INT0, INT1, INT4 :
INT2, INT3
:
X1, X2
:
RESET
:
External Vectored Interrupt Input 0, 1, 4
External Test Input 2, 3
System Clock Oscillation 1, 2
Reset
P90-P93
P120-P123
P130-P133
P140-P143
:
:
:
:
Port
Port
Port
Port
9
12
13
14
VDD
VSS
IC
Positive Power Supply
Ground
Internally Connected
TI0, TI1
PTO0, PTO1
:
:
Timer Input 0, 1
Programmable Timer
Output 0, 1
:
:
:
7
INTBT
BIT SEQ.
BUFFER
(16)
SP(8)
PROGRAM
COUNTER (15) *1
ALU
TIMER/EVENT
COUNTER
#0
TI0
PTO0/P20
CY
TIMER/EVENT
COUNTER
#1
INTT1
SI/P03
SERIAL
INTERFACE
SO/P02
SCK/P01
4
P00-P03
PORT 1
4
P10-P13
PORT 2
4
P20-P23
PORT 3
4
P30-P33
PORT 4
4
P40-P43
PORT 5
4
P50-P53
PORT 6
4
P60-P63
PORT 7
4
P70-P73
PORT 8
4
P80-P83
PORT 9
4
P90-P93
PORT 12
4
P120-P123
PORT 13
4
P130-P133
PORT 14
4
P140-P143
SBS(2) *2
BANK
INTT0
TI1
PTO1/P21
PORT 0
2. BLOCK DIAGRAM
8
BASIC
INTERVAL
TIMER
ROM
PROGRAM
MEMORY
16256 × 8 BITS
: µPD75116H
24448 × 8 BITS
: µPD75117H
GENERAL REG.
DECODE
AND
CONTROL
RAM
DATA
MEMORY
768 × 4 BITS
INTSIO
INT0/P10
INT1/P11
INT2/P12
INT3/P13
INT4/P00
INTERRUPT
CONTROL
N
fX / 2
4
CLOCK
OUTPUT
CONTROL
PCL/P22
CLOCK
DIVIDER
CLOCK
GENERATOR
X1
STAND BY
CONTROL
CPU CLOCK
Φ
X2
VDD
VSS RESET
* 1. The µPD75116H program counter is composed of 14 bits.
2. The µPD75117H incorporates the SBS register.
µPD75116H,75117H
PTH00-PTH03
PROGRAMMABLE
THRESHOLD
PORT #0
µPD75116H,75117H
3. PIN FUNCTIONS
3.1
PORT PINS
Pin Name
Input/Output
DualFunction Pin
P00
Input
INT4
P01
Input/output
SCK
Function
8-bit I/O
Input/output
SO
P03
Input
SI
P10
I/O Circuit
Type *1
B
F
4-bit input port (PORT 0).
P02
Reset
Input
E
B
×
INT0
P11
INT1
4-bit input port (PORT 1).
Input
P12
INT2
P13
INT3
P20
PTO0
P21
Input
B
Input
E
PTO1
4-bit input/output port (PORT 2).
Input/output
P22
PCL
P23
—
*2
—
Programmable 4-bit input/output port (PORT 3).
Input/output can be specified bit-wise.
*2
Input
E
×
P30 to P33
Input/output
P40 to P43
Input/output
—
4-bit input/output port (PORT 4).
*2
Input
E
P50 to P53
Input/output
—
4-bit input/output port (PORT 5).
*2
Input
E
P60 to P63
Input/output
—
Programmable 4-bit input/output port (PORT 6).
Input/output can be specified bit-wise.
*2
Input
E
P70 to P73
Input/output
—
4-bit input/output port (PORT 7).
*2
Input
E
P80 to P83
Input/output
—
4-bit input/output port (PORT 8).
*2
Input
E
P90 to P93
Input/output
—
4-bit input/output port (PORT 9).
*2
Input
E
—
N-ch open-drain 4-bit input/output port (PORT
12).
On-chip pull-up resistor can be specified bitwise (mask option).
Open-drain: +6 V withstand voltage
*3
Input *4
M
—
N-ch open-drain 4-bit input/output port (PORT
13).
On-chip pull-up resistor can be specified bitwise (mask option).
Open-drain: +6 V withstand voltage
*3
Input *4
M
—
N-ch open-drain 4-bit input/output port (PORT
14).
On-chip pull-up resistor can be specified bitwise (mask option).
Open-drain: +6 V withstand voltage
*3
Input *4
M
P120 to P123
P130 to P133
P140 to P143
Input/output
Input/output
Input/output
—
* 1.
: Schmitt trigger input
2. Direct LED drive capability (When VDD = 5 V, IOL = 15 mA).
★
★
3. Direct LED drive capability (When VDD = 5 V, IOL = 10 mA).
4. Open-drain … high impedance
On-chip pull-up resistor … high level
9
µPD75116H,75117H
3.2
OTHER PINS
Pin Name
Input/Output
DualFunction Pin
PTH00 to PTH03
Input
—
Variable threshold voltage 4-bit analog input port.
N
Input
—
External event pulse input to timer/event counter.
Or edge detection vectored interrupt input, or 1-bit input
is also possible.
B
TI0
TI1
Input/output
I/O Circuit
Type *1
Timer/event counter output.
Input
E
P21
PTO1
SCK
Input/output
P01
Serial clock input/output.
Input
F
SO
Input/output
P02
Serial data output.
Input
E
SI
Input
P03
Serial data input.
Input
B
INT4
Input
P00
Edge detection vector interrupt input (detection of both
rising and falling edges)
Input
B
Edge detection vector interrupt input (detection edge
selectable)
Input
B
Edge detection test input (rising edge detection)
Input
B
Clock output
Input
E
P10
INT0
Input
P11
INT1
P12
INT2
Input
P13
INT3
10
Reset
P20
PTO0
*
Function
PCL
Input/output
P22
X1, X2
Input
—
System clock oscillation crystal/ceramic connection pin.
When an external clock is used, the clock is input to X1
and the inverted clock is input to X2.
RESET
Input
—
System reset input (low-level active).
IC
—
—
Internally Connected. IC pin should be connected to VDD
directly.
VDD
—
—
Positive power supply.
VSS
—
—
GND potential.
: Schmitt trigger input
B
µPD75116H,75117H
3.3 PIN INPUT/OUTPUT CIRCUITS
The input/output circuits of each pin of the µPD75117H are shown by in abbreviated form.
Fig. 3-1 Pin Input/Output Circuit List
Type F
Type A
VDD
data
IN/OUT
Type D
P-ch
output
disable
IN
Type B
N-ch
This is an input/output circuit made up of a Type D
push-pull output and Type B Schmitt-triggered input.
CMOS standard input buffer
Type B
VDD
Type M
Pull-Up Resistor
(Mask Option)
N-ch
(+6 V
Withstand
Voltage)
data
IN
output
disable
Middle-High Voltage Input Buffer
(+6 V Withstand Voltage)
Schmitt-trigger input with hysteresis characteristic
Type D
IN/OUT
Type N
Comparator
VDD
data
P-ch
+
OUT
–
output
disable
N-ch
VREF (Threshold Voltage)
Push-pull output that can be made highimpedance output (P-ch and N-ch OFF)
Type E
data
IN/OUT
Type D
output
disable
Type A
This is an input/output circuit made up of a
Type D push-pull output and Type A input buffer.
11
µPD75116H,75117H
3.4
RECOMMENDED CONNECTION OF UNUSED PINS
Recommended Connection
Pin
PTH00 to PTH03
TI0
Connect to VSS or VDD.
TI1
P00
Connect to VSS.
P01 to P03
Connect to VSS or VDD.
P10 to P13
Connect to VSS.
P20 to P23
P30 to P33
P40 to P43
P50 to P53
Input status
: Connect to VSS or VDD.
Output status
: Leave open.
P60 to P63
P70 to P73
P80 to P83
P90 to P93
P120 to P123
P130 to P133
P140 to P143
IC
12
Connect to V DD directly.
µPD75116H,75117H
4. MEMORY CONFIGURATION
• Program memory (ROM)
:
24448 × 8 bits (0000H to 5F7FH) : µPD75117H
16256 × 8 bits (0000H to 3F7FH) : µPD75116H
• 0000H, 0001H
: Vector table in which a program start address after reset is written.
• 0002H to 000BH : Vector table in which program start addresses after interruption are written.
• 0020H to 007FH
: Table area referred by GETI instruction
• Data memory
• Data area : 768 × 4 bits (000H to 2FFH)
• Peripheral hardware area : 128 × 4 bits (F80H to FFFH)
13
µPD75116H,75117H
Fig. 4-1 Program Memory Map (1/2)
(a) µPD75117H
Address
7
0000H
MBE
6
RBE
0
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
MBE
0002H
RBE
INTBT/INT4 Start Address (High-Order 6 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
MBE
0004H
RBE
INT0/INT1 Start Address (High-Order 6 Bits)
CALLF
! faddr
Instruction
Entry
Address
INT0/INT1 Start Address (Low-Order 8 Bits)
MBE
0006H
RBE
INTSIO Start Address (High-Order 6 Bits)
INTSIO Start Address (Low-Order 8 Bits)
MBE
0008H
RBE
BRCB
! caddr
Instruction
Branch
Address
INTT0 Start Address (High-Order 6 Bits)
INTT0 Start Address (Low-Order 8 Bits)
000AH
MBE
RBE
INTT1 Start Address (High-Order 6 Bits)
INTT1 Start Address (Low-Order 8 Bits)
≈
≈
BR !addr
Instruction
Branch Address
CALL !addr
Instruction
Branch Address
0020H
Branch/Call
Address
by GETI
GETI Instruction Reference Table
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
4000H
4FFFH
5000H
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
BR BCDE
BR BCXA
Branch Address
BRA !addr1
Instruction
Branch Address
CALLA !addr1
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BR $addr1 Instruction
Relative Branch
Address
(-15 to -1, +2 to +16)
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
5F7FH
Note
Since the above interrupt vector start address is a 14-bit address, set it in a 16K space (0000H to
3FFFH).
Remarks Apart from the above instructions, branching is possible to an address at which only the PC loworder 8 bits have been changed by the BR PCDE or BR PCXA instruction.
14
µPD75116H,75117H
Fig. 4-1 Program Memory Map (2/2)
(b) µPD75116H
Address
7
0000H
6
MBE
RBE
0
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
0002H
0004H
0006H
0008H
000AH
MBE
MBE
MBE
MBE
MBE
RBE
RBE
RBE
RBE
RBE
INTBT/INT4 Start Address
(High-Order 6 Bits)
INTBT/INT4 Start Address
(Low-Order 8 Bits)
INT0/INT1 Start Address
(High-Order 6 Bits)
INT0/INT1 Start Address
(Low-Order 8 Bits)
INTSIO Start Address
(High-Order 6 Bits)
INTSIO Start Address
(Low-Order 8 Bits)
INTT0 Start Address
(High-Order 6 Bits)
INTT0 Start Address
(Low-Order 8 Bits)
INTT1 Start Address
(High-Order 6 Bits)
INTT1 Start Address
(Low-Order 8 Bits)
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
CALL ! addr
Instruction
Subroutine
Entry Address
BR ! addr
Instruction
Branch Address
BR $ addr
Instruction Relative
Branch Address
–15 to –1,
+2 to +16
0020H
GETI Instruction Reference Table
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
Branch Destination
Address and Subroutine
Entry Address by GETI
Instruction
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
3F7FH
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC loworder 8 bits have been changed by the BR PCDE or BR PCXA instruction.
15
µPD75116H,75117H
Fig. 4-2 Data Memory Map (1/2)
(a) µPD75117H
Data Memory
General
Register Area
Memory Bank
000H
(32 × 4)
01FH
Bank 0
020H
256 × 4
0FFH
100H
Data Area
Static RAM
(768 × 4)
256 × 4
Bank 1
256 × 4
Bank 2
Stack Area
1FFH
200H
2FFH
Not On-Chip
F80H
128 × 4
Peripheral Hardware Area
FFFH
16
Bank 15
µPD75116H,75117H
Fig. 4-2 Data Memory Map (2/2)
(b) µPD75116H
Data Memory
General
Register Area
Stack Area
Memory Bank
000H
(32 × 4)
01FH
Bank 0
020H
256 × 4
0FFH
100H
Data Area
Static RAM
(768 × 4)
256 × 4
Bank 1
256 × 4
Bank 2
1FFH
200H
2FFH
Not On-Chip
F80H
128 × 4
Peripheral Hardware Area
Bank 15
FFFH
17
µPD75116H,75117H
5. PERIPHERAL HARDWARE FUNCTIONS
5.1
PORT
There are the following three digital input/output ports.
• CMOS input (PORT0, PORT1)
:
8
• CMOS input/output (PORT2 to PORT9)
: 32
• N-ch open-drain input/output (PORT12 to PORT14) : 12
Total
: 52
Table 5-1 Port Function
Port Name
Function
PORT 0
4-bit input
PORT 1
Operation/Features
Regardless of the operating mode of the shared
pin, reading or test is always possible.
Remarks
These pins are shared with SI,
SO, SCK, INT0 to INT4.
PORT 3 *1
Can be set in the input or output bit-wise.
PORT 6 *1
PORT 2 *1
PORT 4 *1
4-bit input/output
PORT 5 *1
PORT 7 *1
Can be set in the input or output mode as a 4bit unit. Ports 4 and 5, 6 and 7, and 8 and 9 are
paired and data input/output is possible as an
8-bit unit.
Port 2, PTO0, PTO1, and PCL share
the same pins.
PORT 8 *1
PORT 9 *1
PORT12 *2
4-bit input/output
PORT13 *2
(N-ch open-drain +6
V withstand voltage)
PORT14 *2
★ * 1. When VDD = 5 V, IOL = 15 mA.
★
2. When VDD = 5 V, IOL = 10 mA.
18
Can be set to input or output mode as a 4-bit
unit. Ports 12 and 13 are paired and data input/
output is possible as an 8-bit unit.
On-chip pull-up resistor specifiable bit-wise by mask option.
µPD75116H,75117H
5.2
CLOCK GENERATOR
The clock generator operation is determined by the processor clock control register (PCC).
This circuit can also change the instruction execution time.
• 0.95 µs/1.91 µs/15.3 µs (4.19 MHz operation)
Fig. 5-1 Clock Generator Block Diagram
• Basic Interval Timer (BT)
• Clock Output Circuit
• Timer/Event Counter
• Serial Interface
X1
1/8 to 1/4096
System Clock
Oscillation
Circuit
fXX or fX
Frequency Divider
1/2 1/16
X2
Frequency
Divider
Selector
Oscillation
Stop
1/4
Φ
• CPU
• Clock Output Circuit
PCC
Internal Bus
PCC0
PCC1
4
HALT *
HALT F/F
PCC2
S
PCC3
STOP *
R
PCC2,
PCC3
Clear
Q
Wait Release Signal from BT
STOP F/F
Q
S
RESET Signal (Internal Reset)
R
*
Standby Release Signal from
Interrupt Control Circuit
Instruction execution
Remarks
1.
fXX = Crystal/ceramic oscillator frequency
2.
fX = External clock frequency
3.
Φ = CPU Clock
4.
PCC : Processor clock control register
5.
One Φ clock cycle (t CY) is one machine cycle. See "AC
★
CHARACTERISTICS" in 12. "ELECTRICAL SPECIFICATIONS" for tCY.
19
µPD75116H,75117H
5.3
CLOCK OUTPUT CIRCUIT
The clock output circuit is a circuit which outputs a clock pulse from P22/PCL and is used to supply clock pulses
to remote control outputs or peripheral LSI’s.
• Clock output (PCL) : Φ , 524 kHz, 262 kHz (4.19 MHz operation)
Fig. 5-2 Configuration of Clock Output Circuit
From Clock
Generator
Φ
Output Buffer
fXX/2
3
Selector
PCL/P22
fXX/2
4
PORT2.2
CLOM3 CLOM2 CLOM1 CLOM0 CLOM
P22
Output Latch
4
Internal Bus
20
Bit 2 of PMGB
Bit Specified
in Port 2
Input/Output
Mode
µPD75116H,75117H
5.4
BASIC INTERVAL TIMER
The basic interval timer includes the following functions.
• It operates as an interval timer which generates reference time interrupts.
• It can be applied as a watchdog timer which detects when a program is out of control.
• Selects and counts wait times when the standby mode is released.
• It reads count contents.
Fig. 5-3 Basic Interval Timer Configuration
From Clock
Generator
fXX/2
fXX/2
Clear
5
7
fXX/2
Set
Basic Interval Timer
(8-Bit Frequency Divider)
MPX
fXX/2
Clear
9
BT
12
BT Interrupt
Request Flag
IRQBT
Vector
Interrupt
Request
Signal
3
BTM3
SET1*
BTM2
BTM1
BTM0
Wait Release
Signal during
Standby Release
BTM
8
4
Internal Bus
*
SET1 indicates instruction execution.
5.5 TIMER/EVENT COUNTER
The µPD75117H incorporates two internal timer/event counter channels.
Timer/event counter channel 0 and channel 1 differ only in selectable count pulse (CP) and clock supply function
to serial interface and are the same in other configurations and functions.
• Operates as a programmable interval timer.
• Outputs square waves in the desired frequency to the PTOn pin.
• Operates as an event counter.
• Use of TIn pin as an external interrupt input pin.
• Divides the TIn pin input into N divisions and outputs it to the PTOn pin (frequency divider operation).
• Supplies a serial shift clock to the serial interface circuit. (channel 0 only)
• Count status read function.
21
22
Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1)
Internal Bus
*1
SET1
8
8
8
TMn
TMODn
Modulo Register (8)
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
TOFn
8
TIn
Match
TOUT
F/F
Comparator (8)
8
Input Buffer
TOEn
TO
Enable
Flag
PORT2.n
Bit 2 of PGMB
TOn
Port 2
P2n
Input/
Output
Output
Latch
Mode
To Serial
Interface
(Channel 0 only)
TO
Selector
P2n/PTOn
Output
Buffer
Tn
TIn
From Clock
Generator
CP
INTTn
IRQTn Set
Signal

Clear
TMn1
Timer Operation Start
RESET
SET1 : Instruction execution.
TMn0
IRQTn
Clear Signal
µPD75116H,75117H
*
Edge
Detector
Count Register (8)
MPX
µPD75116H,75117H
5.6
SERIAL INTERFACE
The serial interface has the following functions.
• Clock 8-bit transmission/reception operation (simultaneous transmission/reception)
• Clock 8-bit reception operation (SO output high impedance)
• Half-duplex asynchronous transfer (software control)
• LSB-first/MSB-first switchable
These functions facilitate serial bus data communications with other computers such as µPD7500 series, 78K
series, etc., or conjunction with a peripheral device.
23
24
Fig. 5-5 Serial Interface Block Diagram
Internal Bus
8
8
8
SIO0
P03/SI
SET1 *
SIO7
SIO
SIOM
Shift Registor (8)
SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0
P02/SO
Serial Clock
Counter (3)
INTSIO
IRQSIO 
Set Signal
Overflow
Clear
IRQSIO
Clear Signal
Serial Start
P01/SCK
R
ϕ
S
fxx/2
4
fxx/2
10
MPX
TOF0
(from Timer Channel 0)
* SET1 : instruction execution
µPD75116H,75117H
Q
µPD75116H,75117H
5.7
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)
The µPD75117H is provided with 4-bit analog input pins (PTH00 to PTH03) for which the threshold voltage can
be changed. These pins have a configuration as shown in Fig. 5-6.
15.5
0.5
The threshold voltage (VREF) can be selected in 16 ways (VDD × ——— – VDD × ———) and analog signals can be
16
16
directly input.
7.5
This port can also be used as a digital signal input port by selecting VDD × ——— as VREF.
16
★
Fig. 5-6 Programmable Threshold Port Block Diagram
Input Buffer
PTH00
+
Programmable Threshold
Port Input Latch (4)
–
+
PTH01
–
+
PTH02
–
–
Operation
Stopped
PTH0
VDD
Internal Bus
+
PTH03
PTHM7
1
2R
PTHM6
R
PTHM5
R
MPX
VREF
PTHM4
8
PTHM3
PTHM2
1
2R
4
PTHM1
PTHM0
PTHM
25
µPD75116H,75117H
5.8
BIT SEQUENTIAL BUFFER ······ 16 BITS
Bit manipulation of the bit sequential buffer is the bit manipulation special data memory. Since, in particular,
the bit manipulation can easily be performed by changing sequentially address and bit specification, it is convenient
when processing data comprising a large number of bits bit-wise.
Fig. 5-7 Bit Sequential Buffer Format
Address
Bit
FC3H
3
Symbol
L Register L = F
2
1
FC2H
0
3
BSB3
2
1
FC1H
0
3
BSB2
L=CL=B
2
1
FC0H
0
3
BSB1
L=8L=7
2
L=4 L=3
INCS L
26
0
BSB0
DECS L
Remarks
1
In pmem. @L addressing, the specified bit moves according to the L register.
L=0
µPD75116H,75117H
6. INTERRUPT FUNCTION
The µPD75117H has 7 interrupt sources. Multiple interrupts with priority is are also possible.
Two test sources are also provided. The test sources are edge detection testable inputs.
Table 6-1 Interrupt Sources
Interrupt Source
INTBT (standard time interval signal from
basic interval timer)
INT4
(both rising edge and falling edge
detection)
INT0
(rising edge and falling edge
detection selection)
INT1
INTSIO (serial data transfer end signal)
Interrupt Order*1
Vector Interrupt Request
Signal
(Vector Table Address)
1
VRQ1
(0002H)
2
VRQ2
(0004H)
Internal
3
VRQ3
(0006H)
Internal/External
Internal
External
External
External
INTT0
(match signal from timer/event
counter# 0 or TI0 input edge detection)
Internal/external
4
VRQ4
(0008H)
INTT1
(match signal from timer/event
counter# 1 or TI1 input edge detection)
Internal/external
5
VRQ5
(000AH)
INT2*2 (rising edge detection)
External
INT3*2 (rising edge detection)
*
Testable input signal
(Set IRQ2 and IRQ3)
1. The interrupt order is the priority order when multiple interrupt requests are generated simultaneously.
2. INT2 and INT3 are of test sources . These are affected by interrupt enable flags in the same way as interrupt
sources, but do not generate vector interrupts.
The µPD75117H interrupt control circuit has the following functions:
• Hardware control vector interrupt function that can control interrupt acceptance by interrupt enable flag (IE×××)
and interrupt master enable flag (IME).
• Arbitrary setting of interrupt start address.
• Multiple interruption function by which priority can be specified using the interrupt priority selection register
(IPS).
• Interrupt request flag (IRQ×××) test function (interrupt generation confirmation by software possible).
• Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).
27
28
Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal Bus
2
2
IM1
IM0
INT
BT
INT4
/P00
INT0
/P10
INT1
/P11
INT2
/P12
INT3
/P13
Edge
Detection
Circuit
Edge
Detection
Circuit
Edge
Detection
Circuit
Interrupt Enable Flag (IE XXX )
(IME)
2
IPS
IST
Decoder
IRQBT
IRQ4
IRQ0
IRQ1
INTSIO
IRQSIO
INTT0
IRQT0
INTT1
IRQT1
Edge
Detection
Circuit
Edge
Detection
Circuit
4
9
Priority Control
Circuit
Vector
Table
Address
Generator
IRQ2
IRQ3
µPD75116H,75117H
Interrupt
Request
Flag
Standby Release
Signal
µPD75116H,75117H
7. STANDBY FUNCTION
To reduce the power consumption during program wait, the µPD75117H has two standby modes (STOP mode
and HALT mode).
Table 7-1 Standby Mode Setting and Operation Status
STOP Mode
Operation Status
Setting instruction
HALT Mode
STOP instruction
HALT instruction
Clock generator
System clock oscillation stopped
Only CPU clock Φ stopped
Basic interval timer
Operation stopped
Operable
(IRQBT set at reference time intervals)
Serial interface
Operation possible only when the
external SCK input and TO0 output
(when timer/event counter 0 is external
TI0 input) are selected as a serial clock
Operation possible if a clock other than Φ
is specified as a serial clock
Timer/event counter
Operable only when TIn pin input
specified as count clock
Operation possible
Clock output circuit
Operation stopped
Except CPU clock Φ, output possible.
External interrupt
Operation of INT0 to INT4 possible
CPU
Operation stopped
Release signal
Operation stopped
Interrupt request signal from operable hardware enabled by interrupt enable flag, or
RESET input
29
µPD75116H,75117H
8. RESET FUNCTION
The reset operation timing is shown in Fig. 8-1.
Fig. 8-1 Reset Operation by RESET Input
Wait
(31.3 ms/4.19 MHz)
RESET Input
Operating Mode or Standby
Mode
HALT Mode
Internal Reset Operation
The state of hardware after reset operation is as shown in Table 8-1.
30
Operating Mode
µPD75116H,75117H
Table 8-1 Status of Each Hardware after Resetting (1/2)
Hardware
RESET Input during
Operation
Low-order 6 bits of program
memory address 0000H are
set in PC13 to PC8 and the
contents of address 0001H
are set in PC7 to PC0. PC14*1
is set to 0.
Low-order 6 bits of
program memory address
0000H are set in PC13 to PC8
and the contents of address
0001H are set in PC7 to PC 0.
PC14*1 is set to 0.
Held
Undefined
Skip flag (SK0 to SK2)
0
0
Interrupt status flag (IST0, IST1)
0
0
Program counter (PC)
Carry flag (CY)
PSW
RESET Input in Standby
Mode
Bank enable flag (MBE, RBE)
Sets program memory
Sets program memory
address 000H bit 6 and bit 7 address 000H bit 6 and bit
7 to RBE and MBE,
to RBE and MBE, respecrespectively.
tively.
Stack pointer (SP)
Undefined
Undefined
Stack bank selection register (SBS) *1
Undefined
Undefined
Held *2
Undefined
General register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank selection register (MBS, RBS)
0, 0
0, 0
Undefined
Undefined
Mode register (BTM)
0
0
Counter (Tn)
0
0
FFH
FFH
0
0
TOEn, TOFn
0, 0
0, 0
Shift register (SIO)
Held
Undefined
Mode register (SIOM)
0
0
Processor clock control register (PCC)
0
0
Clock output mode register (CLOM)
0
0
Data memory (RAM)
Basic interval
timer
Timer/event
counter
(n = 0, 1)
Counter (BT)
Modulo register (TMODn)
Mode register (TMn)
Serial interface
Clock generator,
clock output
circuit
* 1. Compatible with the µPD75117H only.
2. Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
31
µPD75116H,75117H
Table 8-1 Status of Each Hardware after Resetting (2/2)
RESET Input in Standby
Mode
RESET Input during
Operation
IRQ1,IRQ2, IRQ4
Undefined
Undefined
Other than above
0
0
0
0
0
0
INT0, INT1 mode registers (IM0, IM1)
0, 0
0, 0
Output buffer
OFF
OFF
Output latch
Clear (0)
Clear (0)
0
0
Undefined
Undefined
0
0
0
0
Hardware
★
Interrupt request
flag (IRQ×××)
Interrupt function
Interrupt enable flag (IE×××)
Priority selection register (IPS)
Digital port
I/O mode register (PMGA, PMGB, PMGC)
PTH00 to PTH03 input latch
Analog port
Mode register (PTHM)
Bit sequential buffer (BSB0 to BSB3)
32
µPD75116H,75117H
9.
INSTRUCTION SET
(1) Operand identifier and description
The operand is described in the operand field of each instruction in accordance with the description for the
operand identifier of the instruction. (For details, refer to RA75X Assembler Package User’s Manual Language
Volume (EEU-730).) When there are multiple elements in the description, one of the elements is selected. Upper
case letters and symbols (+,–) are keywords and are described unchanged.
Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (For details, refer
to µPD75117H User’s Manual (IEU-799).) However, there are restrictions on the labels for which fmem and pmem
can be used.
Identifier
reg
reg1
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
rp
rp1
rp2
rp'
rp'1
XA, BC, DE, HL
BC, DE, HL
BC, DE
XA, BC, DE, HL, XA', BC', DE', HL'
BC, DE, HL, XA', BC', DE', HL'
rpa
HL, HL+, HL–, DE, DL
rpa1
DE, DL
n4
n8
4-bit immediate data or label
8-bit immediate data or label
mem
8-bit immediate data or label*
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
addr
*
Description
µPD75116H
0000H to 3F7FH immediate data or label
µPD75117H
0000H to 3FFFH immediate data or label
addr1
0000H to 5F7FH immediate data or lebel
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
IE×××
RBn
MBn
PORT 0 to PORT 9, PORT12 to PORT14
IEBT, IESIO, IET0, IET1, IE0 to IE4
RB0 to RB3
MB0, MB1, MB2, MB15
In the case of the 8-bit data processing, an even address only can be described for mem.
33
µPD75116H,75117H
(2) Operation description legend
A
: A register; 4-bit accumulator
B
: B register
34
C
D
E
H
:
:
:
:
C register
D register
E register
H register
L
X
XA
BC
:
:
:
:
L register
X register
Register pair (XA); 8-bit accumulator
Register pair (BC)
DE
HL
XA'
BC'
:
:
:
:
Register pair (DE)
Register pair (HL)
Extension register pair (XA')
Extension register pair (BC')
DE'
HL'
PC
SP
:
:
:
:
Extension register pair (DE')
Extension register pair (HL')
Program counter
Stack pointer
CY
PSW
MBE
RBE
:
:
:
:
Carry flag; bit accumulator
Program status word
Memory bank enable flag
Register bank enable flag
PORTn
IME
IPS
IE×××
:
:
:
:
Portn (n = 0 to 9, 12 to 14)
Interrupt master enable flag
Interrupt priority selection register
Interrupt enable flag
RBS
MBS
PCC
.
:
:
:
:
Register bank selection register
Memory bank selection register
Processor clock control register
Address, bit delimiter
(××)
××H
: Contents addressed by ××
: Hexadecimal data
µPD75116H,75117H
MB = MBE • MBS (MBS = 0, 1, 2, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (00H to 7FH)
MB = 15 (80H to FFH)
MBE = 0 : MB = MBS (MBS = 0, 1, 2, 15)
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
addr = 0000H to 3F7FH (µPD75116H)
0000H to 3FFFH (µPD75117H)
*7
• µPD75116H
addr = (Current PC) –15 to (Current PC) –1,
(Current PC) + 2 to (Current PC) + 16
• µPD75117H
addr1 = (Current PC) –15 to (Current PC) –1,
(Current PC) + 2 to (Current PC) + 16
*8
caddr = 0000H to 0FFFH (PC 13, 12 = 00B : µPD75116H)
→
*4
Data memory
addressing
→
*1
→
(3) Description of addressing area field symbols
= 0000H to 0FFFH (PC14, 13, 12 = 000B : µPD75117H)
= 1000H to 1FFFH (PC13, 12 = 01B : µPD75116H)
= 1000H to 1FFFH (PC14, 13, 12 = 001B : µPD75117H)
= 2000H to 2FFFH (PC14, 13, 12 = 010B : µPD75117H)
= 3000H to 3F7FH (PC 13, 12 = 11B : µPD75116H)
= 3000H to 3FFFH (PC14, 13, 12 = 011B : µPD75117H)
= 4000H to 4FFFH (PC14, 13, 12 = 100B : µPD75117H)
= 5000H to 5F7FH (PC14, 13, 12 = 101B : µPD75117H)
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
*11
addr1 = 0000H to 5F7FH ( : µPD75117H only)
Remarks
1.
2.
MB indicates the accessible memory bank.
For *2, MB = 0 without regard to MBE and MBS.
3.
4.
For *4 and *5, MB = 15 without regard to MBE and MBS.
*6 to *10 indicate the addressable area.
→
= 2000H to 2FFFH (PC13, 12 = 10B : µPD75116H)
Program memory
addressing
35
µPD75116H,75117H
(4) Explanation of machine cycle field
S shows the number of machine cycles required when skip is performed by an instruction with skip. The value
of S changes as follows:
• No skip ....................................................................................................................................................................... S = 0
• When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1
• When instruction to be skipped is 3-byte instruction .......................................................................................... S = 2
(BR !addr, BRA !addr1*, CALL !addr, CALLA !addr1* instructions)
*
This instruction is valid for the µPD75117H only.
Note
One machine cycle is required to skip a GETI instruction.
One machine cycle is equivalent to one cycle (= tCY) of the CPU clockΦ. Three times can be selected by PCC setting.
36
µPD75116H,75117H
Instruction Group
Mnemonic
MOV
Transfer
XCH
Operands
Bytes Machine
Cycles
Operation
Addressing
Area
Skip
Condition
A, #n4
1
1
A ← n4
reg1, #n4
2
2
reg1 ← n4
XA, #n8
2
2
XA ← n8
Stack A
HL, #n8
2
2
HL ← n8
Stack B
rp2, #n8
2
2
rp2 ← n8
A, @HL
1
1
A ← (HL)
*1
A, @HL+
1
2+S
A ← (HL), then L ← L + 1
*1
L=0
A, @HL-
1
2+S
A ← (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ← (rpa1)
*2
XA, @HL
2
2
XA ← (HL)
*1
@HL, A
1
1
(HL) ← A
*1
@HL, XA
2
2
(HL) ← XA
*1
A, mem
2
2
A ← (mem)
*3
XA, mem
2
2
XA ← (mem)
*3
mem, A
2
2
(mem) ← A
*3
mem, XA
2
2
(mem) ← XA
*3
A, reg
2
2
A ← reg
XA, rp'
2
2
XA ← rp'
reg1, A
2
2
reg1 ← A
rp'1, XA
2
2
rp'1 ← XA
A, @HL
1
1
A ↔ (HL)
*1
A, @HL+
1
2+S
A ↔ (HL), then L ← L + 1
*1
L=0
A, @HL-
1
2+S
A ↔ (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ↔ (rpa1)
*2
XA, @HL
2
2
XA ↔ (HL)
*1
A, mem
2
2
A ↔ (mem)
*3
XA, mem
2
2
XA ↔ (mem)
*3
A,reg1
1
1
A ↔ reg1
XA, rp'
2
2
XA ↔ rp'
XA, @PCDE
1
3
XA, @PCXA
1
3
XA, @BCDE*
1
3
XA ← (B2-0 + CDE)ROM
*11
XA, @BCXA*
1
3
XA ← (B2-0 + CXA)ROM
*11
Stack A
XA ← (PC13-8 + DE)ROM
Table reference
MOVT
XA ← (PC14-8 + DE)ROM
XA ← (PC13-8 + XA)ROM
XA ← (PC14-8 + XA)ROM
* The 3 lower bits in the B register are valid only.
Remarks Shading indicates a part compatible with the µPD75117H.
37
µPD75116H,75117H
Instruction
Group
Mnemonic
Operands
CY, fmem.bit
CY, pmem.@L
Bit
transfer
MOV1
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
ADDS
ADDC
SUBS
Operations
SUBC
AND
OR
Bytes Machine
Cycles
2
2
2
2
2
2
Addressing
Area
2
CY ← (fmem.bit)
*4
2
CY ← (pmem7 – 2 + L3 – 2.bit(L1–0))
*5
2
CY ← (H + mem3 – 0.bit)
*1
2
(fmem.bit) ← CY
*4
2
(pmem7 – 2 + L3 – 2.bit(L1–0)) ← CY
*5
2
(H + mem3 – 0.bit) ← CY
*1
Skip
Condition
A, #n4
1
1+S
A ← A + n4
XA, #n8
2
2+S
XA ← XA + n8
A, @HL
1
1+S
A ← A + (HL)
XA, rp'
2
2+S
XA ← XA + rp'
carry
rp'1, XA
2
2+S
rp'1 ← rp'1 + XA
carry
A, @HL
1
1
A, CY ← A + (HL) + CY
*1
carry
carry
carry
*1
XA, rp'
2
2
XA, CY ← XA + rp' + CY
rp'1, XA
2
2
rp'1, CY ← rp'1 + XA + CY
A, @HL
1
1+S
A ← A – (HL)
XA, rp'
2
2+S
XA ← XA – rp'
borrow
rp'1, XA
2
2+S
rp'1, CY ← rp'1 – XA – CY
borrow
A, @HL
1
1
A, CY ← A – (HL) – CY
XA, rp'
2
2
XA, CY ← XA – rp' – CY
rp'1, XA
2
2
rp'1, CY ← rp'1 – XA – CY
A, #n4
2
2
A ← A ∧ n4
A, @HL
1
1
A ← A ∧ (HL)
XA, rp'
2
2
XA ← XA ∧ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∧ XA
A, #n4
2
2
A ← A ∨ n4
A, @HL
1
1
A ← A ∨ (HL)
XA, rp'
2
2
XA ← XA ∨ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∨ XA
A, #n4
2
2
A ← A ∨ n4
A, @HL
1
1
A ← A ∨ (HL)
XA, rp'
2
2
XA ← XA ∨ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∨ XA
XOR
38
Operation
*1
*1
*1
*1
*1
borrow
µPD75116H,75117H
Instruction
Group
Mnemonic
Operands
Bytes Machine
Cycles
Operation
Addressing
Area
Skip Condition
A
1
1
CY ← A 0, A3 ← CY, An–1 ← An
A
2
2
A←A
reg
1
1+S
reg ← reg + 1
reg = 0
rp1
1
1+S
rp1 ← rp1 + 1
rp1 = 00H
@HL
2
2+S
(HL) ← (HL) + 1
*1
(HL) = 0
mem
2
2+S
(mem) ← (mem) + 1
*3
(mem) = 0
reg
1
1+S
reg ← reg – 1
reg = FH
rp'
2
2+S
rp' ←rp' – 1
rp' = FFH
reg, #n4
2
2+S
Skip if reg = n4
reg = n4
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2+S
Skip if A = reg
A = reg
XA, rp'
2
2+S
Skip if XA = rp'
XA = rp'
SET1
CY
1
1
CY ← 1
Carry flag CLR1
manipulation
SKT
CY
1
1
CY ← 0
CY
1
1+S
NOT1
CY
1
1
CY ← CY
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
pmem.@L
2
2
(pmem7–2 + L3–2.bit (L1–0)) ← 1
*5
@H + mem.bit
2
2
(H + mem3–0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
pmem.@L
2
2
(pmem7–2 + L3–2.bit (L1–0)) ← 0
*5
@H + mem.bit
2
2
(H + mem3–0.bit) ← 0
*1
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2 + L 3–2.bit (L1–0)) = 1
*5
(pmem.@L) = 1
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 1
*1
(@H + mem.bit) = 1
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem7–2 + L 3–2.bit (L1–0)) = 0
*5
(pmem.@L) = 0
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 0
*1
(@H + mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2 + L 3–2.bit (L1–0))
= 1 and clear
*5
(pmem.@L) = 1
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit)
= 1 and clear
*1
(@H + mem.bit) = 1
Accumulator RORC
manipulation
NOT
INCS
Increment
/decrement
DECS
Comparison SKE
SET1
CLR1
Memory bit
manipulation SKT
CY = 1
Skip if CY = 1
SKF
SKTCLR
39
µPD75116H,75117H
Instruction
Group
Mnemonic
Operands
CY, fmem.bit
AND1
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
Memory bit
manipulation
OR1
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
XOR1
CY, pmem.@L
CY, @H + mem.bit
addr *1
BR
Bytes Machine
Cycles
2
2
2
2
2
2
2
2
2
—
Operation
Skip
Addressing
Condition
Area
2
CY ← CY ∧ (fmem.bit)
*4
2
CY ← CY ∧ (pmem7–2 + L3–2.bit (L1–0))
*5
2
CY ← CY ∧ (H + mem3–0.bit)
*1
2
CY ← CY ∨ (fmem.bit)
*4
2
CY ← CY ∨ (pmem7–2 + L3–2.bit (L1–0))
*5
2
CY ← CY ∨ (H + mem3–0.bit)
*1
2
CY ← CY ∨ (fmem.bit)
*4
2
CY ← CY ∨ (pmem7–2 + L3–2.bit (L1–0))
*5
2
CY ← CY ∨ (H + mem3–0.bit)
*1
—
PC13–0 ← addr
(The assembler selects the optimum instruction from among the BR !addr, BRCB
!caddr, and BR $addr instructions.)
*6
PC14–0 ← addr1
(The assembler selects the optimum instruction from among the BR !addr, BRA
!addr1, BRCB !caddr, and BR $addr1 instructions.)
*11
addr1
—
—
!addr
3
3
$addr
1
2
PC13-0 ← addr
$addr1
1
2
PC14-0 ← addr1
PCDE
2
3
2
3
PC13-0 ← addr
Branch
*6
PC14-0, PC13-0 ← addr
*7
PC13-0 ← PC 13-8 + DE
PCXA
PC14-0 ← PC 14-8 + DE
PC13-0 ← PC 13-8 + XA
PC14-0 ← PC 14-8 + XA
BCDE *2
2
3
PC14-0 ← B 2-0 + CDE
*11
BCXA *2
2
3
PC14-0 ← B 2-0 + CXA
*11
BRA
!addr1
3
3
PC14-0 ← !addr1
*11
BRCB
!caddr
2
2
PC13-0 ← PC 13,12 + caddr 11-0
PC14-0 ← PC 14,13,12 + caddr11-0
*8
(SP – 4) (SP – 1) (SP – 2) ← PC11-0
3
Subroutine
stack
control
(SP – 3) ← MBE, RBE, PC13, PC12
PC13-0 ← addr, SP ← SP–4
CALL
!addr
3
(SP – 2) ← ×, ×, MBE, RBE
4
(SP – 6) (SP – 3) (SP – 4) ← PC11-0
(SP – 5) ← 0, PC14, PC13, PC12
PC14 ← 0, PC13-0 ← addr, SP ← SP–6
*
1. µPD75116H only.
2. The 3 lower bits in the B register are valid only.
Remarks
40
Shading indicates a part compatible with the µPD75117H.
*6
µPD75116H,75117H
Instruction
Group
Mnemonic
Operands Bytes Machine
Cycles
Operation
Addressing
Skip Condition
Area
(SP – 2) ← ×, ×, MBE, RBE
CALLA
!addr1
3
3
(SP – 6) (SP – 3) (SP – 4) ← PC11-0
(SP – 5) ← 0, PC14, PC13, PC12
*11
PC14–0 ← addr1, SP ← SP–6
2
CALLF
!faddr
2
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, RBE, PC13, PC12
PC13–0 ← 000 + faddr, SP ← SP – 4
(SP – 2) ← ×, ×, MBE, RBE
3
*9
(SP – 6) (SP – 3) (SP – 4) ← PC11–0
(SP – 5) ← 0, PC14, PC13, PC12
PC14–0 ← 0000 + faddr, SP ← SP – 6
MBE, RBE, PC13, PC12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4
1
RET
3
Subroutine
stack
control
PC11–0 ← (SP) (SP + 3) (SP + 2)
×, PC14, PC13, PC12 ← (SP + 1)
×, ×, MBE, RBE ← (SP + 4)
SP ← SP +6
MBE, RBE, PC13, PC12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4, then skip unconditionally
RETS
1
3+S
PC11–0 ← (SP) (SP + 3) (SP + 2)
×, PC14, PC13, PC12 ← (SP + 1)
×, ×, MBE, RBE ← (SP + 4)
SP ← SP +6 then skip unconditionally
Unconditional
PC13, PC12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
PSW ← (SP + 4) (SP + 5), SP ← SP +6
1
3
PC11–0 ← (SP) (SP + 3) (SP + 2)
×, PC14, PC13, PC12 ← (SP + 1)
PSW ← (SP + 4) (SP + 5), SP ← SP +6
rp
1
1
(SP – 1) (SP – 2) ← rp, SP ← SP – 2
BS
2
2
(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2
rp
1
1
rp ← (SP + 1) (SP), SP ← SP + 2
BS
2
2
MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2
2
2
IME (IPS.3) ← 1
2
2
IE××× ← 1
2
2
IME (IPS.3) ← 0
2
2
IE××× ← 0
RETI
PUSH
POP
EI
IE×××
Interrupt
control
DI
IE×××
Remarks
Shading indicates a part compatible with the µPD75117H.
41
µPD75116H,75117H
Instruction
Group
Mnemonic
Bytes Machine
Cycles
Operation
A, PORTn
2
2
A← PORTn
XA, PORTn
2
2
XA ← PORTn + 1, PORTn (n = 4, 6, 8, 12)
PORTn, A
2
2
PORTn ← A
PORTn, XA
2
2
PORTn + 1, PORTn ← XA (n = 4, 6, 8, 12)
HALT
2
2
Set HALT Mode (PCC.2 ← 1)
STOP
2
2
Set STOP Mode (PCC.3 ← 1)
NOP
1
1
No Operation
RBn
2
2
RBS ← n
MBn
2
2
MBS ← n (n = 0, 1, 2, 15)
IN
*1
Input/output
*1
OUT
CPU control
Operands
SELL
Addressing
Skip Condition
Area
(n = 0 to 9, 12 to 14)
(n = 2 to 9, 12 to 14)
(n = 0 to 3)
• TBR Instruction
PC13–0 ← (taddr)5–0 ← (taddr + 1)
PC14← 0
-----------------------------------------------------------------------• TCALL Instruction
3
1
Special
*2
GETI
taddr
(SP – 5) (SP – 6) (SP – 3)(SP – 4) ← PC14–0
(SP – 2) ← (×, ×, MBE, RBE)
PC13–0 ← (taddr)5–0 ← (taddr + 1)
SP ← SP – 6 PC14← 0
-----------------------------------------------------------------------• Other than TBR and TCALL Instruction
Execution of an instruction addressed
3
at (taddr) and (taddr + 1)
4
• TBR Instruction
PC13–0 ← (taddr)5–0 ← (taddr + 1)
PC14← 0
-----------------------------------------------------------------------• TCALL Instruction
(SP – 5) (SP – 6) (SP – 3)(SP – 4) ← ×, PC 14–0
(SP – 2) ← ×, ×, MBE, RBE
4
PC13–0 ← (taddr)5–0 ← (taddr + 1)
SP ← SP – 6, PC 14← 0
-----------------------------------------------------------------------• Other than TBR and TCALL Instruction
Execution of an instruction addressed
3
at (taddr) and (taddr + 1)
-----------------------*10
-----------------------Conforms to
referenced
instruction.
3
1
*
*10
----------------------Conforms to
referenced
instruction.
1. When executing the IN/OUT instruction, <MBE = 0> or <MBE = 1, MBS = 15> must be set.
2. The TBR or TCALL instruction is a GETI instruction table definition assembler pseudo-instruction.
Remarks
42
------------------------
Shading indicates a part compatible with the µPD75117H.
Compression
IDC
MSK
Modem
Extension
MPX
Transmitter/
Receiver
Prescaler
Speaker
VCO
Speaker
Amp
PLL
TCXO
MPX
10. APPLICATION EXAMPLE
Amp
10.1 CORDLESS TELEPHONE (SUBSET)
Power Amp
Prescaler
LED Display
µ PD7511H
VCO
PLL
Key Matrix
SIO
Radio Wave
Detection
LCD
Controller/
Driver
LED
Display
µ PD7228
Console
Extra-Area
Detection
ID ROM
µ PD6252
Detection
2SC4226
3SK177
Amp
2SC2757
2SC4182
Legend
43
IDC
:
Immediate Deviation Controller,
ID ROM
:
ID (Identification) Code ROM, LCD
:
Liquid Crystal Display
LED
:
Light Emitting Diode,
MPX
:
Multiplexer
MSK
:
Minimum Shift Keying
PLL
:
Phase Locked Loop,
SIO
:
Serial Data Input/Output
TCXO
:
Temperature Compensation Crystal Oscillator
VCO
:
Voltage Control Oscillator
µPD75116H,75117H
Filter
Mixer
µPD75116H,75117H
10.2 DISPLAY PAGER
µ PD75117H
Filter
INT
RAM
Code ROM
Switch
Piezoelectric
Buzzer
TO
High-Current
Output
LED Display
Comparator
Input
Battery Check
SIO
LCD Controller/Driver
µ PD7228/7229
44
LCD Display
µPD75116H,75117H
11. MASK OPTION SELECTION
The µPD75117H has the following mask option.
Pin Function
P12 to P14
Mask Option
• Pull-up resistor (can be specified bit-wise.)
• No pull-up resistor (can be specified bit-wise.)
45
µPD75116H,75117H
★
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
PARAMETER
Supply voltage
SYMBOL
TEST CONDITIONS
RATING
UNIT
–0.3 to +7.0
V
–0.3 to VDD +0.3
V
–0.3 to VDD +0.3
V
–0.3 to +7.3
V
–0.3 to VDD +0.3
V
One pin
–15
mA
All pins
–30
mA
Peak value
30
mA
Effective value
15
mA
100
mA
60
mA
100
mA
60
mA
VDD
VI1
Except ports 12, 13 and 14
Input voltage
Internal pull-up resistor
VI2*1
Ports 12 to 14
Open–drain
Output voltage
VO
Output current
high
IOH
One pin
Peak value
Output current low
IOL*2
Total of ports 0, 2, 12 to 14
Effective value
Peak value
Total of ports 3 to 9
Effective value
*
Operating
temperature
Topt
–40 to +60
°C
Storage
temperature
Tstg
–65 to +150
°C
1. When a voltage exceeding 6V is applied to ports 12, 13 and 14, the power supply impedance (pull-up resistor)
should be 50KΩ or more.
2. Effective value should be calculated: [Effective value] = [Peak value] × √duty
Note
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even
momentarily.
The absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions which ensure that the absolute
maximum ratings are not exceeded.
OPERATING VOLTAGE RANGE
PARAMETER
46
TEST CONDITIONS
MIN.
MAX.
UNIT
CPU
– 40
+ 60
°C
Programmable threshold port
(comparator input)
– 10
+ 60
°C
Other hardware
– 40
+ 60
°C
µPD75116H,75117H
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
15
pF
15
pF
15
pF
MAX.
UNIT
5.0 *4
MHz
4
ms
5.0 *4
MHz
10
ms
30
ms
2.0
5.0 *4
MHz
100
250
ns
CIN
Input capacitance
COUT
Output capacitance
f = 1 MHz
Unmeasured pins returned to 0 V
Input/output
capacitance
CIO
OSCILLATION CIRCUIT CHARACTERISTICS (Ta = –40 to +60 °C, VDD = 1.8 to 5.5 V)
RESONATOR
RECOMMENDED
CONSTANT
X1
*1
*2
Oscillator
frequency (fXX)
X2
Ceramic
resonator
C1
*3
Oscillation
stabilization time
C2
X1
*1
Crystal
resonator
*5
X1
Oscillation
*3
stabilization time
C2
External
clock
2.0
VDD = 4.5 to 5.5 V
4.19
VDD = 2.7 to 5.5 V
X1 input
high-/low-level width
(tXH, tXL)
µPD74HCU04
*
TYP.
After VDD reaches
MIN. of oscillation
voltage range
X1 input
*2
frequency (fX)
X2
MIN.
2.0
*2
Oscillator
frequency (fXX)
X2
C1
TEST
CONDITIONS
PARAMETER
1. When using in VDD < 2.7 V, the X2 pin oscillation waveform duty should be set within the range between 40%
and 60%.
Duty =
tXXL (or tXXH)
tXXL + tXXH
× 100
VDD
X2 Oscillation
Waveform
1 VDD
2
VSS
tXXL
tXXH
2. Oscillator frequency and X1 input frequency indicate oscillation circuit characteristics only. See AC
CHARACTERISTICS for instruction execution time.
3. The oscillation stabilization time is the time required for oscillation to stabilize after VDD reaches MIN. of
oscillation voltage range or the STOP mode is released.
4. When the oscillator frequency is 4.19 MHz < fXX ≤ 5.0 MHz, PCC = 0011 should not be selected as the instruction
execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 µs and the rated MIN. value
of 0.95 µs is not observed.
5. The external clock cannot be used in VDD < 2.7 V.
47
µPD75116H,75117H
Note
When the clock oscillator is used, the following should be noted concerning wiring in the area in the figure
enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
• The wiring should be kept as short as possible.
• No other signal lines should be crossed.
• Keep away from lines carrying a high fluctuating current.
• The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect
to a ground pattern carrying a high current.
• A signal should be not taken from the oscillator.
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
RECOMMENDED CERAMIC RESONATOR (Ta = –40 to +60 °C)
MANUFACTURER
PRODUCT NAME
FREQUENCY
(MHz)
EXTERNAL CAPACITANCE (pF)
C1
C2
47
47
33
33
Iincorporated
Iincorporated
33
33
Iincorporated
Iincorporated
33
33
Iincorporated
Iincorporated
OSCILLATION VOLTAGE RANGE [V]
MIN.
MAX.
1.8
5.5
KBR–2.0MS
PBRC 2.00A
2.00
KBR–4.0MSA
PBRC 4.00A
KBR–4.0MKS
4.00
KBR–4.0MWS
Kyocera
KBR–4.19MSA
PBRC 4.19A
KBR–4.19MKS
4.19
KBR–4.19MWS
KBR–5.0MSA
PBRC 5.00A
KBR–5.0MKS
KBR–5.0MWS
48
5.00
µPD75116H,75117H
DC CHARACTERISTICS (Ta = –40 to +60 °C, VDD = 1.8 to 5.5 V)
PARAMETER
SYMBOL
VIH1
VIH2
Input voltage high
VIH3
VIH4
VIL1
Input voltage low
VIL2
VIL3
TEST CONDITIONS
Other than below
VOH
IOH = –100 µA
Ports 0, 2,
4 to 8
Output voltage low
VOL
Ports 3, 9
Ports 12 to
14
ILIH1
Input leakage
current high
ILIH2
ILIH3
ILIL1
VDD = 1.8 to 2.7 V
0.8 V DD
VDD
V
0.8 V DD
VDD
V
VDD = 2.7 to 5.5 V
0.7 V DD
VDD
V
VDD = 1.8 to 2.7 V
0.8 V DD
VDD
V
VDD = 2.7 to 5.5 V
0.7 V DD
6
V
VDD = 1.8 to 5.5 V
0.8 V DD
6
V
VDD = 2.7 to 5.5 V
VDD – 0.5
VDD
V
VDD = 1.8 to 2.7 V
VDD – 0.3
VDD
V
VDD = 2.7 to 5.5 V
0
0.3 VDD
V
VDD = 1.8 to 5.5 V
0
0.2 VDD
V
0
0.2 VDD
V
0
0.4
V
VDD = 1.8 to 2.7 V
0
0.25
V
VDD = 4.5 to 5.5 V
VDD – 1.0
V
VDD = 2.7 to 5.5 V
VDD – 0.8
V
VDD = 2.7 to 5.5 V
VDD – 0.5
V
VDD = 1.8 to 2.7 V
VDD – 0.2
V
VDD = 2.7 to 5.5 V
IOH = –1 mA
Output voltage high
V
Ports 0,1,TI0, 1, RESET
X1, X2
VIN = VDD
VIV = 6 V
UNIT
VDD
N-ch open–
drain
Other than below
MAX.
0.7 V DD
Internal pull-up
resistor
X1, X2
TYP.
VDD = 2.7 to 5.5 V
Ports 0,1,TI0, 1, RESET
Ports
12 to 14
MIN.
2.0
V
VDD = 2.7 to 5.5 V
0.4
V
IOL = 400 µA
VDD = 2.7 to 5.5 V
0.5
V
IOL = 100 µA
VDD = 1.8 to 5.5 V
0.3
V
IOL = 15 mA
VDD = 4.5 to 5.5 V
0.35
2.0
V
IOL = 10 mA
VDD = 2.7 to 5.5 V
0.3
1.0
V
IOL = 1.6 mA
VDD = 2.7 to 5.5 V
0.4
V
IOL = 400 µA
VDD = 2.7 to 5.5 V
0.5
V
IOL = 100 µA
VDD = 1.8 to 5.5 V
0.3
V
IOL = 10 mA
VDD = 4.5 to 5.5 V
2.0
V
IOL = 1.6 mA
VDD = 2.7 to 5.5 V
0.4
V
IOL = 400 µA
VDD = 2.7 to 5.5 V
0.5
V
IOL = 100 µA
VDD = 1.8 to 5.5 V
0.3
V
Other than below
3
µA
X1, X2
20
µA
Ports 12 to 14 (open-drain)
15
µA
Other than below
–3
µA
–20
µA
IOL = 15 mA
VDD = 4.5 to 5.5 V
IOL = 1.6 mA
0.35
0.35
Input leakage
current low
ILIL2
Output leakage
current high
VOUT = VDD
Other than below
3
µA
ILOH2
VOUT = 6 V
Ports 12 to 14 (open-drain)
15
µA
Output leakage
current low
ILOL
VOUT = 0 V
–3
µA
Internal pull-up
resistor
(mask option)
RL
Ports 12 to 14
60
kΩ
ILOH1
VIN = 0 V
X1, X2
10
35
49
µPD75116H,75117H
DC CHARACTERISTICS (Ta = –40 to +60 °C, VDD = 1.8 to 5.5 V)
PARAMETER
SYMBOL
TEST CONDITIONS
IDD1
4.19 MHz
Crystal oscillation
C1 = C2 = 22 pF
Supply current*1
IDD3
TYP.
MAX.
UNIT
VDD = 5 V ±10 % *2
3.0
9.0
mA
VDD = 3 V ±10 % *2
1.6
4.8
mA
VDD = 2 V ±10 % *3
0.6
1.8
mA
VDD = 5 V ±10 %
0.7
2.1
mA
VDD = 3 V ±10 %
280
860
µA
VDD = 2 V ±10 %
120
360
µA
VDD = 5 V ±10 %
0.2
50
µA
VDD = 3 V ±10 %
0.1
20
µA
VDD = 2 V ±10 %
0.05
10
µA
HALT
mode
IDD2
STOP mode
MIN.
* 1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. When the processor clock control register (PCC) is set to 0011 for operation in the high-speed mode.
3. When the PCC register is set to 0010 for operation in the low-speed mode.
COMPARATOR CHARACTERISTICS (Ta = –10 to +60 °C*, VDD = 1.8 to 5.5 V)
PARAMETER
SYMBOL
Compare accuracy
VACOMP
Threshold voltage
VTH
PTH input voltage
VIPTH
Comparator circuit
current consumption
*
50
TEST CONDITIONS
VDD = 5.0 V
PTHM7 set to "1"
VDD = 3.0 V
VDD = 2.0 V
MIN.
TYP.
MAX.
UNIT
±100
mV
0
VDD
V
0
VDD
V
0.7
0.3
0.1
mA
mA
mA
The comparator cannot operate in the range of Ta = –40 to –10 °C. It must be used within the range of Ta =
–10 to +60 °C.
µPD75116H,75117H
AC CHARACTERISTICS (Ta = –40 to +60 °C, VDD = 1.8 to 5.5 V)
PARAMETER
SYMBOL
CPU clock cycle time*
(Minimum instruction
execution time = 1
machine cycle)
tCY
TI0, TI1 input
frequency
fTI
TI0, TI1 input high/
low-level width
TEST CONDITIONS
MIN.
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
tTIH,
TYP.
MAX.
UNIT
0.95
16
µs
1.91
16
µs
0
1
MHz
0
275
kHz
0.48
µs
1.8
µs
Input
0.8
µs
Output
0.95
µs
Input
3.2
µs
Output
3.8
µs
Input
0.4
µs
tKCY/2 – 50
ns
1.6
µs
tKCY/2 – 150
ns
VDD = 2.7 to 5.5 V
tTIL
V DD = 4.5 to 5.5 V
SCK cycle time
tKCY
VDD = 4.5 to 5.5 V
SCK high/low-level
width
tKH,
Output
tKL
Input
Output
SI setup time
(to SCK↑)
tSIK
100
ns
SI hold time
(from SCK↑)
tKSI
400
ns
SO output delay
time from SCK↓
tKSO
INT0 to INT4
high/low-level width
tINTH,
tINTL
5
µs
RESET low-level
width
tRSL
5
µs
VDD = 4.5 to 5.5 V
0
300
ns
0
1000
ns
51
µPD75116H,75117H
*
The CPU clock (Φ) cycle time is determined by the
oscillator frequency of the connected resonator
and the setting of the processor clock control
tCY vs. VDD
100
register (PCC). The graph on the right shows the
characteristic for cycle time tCY supply current VDD
during system clock operation.
Cycle Time tCY [ µ s]
10
Operating
Guarantee
Range
1.0
0.1
0
1
2
3
4
5
Supply Voltage VDD [V]
AC Timing Test Point (Except ports 0, 1, TI0, TI1, X1, X2, RESET)
(1)
VDD = 2.7 to 5.5 V
0.7 VDD
Test Points
0.3 VDD
(2)
0.3 VDD
VDD = 1.8 to 2.7 V
0.8 VDD
0.2 VDD
52
0.7 VDD
Test Points
0.8 VDD
0.2 VDD
6
7
µPD75116H,75117H
Clock Timing
(1)
VDD = 2.7 to 5.5 V
1/fX
tXL
tXH
VDD – 0.5 V
0.4 V
X1 Input
(2)
VDD = 1.8 to 2.7 V
1/fX
tXL
tXH
VDD – 0.3 V
0.25 V
X1 Input
TI0,TI1 Input Timing
1/fTI
tTIL
TI0, TI1
tTIH
0.8 VDD
0.2 VDD
53
µPD75116H,75117H
Serial Transfer Timing
tKCY
tKH
tKL
0.8 VDD
0.2 VDD
SCK
tSIK
tKSI
0.8 VDD
Input Data
SI
0.2 VDD
tKSO
SO
Output Data
Interrupt Input Timing
tINTL
tINTH
0.8 VDD
INT0–INT4
0.2 VDD
RESET Input Timing
tRSL
RESET
54
0.2 VDD
µPD75116H,75117H
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +60 °C)
PARAMETER
*
SYMBOL
Data retention supply voltage
VDDDR
Data retention supply current*1
IDDDR
Release signal set time
tSREL
Oscillation stabilization wait
time*2
tWAIT
TEST CONDITIONS
MIN.
TYP.
1.8
VDDDR = 2.0 V
0.05
MAX.
UNIT
5.5
V
10
µA
µs
0
Release by RESET
Release by interrupt request
217/fXX
ms
*3
ms
1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. The oscillation stabilization wait time is the time during which CPU operation is stopped to prevent unstable
operation when oscillation is started.
3. Depends on the basic interval timer mode register (BTM) setting (see table below).
BTM3
BTM2
BTM1
BTM0
WAIT TIME
(Figures in parentheses are for operation at fXX = 4.19 MHz)
—
0
0
0
220/f XX (approx. 250 ms)
—
0
1
1
217/fXX (approx. 31.3 ms)
—
1
0
1
215/fXX (approx. 7.82 ms)
—
1
1
1
213/fXX (approx. 1.95 ms)
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
55
µPD75116H,75117H
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
56
µPD75116H,75117H
13. PACKAGE INFORMATION
64-PIN PLASTIC QFP ( 14)
64 PIN PLASTIC QFP ( 14)
A
B
48
49
33
32
F
Q
5°±5°
S
C
D
detail of lead end
64
1
G
17
16
H
I M
J
M
P
K
N
L
P64GC-80-AB8-3
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
17.6 ± 0.4
0.693 ± 0.016
B
14.0 ± 0.2
0.551 +0.009
–0.008
C
14.0 ± 0.2
0.551 +0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
1.0
0.039
H
0.35 ± 0.10
0.014 +0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071 ± 0.008
L
0.8 ± 0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.55
0.100
Q
0.1 ± 0.1
0.004 ± 0.004
S
2.85 MAX.
0.112 MAX.
57
µPD75116H,75117H
★
64-PIN PLASTIC QFP ( 12)
64 PIN PLASTIC QFP ( 12)
A
B
48
49
33
32
Q
5°±5°
D
C
S
detail of lead end
F
64
17
16
1
H
I M
J
P
G
M
K
N
L
P64GK-65-8A8
NOTE
Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
58
ITEM
MILLIMETERS
INCHES
A
14.8 ± 0.4
0.583 ± 0.016
B
12.0 ± 0.2
0.472+0.009
–0.008
C
12.0 ± 0.2
0.472+0.009
–0.008
D
14.8 ± 0.4
0.583 ± 0.016
F
1.125
0.044
G
1.125
0.044
H
0.30 ± 0.10
0.012+0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.4 ± 0.2
0.055 ± 0.008
L
0.6 ± 0.2
0.024+0.008
–0.009
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.10
0.004
P
1.4
0.055
Q
0.1 ± 0.1
0.004 ± 0.004
S
1.7 MAX.
0.067 MAX.
µPD75116H,75117H
★
14. RECOMMENDED SOLDERING CONDITIONS
The µPD75117H should be soldered and mounted under the conditions recommended in the table below.
For details of recommended conditions, refer to the information document "Semiconductor Device Mount
Technology Manual" (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our sales personnel.
Table 14-1 Surface Mount Type Soldering Conditions
(1)
µ PD75117HGC: 64-Pin Plastic QFP ( 14 mm)
Soldering Method
Recommended
Condition Symbol
Package peak temperature : 230 °C, Duration : 30 sec. max. (at 210 °C or
avove), Number of times : twice
<Points to note>
Flux washing by the water after the first reflow should be avoided.
IR30-00-2
VPS
Package peak temperature : 215 °C, Duration : 40 sec. max. (at 200 °C or
above), Number of times : twice
<Points to note>
Flux washing by the water after the first reflow should be avoided.
VP15-00-2
Wave soldering
Solder bath temperature : 260 °C max., Duration : 10 sec. max., Number of
times : once, Preheating temperature : 120 °C max. (package surface
temperature)
WX60-00-1
Pin part heating
Pin part temperature : 300 °C max., Duration : 3 sec. max. (per device side)
Infrared reflow
(2)
—
µ PD75117GK: 64-Pin Plastic QFP ( 12 mm)
Soldering Method
*
Soldering Conditions
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature : 230 °C, Duration : 30 sec. max. (at 210 °C or
avove), Number of times : twice, Time limit: 7 days* (thereafter 10 hours
prebaking at 125 ˚C required)
<Points to note>
Flux washing by the water after the first reflow should be avoided.
IR35-107-2
VPS
Package peak temperature : 215 °C, Duration : 40 sec. max. (at 200 °C or
above), Number of times : twice, Time limit: 7 days* (thereafter 10 hours
prebaking at 125 ˚C required)
<Points to note>
Flux washing by the water after the first reflow should be avoided.
VP15-107-2
Pin part heating
Pin part temperature : 300 °C max., Duration : 3 sec. max. (per device side)
—
For the storage period after dry-pack decupsulation storage conditions are max. 25 ˚C, 65 % RH.
Note
Use of more than one soldering method should be avoided (except in the case of pin part heating).
59
µPD75116H,75117H
★
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG µPD751×× SERIES PRODUCTS
Product Name
Item
ROM (byte)
RAM (× 4 bits)
µPD75104/106/108/112/116
µPD75104A/108A
µPD75108F/112F/116F
4K/6K/8K/12K/16K
(Mask ROM)
4K/8K
(Mask ROM)
8K/12K/16K
(Mask ROM)
320/320/512/512/512
320/512
Instruction set
75X High-End
Total
58
CMOS input
CMOS
input/output
10
10 (Pull-up resistor mask option : 4)
32 (LED direct drive capability
*2)
I/O N-ch open-drain
port input/output
512
10
32 (Pull-up resistor mask option : 24, 32 (LED direct drive capability
*2)
LED direct drive capability)
12 (LED direct drive capability *2)
+12 V
Withstand voltage
Pull-up resistor
+10 V
Can be incorporated by mask option
4 (4-bit precision)
Analog input
Power-on reset circuit
On-chip (Mask option)
None
Power-on flag
Operating voltage
Operating temperature
range
Minimum instruction
execution time
Package
*
60
2.7 to 6.0 V
2.7 to 5.0 V (Ta = –40 to +50 °C)
2.8 to 5.0 V
–40 to +85 °C
–40 to +60 °C
0.95 µs (operating at 4.5 to 6.0 V)
3.8 µs (operating at 2.7 V)
0.95 µs (operating at 4.5 to 5.0 V)
1.91 µs (operating at 2.7V)
• 64-pin plastic shrink DIP
(750 mil)
• 64-pin plastic QFP
(14 × 20 mm)
• 64-pin plastic QFP ( 14 mm)
(Resin thick 2.55 mm)
• 64-pin plastic QFP ( 14 mm)
(Resin thick 1.5 mm)
• 64-pin plastic QFP
(14 × 20 mm)
1. 75X High-End can also be used by means of the 16K-byte mode/24K-byte mode switching function.
2. For details, refer to the electrical specifications in each data sheet.
µPD75116H,75117H
µPD75116H/117H
16K/24K
(Mask ROM)
µPD75P108B
µPD75P116
8K
(One-time PROM, EPROM)
8K
(One-time PROM)
µPD75P117H
24K
(One-time PROM)
768
512
768
75X High-End/Extended
High-End
75X High-End
75X Extended
High-End*1
58
10
32 (LED direct drive capability *2)
12 (LED direct drive capability *2)
+12 V
+6 V
Can be incorporated by mask
option
+6 V
None
4 (4-bit precision)
None
1.8 to 5.5 V
–40 to +60 °C
0.95 µs (operating at 2.7 V)
1.91 µs (operating at 1.8 V)
• 64-pin plastic QFP
( 12 mm)
• 64-pin plastic QFP
( 14 mm)
(Resin thick 2.55 mm)
5 V ±10 %
2.7 to 6.0 V
–40 to +85 °C
1.8 to 5.5 V
–40 to +60 °C
0.95 µs (operating at 4.5 to 6.0 V)
3.8 µs (operating at 2.7 V)
0.95 µs
(operating at 4.75 to 5.5 V)
0.95 µs (operating at 2.7 V)
1.91 µs (operating at 1.8 V)
• 64-pin plastic shrink DIP
(750 mil)
• 64-pin ceramic shrink DIP
(750 mil)
• 64-pin plastic QFP
(14 × 20 mm)
• 64-pin plastic shrink DIP
(750 mil)
• 64-pin plastic QFP
(14 × 20 mm)
• 64-pin plastic QFP
( 12 mm)
• 64-pin plastic QFP
( 14 mm)
(Resin thick 2.55 mm)
61
µPD75116H,75117H
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD75116H/75117H.
IE-75000-R*1
IE-75001-R
75X series in-circuit emulator
IE-75000-R-EM*2
Emulation board for the IE-75000-R or IE-75001-R
EP-75108AGC-R
Emulation probe for the µPD75116HGC/75117HGC. A 64-pin conversion socket (EV9200G-64) is also provided.
EV-9200G-64
Hardware
EP-75117GK-R
EV-9500G-64
Emulation probe for the µPD75116HGK/75117HGK. A 64-pin conversion socket (EV9500G-64) is also provided.
PG-1500
PROM programmer
PA-75P117GC
PROM programmer adapter for the µPD75P117HGC, connected to the PG-1500.
PA-75P117GK
PROM programmer adapter for the µPD75P117HGK, connected to the PG-1500.
IE control program
Software
PG-1500 controller
RA75X relocatable
assembler
*
62
Host machines
• PC-9800 series (MS-DOS™ Ver. 3.30 to Ver. 5.00A*3)
• IBM PC/AT™ (PC DOS™ Ver.3.1)
1. Maintenance product
2. Not incorporated in the IE-75001-R.
3. A task swapping function is provided in Ver. 5.00/5.00A, but this function cannot be used with this software.
µPD75116H,75117H
★
APPENDIX C. RELATED DOCUMENTS
Device Related Documents
Document Name
Document Number
User’s Manual
IEM–1340
Instruction Application Table
—
75X Series Selection Guide
IF–1027
Development Tools Documents
Document Name
Document Number
IE-75000-R/IE-75001-R User’s Manual
EEU–1455
IE-75000-R-EM User’s Manual
EEU–1294
EP-75117GK-R User’s Manual
EEU–1318
PG-1500 User’s Manual
EEU–1335
Hardware
Operation Volume
EEU–1346
Language Volume
EEU–1343
RA75X Assembler Package User’s Manual
Software
PG-1500 Controller User’s Manual
EEU–1291
Other Documents
Document Name
Document Number
Package Manual
IEI–1213
Surface Mount Technology Manual
IEI–1207
Quality grade on NEC Semiconductor Devices
IEI–1209
NEC Semiconductor Device Reliability & Quality Control
—
Electrostatic Discharge (ESD) Test
—
Semiconductor Devices Quality Guide Guarantee Guide
Microcomputer Related Products Guide Other Manufacturers Volume
Note
MEI–1202
—
The information in these related documents is subject to change without notice. For design purpose, etc.,
be sure to use the latest ones.
63
µPD75116H,75117H
64
µPD75116H,75117H
65
µPD75116H,75117H
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.