DATA SHEET MOS INTEGRATED CIRCUIT µPD75P108B 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75P108B is a version of the µPD75108 in which the on-chip mask ROM is replaced by one-time PROM which can be written to once only, or EPROM which is capable of program write, erasure and rewrite. Also, since the µPD75P108B is capable of program write by a user, it can easily be exchanged with the mask version, allowing evaluation at low voltage. Detailed functional descriptions are shown in the following User’s Manual. Be sure to read for designations. µPD751×× Series User’s Manual : IEM-922 FEATURES • Version with on-chip PROM, allowing low-voltage operation VDD = 2.7 to 6.0 V • µPD75108 compatible • Memory capacity • Program memory (PROM) : 8064 × 8 bits : 512 × 4 bits • Data memory (RAM) • Correspondence to QTOP™ microcomputer ORDERING INFORMATION Ordering Code µ PD75P108BCW µ PD75P108BDW µ PD75P108BGF-3BE Note Package On-Chip ROM 64-pin plastic shrink DIP (750 mil) 64-pin ceramic shrink DIP (with window) One-time PROM EPROM 64-pin plastic QFP (14 × 20 mm, 1.0 mm pitch) One-time PROM ★ There is no on-chip pull-up resistor function by means of a mask option. QUALITY GRADE Standard Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. In this ducument, common parts of one-time PROM products and EPROM products are represented as PROM. The information in this document is subject to change without notice. Document No. IC-2580C (O. D. No. IC-7987C) Date Published December 1993 P Printed in Japan The mark ★ shows major revised points. © NEC Corporation 1989 µPD75P108B PIN CONFIGURATION (TOP VIEW) 64-pin plastic shrink DIP (750 mil) 64-pin ceramic shrink DIP (with window) 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 µPD75P108BCW µPD75P108BDW P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 PTH01 PTH00 TI0 TI1 P23 P22/PCL P21/PTO1 P20/PTO0 P03/SI P02/SO P01/SCK P00/INT4 P123 P122 P121 P120 P133 P132 P131 P130 P143 P142 P141 P140 V PP V DD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 V SS P90 P91 P92 P93 P80 P81 P82 P83 P70 P71 P72 P73 P60 P61 P62 P63 X1 X2 RESET P50 P51 P52 P53 P40 P41 P42 P43 P30/MD0 P31/MD1 P32/MD2 P33/MD3 µPD75P108B P42 P43 P30/MD0 P31/MD1 P32/MD2 P33/MD3 V DD V PP P140 P141 P142 P143 P130 64-pin plastic QFP (14 × 20 mm, 1.0 mm pitch) 64 636261605958575655545352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 µPD75P108BGF-3BE 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P131 P132 P133 P120 P121 P122 P123 P00/INT4 P01/SCK P02/SO P03/SI P20/PTO0 P21/PTO1 P22/PCL P23 T11 T10 PTH00 PTH01 m P81 P80 P93 P92 P91 P90 V SS P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 P41 P40 P53 P52 P51 P50 RESET X2 X1 P63 P62 P61 P60 P73 P72 P71 P70 P83 P82 3 µPD75P108B OVERVIEW OF FUNCTIONS Description Item Basic instructions 43 Minimum instruction execution time 0.95 µs, 1.91 µs, 15.3 µs (4.19 MHz operation) 3-stage switching capability ROM 8064 × 8 RAM 512 × 4 Internal memory General register 4-bits × 8 × 4 banks (memory mapping) Accumulator 3 types of accumulators corresponding to bit length of manipulated data • 1-bit accumulator (CY), 4-bit accumulator (A), 8-bit accumulator (XA) Input/output port Total 58 • CMOS input pins • CMOS input/output pins (LED direct drive capability) • Middle-high voltage N-ch open-drain input/output pins (LED direct drive capability) • Comparator input pins (4-bit precision) Timer/counter • 8-bit timer/event counter × 2 • 8-bit basic interval timer (watchdog timer applicable) 8-bit serial interface • Two transfer modes • Serial transmity receive mode • Serial receive mode • LSB-first/MSB-first switchable Vectored interrupt External : 3, internal : 4 Test input External : 2 Standby • STOP/HALT mode Instruction set ★ 4 • • • • : 10 : 32 : 12 : 4 Various bit manipulation instructions (set, reset, test, boolean operation) 8-bit data transfer, comparison, operation, increment/decrement instructions 1-byte relative branch instruction GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte Others • Bit manipulation memory (bit sequential buffer : 16 bits) on-chip Package • 64-pin plastic shrink DIP (750 mil) • 64-pin ceramic shrink DIP (with window) • 64-pin plastic QFP (14 × 20mm, 1.0 mm pitch) INTBT SP(8) PROGRAM COUNTER (13) ALU TIMER/EVENT COUNTER #0 TI0 PTO0/P20 PORT 0 4 P00-P03 PORT 1 4 P10-P13 PORT 2 4 P20-P23 PORT 3 4 P30-P33 /MD0-MD3 PORT 4 4 P40-P43 PORT 5 4 P50-P53 PORT 6 4 P60-P63 PORT 7 4 P70-P73 PORT 8 4 P80-P83 PORT 9 4 P90-P93 PORT 12 4 P120-P123 PORT 13 4 P130-P133 PORT 14 4 P140-P143 BLOCK DIAGRAM BIT SEQ. BUFFER (16) BASIC INTERVAL TIMER CY BANK INTT0 TIMER/EVENT COUNTER #1 TI1 PTO1/P21 INTT1 SI/P03 SERIAL INTERFACE SO/P02 SCK/P01 GENERAL REG. ROM PROGRAM MEMORY 8064 × 8 BITS DECODE AND CONTROL RAM DATA MEMORY 512 × 4 BITS INTSIO INT0/P10 INT1/P11 INT2/P12 INT3/P13 INT4/P00 PTH00-PTH03 INTERRUPT CONTROL fXX / 2 4 PROGRAMMABLE THRESHOLD PORT #0 CLOCK OUTPUT CONTROL CLOCK GENERATOR X1 X2 STAND BY CONTROL CPU CLOCK Φ VPP VDD VSS RESET 5 µPD75P108B PCL/P22 CLOCK DIVIDER N µPD75P108B CONTENTS 1. ★ PIN FUNCTIONS .................................................................................................................................... 7 1.1 1.2 1.3 1.4 PORT PINS ..................................................................................................................................................... OTHER PINS ................................................................................................................................................... PIN INPUT/OUTPUT CIRCUITS ................................................................................................................... RECOMMENDED CONNECTION OF UNUSED PINS ................................................................................. 7 8 9 11 1.5 CAUTION ON USING P00/INT4 PIN AND RESET PIN .............................................................................. 12 2. DIFFERENCES BETWEEN µPD75P108B AND µPD75P116 ................................................................. 12 3. DIFFERENCES BETWEEN MASK VERSION (µPD75108) AND PROM VERSION (µPD75P108B) .. 13 4. PROM (PROGRAM MEMORY) WRITE AND VERIFY .......................................................................... 14 ★ 4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ................................................................... 14 4.2 4.3 4.4 4.5 PROGRAM MEMORY WRITE PROCEDURE ................................................................................................ PROGRAM MEMORY READ PROCEDURE ................................................................................................. ERASUER METHOD ( µPD75P108BDW only) .............................................................................................. SCREENING OF ONE-TIME PROM PRODUCTS ......................................................................................... 15 16 17 17 5. ELECTRICAL SPECIFICATIONS ............................................................................................................ 18 6. CHARACTERISTIC CURVE (REFERENCE VALUE) .............................................................................. 30 7. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 36 8. PACKAGE INFORMATION .................................................................................................................... 37 APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 39 ★ APPENDIX B. RELATED DOCUMENTATIONS .......................................................................................... 40 APPENDIX C. FONCTIONAL DIFFERENCE AMONG µPD751×× SERIES ................................................ 42 6 µPD75P108B 1. PIN FUNCTIONS 1.1 PORT PINS Pin Name Input/Output DualFunction Pin P00 Input INT4 P01 Input/output SCK P02 Input/output SO P03 Input SI Function 8-bit I/O After Reset I/O Circuit Type *1 B F 4-bit input port (PORT 0). Input E B × P10 INT0 P11 INT1 Input B Input E Programmable 4-bit input/output port (PORT 3). MD0 to MD3 Input/output can be specified bit-wise. *2 Input E INT2 P13 INT3 P20 PTO0 P21 PTO1 Input/output P22 PCL P23 — 4-bit input/output port (PORT 2). × *2 P30 to P33 Input/output P40 to P43 Input/output — 4-bit input/output port (PORT 4). Data input/output pin for program memory (PROM) write/verify (low-order 4 bits). *2 Input E P50 to P53 Input/output — 4-bit input/output port (PORT 5). Data input/output pin for program memory (PROM) write/verify (high-order 4 bits). *2 Input E P60 to P63 Input/output Programmable 4-bit input/output port (PORT 6). Input/output can be specified bit-wise. *2 Input E — P70 to P73 Input/output — 4-bit input/output port (PORT 7). *2 Input E P80 to P83 Input/output — 4-bit input/output port (PORT 8). *2 Input E — 4-bit input/output port (PORT 9). *2 Input E Input M-A Input M-A Input M-A P90 to P93 * 4-bit input port (PORT 1). Input P12 Input/output P120-P123 Input/output — N-ch open-drain 4-bit input/output port (PORT 12). +12 V withstand voltage. *2 P130-P133 Input/output — N-ch open-drain 4-bit input/output port (PORT 13). +12 V withstand voltage. *2 P140-P143 Input/output — N-ch open-drain 4-bit input/output port (PORT 14). +12 V withstand voltage. *2 1. 2. — indicates Schmitt-triggered input. LED direct drive capability 7 µPD75P108B 1.2 OTHER PINS Pin Name Input/Output DualFunction Pin PTH00 to PTH03 Input — Variable threshold voltage 4-bit analog input port. N Input — External event pulse input to timer/event counter. Or edge detection vectored interrupt input pin, or 1-bit input is also possible. B TI0 TI1 Input/output I/O Circuit Type *1 Timer/event counter output pin. Input E P21 PTO1 SCK Input/output P01 Serial clock input/output pin. Input F SO Input/output P02 Serial data output pin. Input E SI Input P03 Serial data input pin. Input B INT4 Input P00 Edge detection vector interrupt input pin (detection of both rising and falling edges). B Edge detection vector interrupt input pin (detection edge selectable). B Edge detection testable input pin (rising edge detection) B P10 INT0 Input P11 INT1 P12 INT2 Input P13 INT3 PCL Input/output X1, X2 RESET Input MD0 to MD3 Input/output P22 Clock output pin — System clock oscillation crystal/ceramic connection pin. When an external clock is used, the clock is input to X1 and the inverted clock is input to X2. — System reset input pin (low-level active). P30 to P33 Mode selection pin for program memory (PROM) write/ verify. VDD — Positive power supply pin. Applies +6 V for write/verify. VSS — GND potential pin. — Program voltage impression pin for program memory (PROM) write/verify. Connected to VDD in normal operation. Applies +12.5 V for PROM write/verify. VPP *2 8 After Reset P20 PTO0 * Function 1. 2. indicates Schmitt-triggered input. The device will not operate correctly unless VPP is connected to VDD in normal use. Input E B Input E µPD75P108B 1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the µPD75P108B are shown by in abbreviated form. (1) Type A (for Type E) VDD P-ch IN N-ch CMOS standard input buffer (2) Type B IN Schmitt-triggered input with hysteresis characteristic (3) Type D (for Type E, F) VDD data P-ch OUT output disable N-ch Push-pull output that can be made high-impedance output (P-ch and N-ch OFF) 9 µPD75P108B (4) Type E data IN/OUT Type D output disable Type A This is an input/output circuit made up of a Type D push-pull output and Type A input buffer. (5) Type F data IN/OUT Type D output disable Type B This is an input/output circuit made up of a Type D push-pull output and Type B Schmitt-triggered input. (6) Type M-A IN/OUT data output disable N-ch (+12 V Withstand Voltage) Middle-High Voltage Input Buffer (+12 V Withstand Voltage) 10 µPD75P108B (7) Type N Comparator IN + – VREF (Threshold Voltage) 1.4 RECOMMENDED CONNECTION OF UNUSED PINS Recommended Connection Pin PTH00 to PTH03 TI0 Connect to VSS or VDD. TI1 P00 Connect to VSS. P01 to P03 Connect to VSS or VDD. P10 to P13 Connect to VSS. P20 to P23 P30 to P33 P40 to P43 P50 to P53 Input status : Connect to VSS or VDD. Output status : Leave open. P60 to P63 P70 to P73 P80 to P83 P90 to P93 P120 to P123 P130 to P133 P140 to P143 RESET Connect to VDD. 11 µPD75P108B 1.5 CAUTION ON USING P00/INT4 PIN AND RESET PIN The P00/INT4 and RESET pins have a test mode setting function (for IC test) which tests internal operations of pin of the µPD75P108B in addition to those functions given in 1.1 and 1.2. The test mode is set when voltage greater than VDD is applied to either pin. Therefore, even during normal operation, the test mode is engaged when noise greater than VDD is added, thus causing interference with normal operation. For example, this problem may occure if the P00/INT4 and RESET pins wiring is too long, causing line noise. To avoid this, try to suppress line noise in wiring. If line noise is still high, try elimminating the noise using the exterior add-on components shown in the Figures below. ● CONNECT A DIODE WITH LOW VF BETWEEN THE VDD AND THE PIN. ● CONNECT A CONDENSER BETWEEN THE VDD AND THE PIN. VDD ★ VDD VDD VDD P00/INT4, RESET P00/INT4, RESET 2. DIFFERENCES BETWEEN µPD75P108B AND µPD75P116 In addition to the µ PD75P108B, the µPD75P116 is available as µPD751×× series on-chip PROM device. µPD75P108B µPD75P116 8064 × 8 bits 16256 × 8 bits 2.7 to 6.0 V 5 V ±10% 12.5 V 12.5 V –40 to +85 °C –40 to +85 °C Supply current TYP. value during operation 4 mA 5 mA Supply current TYP. value in STOP mode 0.1 µA 0.5 µA No No Parameter PROM capacity Operating voltage range Write voltage Operating temperature range Power-on reset function Package 12 • 64-pin plastic shrink DIP • 64-pin ceramic shrink DIP (with window) • 64-pin plastic QFP (14 × 20 mm, 1.0 mm pitch) • 64-pin plastic shrink DIP • 64-pin plastic QFP (14 × 20 mm, 1.0 mm pitch) µPD75P108B 3. DIFFERENCES BETWEEN MASK VERSION (µPD75108) AND PROM VERSION (µPD75P108B) Parameter µPD75P108B (PROM product) µPD75108 (Mask ROM product) • 0000H to 1F7FH • 8064 × 8 bits Program memory Pull-up resistor of ports 12,13 and 14 ★ No Mask option No Mask option Power-on reset circuit Power-on reset Power-on Flag 2.7 to 6.0 V Operating voltage range SDIP (Nos. 33 to 36) QFP (Nos. 39 to 62) P33/MD3 to P30/MD0 P33 to P30 VPP NC Pin connection SDIP (No. 31) QFP (No. 57) Electrical specification Different consumption current, etc. Refer to the parameter for each data sheet for details. Other Different noise resistance, noise radiation, etc., due to difference in the size of circuits and mask layout Note The PROM and ROM products differ in noise resistance and noise radiation. If you are considering replacement of the PROM product by the ROM product in the transition from preproduction to volume production, this should be evaluated thoroughly with the mask ROM CS product (not ES product). 13 µPD75P108B 4. PROM (PROGRAM MEMORY) WRITE AND VERIFY The ROM built into the µPD75P108B is a 8064 × 8-bit PROM. The pins shown in the table below are used to write/verify this PROM. There is no address input; instead, a method to update the address by the clock input from the X1 pin is adopted. Function Pin Name VPP Voltage applecation pin for program memory write/verify (normally VDD potential). X1, X2 Address update clock inputs for program memory write/ verify. Inverse of X1 pin signal is input to X2 pin. MD0 to MD3 Operating mode selection pin for program memory write/ verify. P40 to P43 (low-order 4 bits) 8-bit data input/output pins for progrm memory write/ P50 to P53 (high-order 4 bits) verify. Supply voltage application pin. Applies 2.7 to 6.0 V in normal operation, and 6 V for program memory write/verify. VDD Note 4.1 Pins not used in a program memory write/verify operation should be connected to VSS with a pulldown resistor. PROGRAM MEMORY WRITE/VERIFY OPERATING MODES The µPD75P108B assumes the program memory write/verify mode is +6 V and +12.5 V are applied respectively to the VDD and VPP pins. The table below shows the operating modes available by the MD0 to MD3 pin setting in this mode. Operating Mode Setting Operating Mode VPP +12.5 V VDD MD0 MD1 MD2 MD3 H L H L Program memory address zero-clear L H H H Write mode L L H H Verify mode H × H H Program inhibit mode +6 V × : L or H 14 µPD75P108B 4.2 PROGRAM MEMORY WRITE PROCEDURE The program memory writing procedure is shown below. High-speed write is possible. (1) Pull down a pin which is not used to VSS via the resistor. A low-level signal is input to the X1 pin. (2) Supply +5 V to the VDD and VPP pins. (3) (4) (5) (6) 10 µs wait. The program memory address 0 clear mode. Supply +6 V and +12.5 V respectively to VDD and VPP. The program inhibit mode. (7) (8) (9) (10) Write data in the 1-ms write mode. The program inhibit mode. The verify mode. If written, proceed to (10); if not written, repeat (7) to (9). (Number of times written in (7) to (9): X) x 1-ms additional write. (11) (12) (13) (14) The program inhibit mode. Update (+1) the program memory address by inputting 4 pulses to the X1 pin. Repeat (7) to (12) up to the last address. The program memory address 0 clear mode. (15) Change the VDD and VPP pins voltage to +5 V. (16) Power off. The diagram below shows the procedure of the above (2) to (12). Repeated X Times Write Verify Additional Write Address Increment VPP VPP VDD VDD + 1 VDD VDD X1 P40-P43 P50-P53 Data Input Data Output Data Input MD0 MD1 MD2 MD3 15 µPD75P108B 4.3 PROGRAM MEMORY READ PROCEDURE The µPD75P108B can read the content of the program memory in the following procedure. (1) Pull down a pin which is not used to VSS via the resistor. A low-level signal is input to the X1 pin. (2) Supply +5 V to the VDD and VPP pins. 10 µs wait. The program memory address 0 clear mode. Supply +6 V and +12.5 V respectively to VDD and VPP. The program inhibit mode. (3) (4) (5) (6) (7) The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at the period of inputting 4 pulses. (8) The program inhibit mode. (9) The program memory address 0 clear mode. (10) Change the VDD and VPP pins voltage to +5 V. (11) Power off. The diagram below shows the procedure of the above (2) to (9). VPP VPP VDD VDD + 1 VDD VDD X1 P40-P43 P50-P53 Data Output MD0 MD1 MD2 MD3 16 "L" Data Output µPD75P108B 4.4 ERASURE METHOD ( µPD75P108BDW only) The data contents programmed in the µPD75P108BDW can be erased by exposure to ultra-violet rays via the upper window. The wavelength of erasable UVR is approx. 250 nm. The irradiation amount required for complete erasure is 15Ws/cm 2 (UVR intensity × erasure time). Erasure requires approx. 15 to 20 minutes if a commercially available UVR lamp (wavelength 254 nm, intensity 12 mW/cm2). Note 1. If exposed directly to sunshine or a fluorescent light for a long period, the contents may be erased. For protection of the contents, mask the upper window with the lightshield cover film. Use the lightshield cover film provided by NEC for UV EPROM products. Note 2. When performing erasure, ensure that the distance between the UV lamp and the µPD75P108BDW is 2.5 cm or less. Remarks The erasure time may be increased due to deterioration of the UV lamp, dirt or stains on the package window surface. 4.5 SCREENING OF ONE-TIME PROM PRODUCTS Due to the nature of their construction, it is not possible for NEC to fully test one-time PROM products (µPD75P108BCW, µPD75P108BGF-3BE) before shipment. It is therefore recommended that screening which performs PROM verification be carried out after high-temperature storage under the conditions shown below once the necessary data has been written to the device. Storage Temperature Storage Time 125 °C 24 hours NEC offers a fee-paying service under the QTOP microcomputer name which covers one-time PROM writing, marking, screening and verification. Please contact our salesman for details. 17 ★ µPD75P108B 5. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) PARAMETER SYMBOL Supply voltage RATING UNIT –0.3 to + 7.0 V –0.3 to 13.5 V –0.3 to VDD + 0.3 V –0.3 to +13 V –0.3 to VDD + 0.3 V 1 pin –15 mA Total pins –30 mA Peak value 30 mA Effective value 15 mA Ports 0, 2 to 4, 12 to 14 total Peak value 100 mA Effective value 60 mA Ports 5 to 9 total Peak value 100 mA Effective value 60 mA VDD Supply voltage Input voltage TEST CONDITIONS VPP VI1 VI2 *1 Output voltage VO Output current high IOH Except ports 12 to 14 Ports 12 to 14 1 pin Output current low * IOL*2 Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C 1. The power supply impedance (pull-up resistor) should be 50 kΩ or more when the voltage exceeding 2. 10 V applied to ports 12, 13 and 14. Effective value should be calculated as follows: [Effective value] = [Peak value] × √duty OPERATING VOLTAGES (Ta = –40 to +85 °C) MIN. MAX. UNIT CPU *1 *2 6.0 V Programmable threshold port (comparator input) 4.5 6.0 V Other hardware *1 2.7 6.0 V PARAMETER * 18 1. 2. TEST CONDITIONS Excluding system clock oscillation circuit and programmable threshold ports. The operating voltage range varies depending on the CPU clock cycle time. See "AC characteristics". µPD75P108B CAPACITANCE (Ta = 25 °C, VDD = 0 V) PARAMETER Input capacitance Output capacitance I/O capacitance SYMBOL CIN COUT TEST CONDITIONS MIN. TYP. f = 1 MHz Unmeasured pins returned to 0 V. CIO MAX. UNIT 15 pF 15 pF 15 pF MAX. UNIT ±100 mV COMPARATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 4.5 to 6.0 V) PARAMETER SYMBOL Comparison accuracy VACOMP TEST CONDITIONS MIN. TYP. Threshold voltage VTH 0 VDD V PTH input voltage VIPTH 0 VDD V Comparator circuit current consumption PTHM7 set to "1" 1 mA 19 µPD75P108B SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT X2 ★ Ceramic resonator Crystal resonator TEST CONDITIONS MIN. Oscillator frequency (fXX) *1 VDD = Oscillation voltage VDD = range 2.0 Oscillation stabilization time *2 After VDD reaches oscillator voltage range MIN. X1 V SS Oscillator frequency (fXX) *1 X1 * 1. 2. 3. ★ 2.0 4.19 C1 C2 Oscillation stabilization time *2 External clock TYP. MAX. UNIT *3 5.0 MHz 4 ms *3 5.0 MHz 10 ms 30 ms C1 C2 X2 ★ X1 V SS PARAMETER X2 µPD74HCU04 VDD = 4.5 to 6.0 V X1 input frequency (fX) *1 2.0 5.0 MHz X1 input high/low level width (tXH , tXL ) 100 250 ns Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time. Time required to stabilize oscillation after VDD impression or STOP mode release. When using a value of fx such that 4.19MHz<fxx≤5.0MHz, if the maximum speed mode:Φ=fx/4 is set as the CPU clock frequency, 1 machine cycle becomes less than 0.95µs, with the result that the specified MIN value of 0.95 cannot be observed. ★ Note When the system clock oscillator is used, the following points should be noted concerning wiring in the section enclosed by dots, in order to prevent the effects of wiring capacitance, etc. • Keep the wiring as short as possible. • Do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows. • Ensure that oscillator capacitor connection points are always at the same potential as VSS. Do not ground in a ground pattern in which a high current flows. • Do not take a signal from the oscillator. 20 µPD75P108B RECOMMENDED CERAMIC RESONATOR MANUFACTURER Murata Mfg. Co., Ltd. PART NAME EXTERNAL CAPACITANCE OSCILLATION VOLTAGE RANGE C1 (pF) C2 (pF) MIN. (V) MAX. (V) CSAx.xxMG 2.00 to 5.00 30 30 CSTx.xxMG 2.00 to 5.00 30 30 CSTx.xxMGW 2.45 to 5.00 30 30 2.0 to 2.5 100 100 2.6 to 6.0 33 33 3.00 to 4.19 27 27 Kyocera Corporation KBR-x.xMS Toko, Inc. FREQUENCY (MHz) CRHFx.xx 2.7 6.0 2.7 6.0 3.0 6.0 RECOMMENDED CRYSTAL RESONATOR MANUFACTURER Kinseki, Ltd. PART NAME HC-49/U FREQUENCY (MHz) 2.00 to 5.00 EXTERNAL CAPACITANCE OSCILLATION VOLTAGE RANGE C1 (pF) C2 (pF) MIN. (V) MAX. (V) 22 22 2.7 6.0 21 µPD75P108B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER Input voltage high Input voltage low Output voltage high Output voltage low SYMBOL TEST CONDITIONS UNIT 0.7VDD 0.8V DD 0.7VDD VDD VDD 12 V V V VIH4 X1, X2 VDD–0.5 VDD V VIL1 Other than below 0 0.3VDD V VIL2 Ports 0 & 1, TI0 & 1, RESET 0 0.2VDD V VIH3 X1, X2 0 0.4 V VOH VOL VDD = 4.5 to 6.0 V, IOH = –1 mA VDD–1.0 V IOH = –100 µA VDD–0.5 V VDD = Ports 0, 2, to 9, I OL = 15 mA 0.35 2.0 V 4.5 to 6.0 V Ports 12 to 14, I OL = 10 mA 0.35 2.0 V VDD = 4.5 to 6.0 V, IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V 3 µA X1, X2 20 µA Ports 12 to 14 20 µA Except X1 & X2 –3 µA X1, X2 –20 µA Other than below VIN = VDD ILIH2 VIN = 12 V Input leakage current low ILIL1 Output leakage current high ILOH1 VOUT = VDD Other than below 3 µA ILOH2 VOUT = 12 V Ports 12 to 14 20 µA ILOL VOUT = 0 V –3 µA Output leakage current low VIN = 0 V ILIL2 IDD1 Power supply current *1 IDD2 IDD3 22 MAX. Other than below Ports 0 & 1, TI0 & 1, RESET Ports 12 to 14 ILIH3 * TYP. VIH1 VIH2 VIH3 ILIH1 Input leakage current high MIN. 4.19 MHz Crystal oscillation C1 = C2 = 22 pF VDD = 5 V ± 10 % *2 4 10 mA VDD = 3 V ± 10 % *3 1 2.5 mA VDD = 5 V ± 10 % 600 1800 µA VDD = 3 V ± 10 % 200 600 µA 0.1 10 µA HALT mode STOP mode, VDD = 3 V ± 10 % 1. Not including current flowing in comparator. 2. 3. When processor clock control register (PCC) is set to 0011 and CPU is operating in high-speed mode. When PCC is set to 0000 and CPU is operating in low-speed mode. µPD75P108B AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL CPU clock cycle time* (minimum instruction execution time = 1 machine cycle) TEST CONDITIONS MIN. VDD = 4.5 to 6.0 V TI0, TI1 input high/lowlevel width MAX. UNIT 0.95 32 µs 3.8 32 µs 0 1 MHz 0 275 kHz fTI tTIH, 0.48 µs 1.8 µs Input 0.8 µs Output 0.95 µs Input 3.2 µs Output 3.8 µs Input 0.4 µs tKCY/2–50 ns 1.6 µs tKCY/2–150 ns VDD = 4.5 to 6.0 V tTIL VDD = 4.5 to 6.0 V SCK cycle time tKCY VDD = 4.5 to 6.0 V SCK high/low-level width ★ tCY VDD = 4.5 to 6.0 V TI0, TI1 input frequency TYP. tKH, Output tKL Input Output SI setup time (to SCK↑) tSIK 100 ns SI hold time (from SCK↑) tKSI 400 ns SO output delay time from SCK↓ tKSO VDD = 4.5 to 6.0 V tINTH, INT0 to INT4 high/lowlevel width tINTL RESET low level width tRSL tCY VS. 300 ns 1000 ns 5 µs 5 µs VDD ★ 40 The cycle time of the CPU clock (Φ) is determined by the oscillator frequency of 32 7 6 the connected resonator and the processor clock control register (PCC). The graph on the right shows cycle time tCY characteristics against supply voltage VDD when system clock is operated. 5 Operation Guaranteed Range 4 tCY [µs] * 3 2 1 0.5 0 1 2 3 4 5 6 VDD [V] 23 µPD75P108B AC Timing Test Point (Excluding ports 0 & 1, TI0, TI1, X1, X2, RESET) 0.7 VDD 0.3 VDD 0.7 VDD 0.3 VDD Test Points Clock Timing 1/fX tXL tXH VDD - 0.5 0.4 X1 Input TI0, TI1 Input Timing 1/fTI tTIL TI0, TI1 24 tTIH 0.8 VDD 0.2 VDD µPD75P108B Serial Transfer Timing tKCY tKL tKH 0.8 VDD 0.2 VDD SCK tSIK tKSI 0.8 VDD Input Data SI 0.2 VDD tKSO SO Output Data Interrupt Input Timing tINTL tINTH 0.8 VDD INT0-INT4 0.2 VDD RESET Input Timing tRSL RESET 0.2 VDD 25 µPD75P108B DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +85 °C) PARAMETER SYMBOL Data retention supply voltage VDDDR Data retention power supply current *1 IDDDR Release signal set time tSREL Oscillation stabilization wait time tWAIT * 1. 2. 3. TEST CONDITIONS MIN. TYP. 2.0 VDDDR = 2.0 V 0.1 0 217/f x *3 Release by RESET Release by interrupt request MAX. UNIT 6.0 V 10 µA µs ms ms Does not include current flowing in the comparator. The oscillator stabilization wait time is the time during which CPU operation is halted to prevent unstable operation when oscillation begins. Depends on the setting of the basic interval timer mode register (BTM) (table below). BTM3 BTM2 BTM1 BTM0 WAIT Time (Figure in Parentheses is for fXX = 4.19 MHz) – 0 0 0 220/fXX (Approx. 250 ms) – 0 1 1 217/fXX (Approx. 31.3 ms) – 1 0 1 215/fXX (Approx. 7.82 ms) – 1 1 1 213/fXX (Approx. 1.95 ms) Data Retention Timing (STOP Mode Release by RESET) Internal RESET Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD tSREL VDDDR STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 26 µPD75P108B DC PROGRAMMING CHARACTERISTICS (Ta = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VIH1 Except X1 & X2 0.7V DD VDD V VIH2 X1, X2 VDD–0.5 VDD V VIL1 Except X1 & X2 0 0.3VDD V VIL2 X1, X2 0 0.4 V 10 µA Input voltage high Input voltage low Input leakage current ILI Output voltage high VOH IOH = –1 mA Output voltage low VOL IOL = 1.6 mA VDD supply current IDD VPP supply current IPP Note 1. 2. VIN = VIL or VIH V VDD–1.0 MD0 = VIL, MD1 = VIH 0.4 V 30 mA 30 mA Ensure that VPP does not reach +13.5 V or above including overshot. Ensure that VDD is applied before VPP and cut off after VPP. 27 µPD75P108B AC PROGRAMMING CHARACTERISTICS (Ta = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V) PARAMETER ★ ★ Address setup time *2 (to MD0↓) tAS tAS 2 µs MD1 setup time (to MD0↓) tM1S tOES 2 µs Data setup time (to MD0↓) tDS tDS 2 µs Address hold time *2 (from MD0↑) tAH tAH 2 µs Data hold time (from MD0↑) tDH tDH 2 µs Data output float delay time from MD0↑ tDF tDF 0 VPP setup time (to MD3↑) tVPS tVPS 2 µs VDD setup time (to MD3↑) tVDS tVCS 2 µs Initial program pulse width tPW tPW 0.95 Additional program pulse width tOPW tOPW 0.95 MD0 setup time (to MD1↑) tMOS tCES 2 Data output delay time from MD0↓ tDV tDV MD1 hold time (from MD0↑) tM1H tOEH MD1 recovery time (from MD0↓) tM1R tOR Program counter reset time tPCR MIN. MD0 = MD1 = VIL MAX. 130 1.0 UNIT ns 1.05 ms 21.0 ms µs 1 µs 2 µs 2 µs — 10 µs tXH, tXL — 0.125 µs X1 input frequency fX — Initial mode setting time tI — 2 µs MD3 setup time (to MD1↑) tM3S — 2 µs MD3 hold time (from MD1↓) tM3H — 2 µs MD3 setup time (to MD0↓) tM3SR — In program memory read 2 µs Address *2 data output delay time tDAD tACC In program memory read Address *2 data output hold time tHAD tOH In program memory read 0 MD3 hold time (from MD0↑) tM3HR — In program memory read 2 Data output float delay time from MD3↓ tDFR — In program memory read * 28 TYP. *1 X1 input high-/low-level width ★ TEST CONDITIONS SYMBOL tM1H + tM1R ≥ 50 µs 4.19 MHz 2 µs 130 ns µs 2 µs 1. Corresponding to µPD27C256A symbol. 2. Internal address signal is incremented by 1 on rise of 4th X1 input, and is not connected to a pin. µPD75P108B Program Memory Write Timing tVPS VPP VPP VDD tVDS VDD + 1 VDD VDD tXH X1 Data Output tXL P40-P43 P50-P53 Data Input Data Input tDS t1 tDV tOH tDF Data Input tDH tAH tDS tAS MD0 tM1R tPW tOPW tMOS MD1 tPCR tMIS tM1H MD2 tM3H tM3S MD3 Program Memory Read Timing tVPS VPP VPP VDD tVDS tXH VDD + 1 VDD VDD X1 tXL tDAD tHAD P40-P43 P50-P53 t1 Data Output Data Output tDFR tDV tM3HR MD0 MD1 tPCR MD2 tM3SR MD3 29 µPD75P108B 6. CHARACTERISTIC CURVE (REFERENCE VALUE) IDD vs VDD (Crystal Oscillation) (Ta = 25 °C) 10000 High-Speed Mode Middle-Speed Mode Low-Speed Mode HALT Mode Power Supply Current IDD (µ A) 1000 X1 100 X2 Crystal 4.19 MHz 22 pF 22 pF 10 0 1 2 3 4 5 Power Supply Voltage VDD (V) 30 6 7 µPD75P108B IDD vs VDD (Ceramic Oscillation) (Ta = 25 °C) 10000 High-Speed Mode Middle-Speed Mode Low-Speed Mode 1000 Power Supply Current IDD (µ A) HALT Mode X1 100 X2 Ceramic Resonator 4.19 MHz 30 pF 30 pF 10 0 1 2 3 4 5 6 7 Power Supply Voltage VDD (V) 31 µPD75P108B IDD vs VDD (Crystal Oscillation) (Ta = 25 °C) 10000 High-Speed Mode Middle-Speed Mode Low-Speed Mode 1000 Power Supply Current IDD (µ A) HALT Mode X1 100 X2 Crystal 2.00 MHz 22 pF 22 pF 10 0 1 2 3 4 5 Power Supply Voltage VDD (V) 32 6 7 µPD75P108B IDD vs Ta (Crystal Oscillation) (VDD = 5V) 10000 High-Speed Mode Middle-Speed Mode Low-Speed Mode Power Supply Current IDD (µ A) 1000 HALT Mode X1 100 X2 Crystal 4.19 MHz 22 pF 22 pF 10 –40 0 40 80 85 Ambient Temperature Ta (°C) 33 µPD75P108B IDD vs fX (External Clock) IDD vs fX (External Clock) (VDD = 5 V, Ta = 25 °C) (VDD = 3 V, Ta = 25 °C) X1 X2 X1 1.5 X2 Middle-Speed Mode µPD74HCU04 1.0 µPD74HCU04 3 Low-Speed Mode 0.5 Power Supply Current IDD (mA) Power Supply Current IDD (mA) High-Speed Mode Middle-Speed Mode 2 Low-Speed Mode 1 HALT Mode HALT Mode 0 0 2 3 4 X1 Input Frequency fx (MHz) 34 5 0 2 3 4 X1 Input Frequency fx (MHz) 5 µPD75P108B VOL vs IOL (Ports 12, 13 and 14) VOL vs IOL (Ports 0 and 2 to 9) VDD = 5 V 30 VDD = 6 V VDD = 4 V VDD = 3 V 20 VDD = 2.7 V 10 0 1 2 3 Low-Level Output Voltage VOL (V) (Ta = 25 °C) Low-Level Output Current IOL (mA) Low-Level Output Current IOL (mA) (Ta = 25 °C) VDD = 5 V 30 VDD = 6 V VDD = 4 V VDD = 3 V 20 VDD = 2.7 V 10 0 1 2 3 Low-Level Output Voltage VOL (V) VDD – VOH vs IOH (Ta = 25 °C) VDD = 5 V IOH (mA) 15 VDD = 6 V VDD = 4 V VDD = 3 V 10 VDD = 2.7 V 5 0 1 2 3 VDD–VOH (V) 35 µPD75P108B ★ 7. RECOMMENDED SOLDERING CONDITIONS The µPD75P108B should be mounted under the conditions recommended in the table below. For details of recommended soldering conditions for the surface mounting type, refer to the information document “Surface Mount Technology Manual” (IEI-1207) For soldering methods and conditions other than those recommended below, contact our salesman. Table 7-1 Surface Mount Type Soldering Conditions µPD75P108BGF-3BE : 64-pin plastic QFP (14 × 20 mm, 1.0 mm pitch) Soldering Method * Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 230°C, Duration: 30 sec. max. (at 210°C or above), Number of times: Once Time limit: 2 days* (thereafter 16 hours prebaking required at 125°C) VPS Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above), Number of times: 0nce Time limit: 2 days* (thereafter 16 hours prebaking required at 125°C) Wave soldering Solder bath temperature: 260°C max., Duration: 10 sec. max Number of times: Once Preheating temperature: 120°C max. (package surface temperature), Time limit: 2days* (thereafter 16 hours prebaking required at 125°C) WS60-162-1 Pin part heating Pin part temperature: 300°C max., Duration 3 sec. max. (per device lead) Pin part heating IR30-162-1 VP15-162-1 For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% 1H. Note Use of more than one soldering method should be avoided (except in the case of pin part heating). Table 7-2 Insertion Type Soldering Conditions µPD75P108BCW : 64-pin plastic shrink DIP (750 mil) µPD75P108BDW : 64-pin ceramic shrink DIP (with window) Soldering Method Soldering Conditions Wave Soldering (lead part only) Solder bath temperature: 260°C max., Duration: 10sec. max. Pin part heating Pin part temperature: 260°C max., Duration: 10sec. max. Note Ensure that the application of (wave soldering) is limited to the lead part and no solder touches the main unit directly. For Your Information Products to improve the recommended soldering conditions are available. (Improvements: Extension of the infrared reflow peak temperature to 235°C, doubled frequency, increased life, etc.) For further details, consult our sales personnel. 36 µPD75P108B 8. PACKAGE INFORMATION 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE M B C ITEM MILLIMETERS R INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 37 µPD75P108B 64 PIN CERAMIC SHRINK DIP (SEAM WELD) (750 mil) 64 33 1 32 A K J I G H L C F D N R M B M NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 58.68 MAX. 2.310 MAX. B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.46±0.05 0.018±0.002 F 0.8 MIN. 0.031 MIN. G 3.5±0.3 0.138±0.012 H 1.0 MIN. 0.039 MIN. I 2.62 0.103 J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 18.8 0.740 M 0.25±0.05 0.010 +0.002 –0.003 N R 0.25 0~15° 0.01 0~15° P64D-70-750A-1 38 µPD75P108B 64 PIN PLASTIC QFP (14×20) A B detail of lead end 33 32 51 52 C D S R Q 64 1 20 19 F G H I M J K M P N L NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.6±0.4 0.929±0.016 B 20.0±0.2 0.795 +0.008 –0.009 C 14.0±0.2 0.551+0.009 –0.008 D 17.6±0.4 0.693±0.016 F 1.0 0.039 G 1.0 0.039 H 0.40±0.10 0.016 +0.004 –0.005 0.008 I 0.20 J 1.0 (T.P.) 0.039 (T.P) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N P Q R S 0.10 0.004 2.7 0.106 0.1±0.1 0.004±0.004 5°±5° 5°±5° 3.0 MAX. 0.119 MAX. P64GF-100-3B8,3BE,3BR-2 39 µPD75P108B APPENDIX A. DEVELOPMENT TOOLS Hardware The following development tools are available for system development using the µPD75P108B. 40 In-circuit emulator for 75X series IE-75000-R-EM *2 Emulation board for IE-75000-R and IE-75001-R EP-75108CW-R Emulation probe for µPD75P108BCW EP-75108GF-R Emulation probe for µPD75P108BGF A 64-pin conversion socket EV-9200G-64 is provided. EV-9200G-64 PG-1500 PROM programmar PA-75P108CW This is a PROM programmar adopter for µPD75P108BCW and connects to PG-1500. PA-75P116GF This is a PROM programmar adopter for µPD75P108BGF and connects to PG-1500. IE control program Software * IE-75000-R *1 IE-75001-R PG-1500 controller RA75X relocatable assembler Host machine PC-9800 series (MS-DOS™ Ver.3.30 to Ver.5.00A *3) PC/AT™ series (PC-DOS™ Ver.3.10) 1 Maintenance product 2 3 This is not incorporated in the IE-75001-R. A task swap function is not provided with Ver.5.00/5.00A; however, a task swap function cannot be used with this software. µPD75P108B APPENDIX B. RELATED DOCUMENTATIONS List of Device-Related Documentations Document Name Document No. User's Manual IEM-922 Instruction Using Table IEM-902 (I) Introductory Volume Application Note IEM-980 (II) Remote-Controlled Reception Volume IEM-5003 (III) Bar-Code Reade-Volume IEM-5065 (IV) IC Control for MSK Transmission/Reception Volume 75X Series Selection Guide IEA-694 IF-151 List of Development Tool Related Documentations Software Hardware Document Name Document No. IE-75000-R/IE-75001-R User's Manual EEU-846 IE-75000-R-EM User's Manual EEU-673 EP-75108CW-R User's Manual EEU-696 EP-75108GF-R User's Manual EEU-695 PG-1500 User's Manual EEU-651 Operation Volume EEU-731 Language Volume EEU-730 RA75X Assembler Package User's Manual PG-1500 Controller User's Manual EEU-704 Other Documentations Document Name Document No. Package Manual IEI-635 Surface Mount Technology Manual IEI-1207 Quality Grade on NEC Semiconductor Devices IEI-1209 NEC Semiconductor Device Reliability Quality Control IEM-5068 Static Discharge (ESD) Test MEM-539 Semiconductor Device Quality Guarantee Guide MEI-603 Microcomputer Related Product Guide Other Manufacturer Volume MEI-604 Note The above related documentations may be changed without notice. Be sure to use the latest documentations for designations. 41 µPD75P108B [MEMO] 42 µPD75P108B APPENDIX C. FONCTIONAL DIFFERENCES AMONG µPD751×× SERIES Product Name Item µPD75104/106/108/112/116 µPD75104A/108A µPD75108F/112F/116F 4K/6K/8K/12K/16K (Mask ROM) 320/320/512/512/512 4K/8K (Mask ROM) 320/512 8K/12K/16K (Mask ROM) 512 ROM (byte) RAM (× 4 bits) Instruction set 75X High-End I/O Port Total CMOS input 10 CMOS input/output 32 (LED can be driver directly) N-ch open-drain output Withstand Voltage 10 32 (LED can be driver directly) 32 (Pull-up resistor mask option : 24, LED can be driverndirectly) 12 (LED can be driven directly) +12 V Pull-up resistor +10 V Can be incorporated by mask option 4 (4-bit accuracy) Analog input Power-on reset circuit Power-on flag Incorporated (mask option) No Operating voltage 2.7 to 6.0 V 2.7 to 5.0 V (Ta = –40 to +50°C) 2.8 to 5.0 V Operating temperature rang –40 to 85C° –40 to +60 °C 0.95 µs (Operation at 4.5 to 6.0 V) 3.8 µs (Operation at 2.7 V) 0.95 µs (Operation at 4.5 to 5.0 V) 1.91 µs (Operation at 2.7 V) Minimum instruction excution time Package *3 * 58 10 (Pull resistor mask option : 4) • 64-pin plastic shrink DIP • 64-pin plastic QFP (GF-3BE) • 64-pin plastic QFP (GC-AB8) • 64-pin plastic QFP (G-22) : µPD75108A only • 64-pin plastic QFP (GF-3BE) 1. Under development 2. 3. Can be used as 75X High-End by 16K-byte mode/24K-byte mode switching function There are four kinds of plastic QFP. •GC-AB8 ........14 × 14 × 2.55 mm, 0.8 mm pitch •GF-3BE ........14 × 20 × 2.7 mm, 1.0 mm pitch •G-22 ............. 14 × 14 × 1.5 mm, 0.8 mm pitch •GK-8A8 ........12 × 12 × 1.4 mm, 0.65 mm pitch 43 µPD75P108B µPD75116H/117H 16K/24K (Mask ROM) 768 75X High-End/expanded High-End µPD75P108B µPD75P116 µPD75P117H 512 24K (One-time PROM) 768 75X High-End 75X expanded High-End *2 8K (One-time PROM, EPROM) 8K (One-time PROM) 58 10 32 (LED can be driver directly : 8) 32 (LED can be driver directly) 32 (LED can be driver directly : 8) 12 12 (LED can be driver directly) 12 +6 V +12 V +6 V Can be incorporated by mask option No 4 (4-bit accuracy) No 1.8 to 5.0 V –40 to +60 °C No 5 V ±10% 2.7 to 6.0 V –40 to +85 °C 0.95 µs (Operation at 2.7 V) 1.91 µs (Operation at 1.8 V) 0.95 µs (Operation at 4.5 to 6.0 V) 3.8 µs (Operation at 2.7 V) 0.95 µs (Operation at 4.75 to 5.5 V) • 64-pin plastic QFP (GC-AB8) • 64-pin plastic QFP (GK-8A8) • 64-pin plastic shrink DIP • 64-pin ceramic shrink DIP (with window) • 64-pin plastic QFP (GF-3BE) • 64-pin plastic shrink DIP • 64-pin plastic QFP (GF-3BE) 44 1.8 to 5.0 V –40 to +60 °C 0.95 µs (Operation at 2.7 V) 1.91 µs (Operation at 1.8 V) • 64-pin plastic QFP (GC-AB8) • 64-pin plastic QFP (GK-8A8) *1 µPD75P108B [MEMO] 45 µPD75P108B [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 QTOP is a trademark of NEC Corporation. MS-DOS is a trademark of MicroSoft Corporation. PC/AT, PC DOS is a trademark of IBM Corporation.