DATA SHEET MOS INTEGRATED CIRCUIT µPD78P324, 78P324(A) 16-/8-Bit Single-Chip Microcomputers The µPD78P324 is a product in which the µPD78324’s internal mask ROM is replaced by a one-time PROM or EPROM. The one-time PROM product, which enables writing only once, is effective for multiple-device small production of sets or early start of mass-production. The EPROM product, which enables program writing, deletion, and rewriting, is the most suitable for system evaluation. The µPD78P324(A) is more reliable than the µPD78P324. The µPD78P324(A) is a product resulting from the µPD78324(A) whose internal mask ROM is replaced by a one-time PROM. For details of functions, please refer to the following User’s Manual. Reading this manual is indispensable especially for designing work. µPD78322 User’s Manual: IEU-1248 FEATURES ● µPD78324 compatible • For mass-production, this can be replaced by the µPD78324 incorporated in the mask ROM. ● Minimum instruction run time: 250 ns (with the external clock operating at 16 MHz): µPD78P324 & 78P324(A) 320 ns (with the external clock operating at 12.5 MHz): µPD78P324(A1) & 78P324(A2) ● Internal PROM: 32768 x 8 bits • Writing enabled only once (windowless one-time PROM product) • Elimination by ultraviolet light and electrical rewriting enabled (EPROM product with window): µPD78P324 only ● ECC circuit incorporated • High internal PROM content reliablility possible ● PROM programming characteristic: µPD27C1001A compatible ● QTOPTM microcomputer compatible Remark A QTOP microcomputer is a single-chip microcomputer with one-time PROM for which program writing, marking, screening, and verifying is completely supported by NEC. APPLICATION FIELDS ● µPD78P324: Fields dealing with motor control equipment. ● µPD78P324(A), 78P324(A1), and 78P324(A2): Automotive and transportation equipments, etc. This document describes the µPD78P324, 78P324(A), µPD78P324(A1), and µPD78P324(A2) as well. However, unless there are particular differences, the µPD78P324 is described as a representative product. PROM is the representative term used for the part common to both the one-time PROM product and the EPROM product. The information in this document is subject to change without notice. Document No. IC-2857 (O. D. No. IC-8315) Date Published January 1995 P Printed in Japan © 1991, 1995 µPD78P324, 78P324(A) ORDERING INFORMATION Part No. Package Internal ROM Operating Temperature (TA) µPD78P324GJ-5BJ 74-pin plastic QFP(20 x 20 mm) One-time PROM –10 to +70 °C µPD78P324LP 68-pin plastic QFJ(■ ■ 950 mil) One-time PROM –10 to +70 °C µPD78P324KC 68-pin ceramic WQFN EPROM –10 to +70 °C µPD78P324KD 74-pin ceramic WQFN EPROM –10 to +70 °C µPD78P324GJ(A)-5BJ 74-pin plastic QFP(20 x 20 mm) One-time PROM –40 to +85 °C µPD78P324GJ(A1)-5BJ 74-pin plastic QFP(20 x 20 mm) One-time PROM –40 to +110 °C µPD78P324GJ(A2)-5BJ 74-pin plastic QFP(20 x 20 mm) One-time PROM –40 to +125 °C µPD78P324LP(A) 68-pin plastic QFJ(■ ■ 950 mil) One-time PROM –40 to +85 °C µPD78P324LP(A1) 68-pin plastic QFJ(■ ■ 950 mil) One-time PROM –40 to +110 °C µPD78P324LP(A2) 68-pin plastic QFJ(■ ■ 950 mil) One-time PROM –40 to +125 °C QUALITY GRADE Part No. Quality Grade µPD78P324GJ-5BJ Standard µPD78P324LP Standard µPD78P324KC Standard µPD78P324KD Standard µPD78P324GJ(A)-5BJ Special µPD78P324GJ(A1)-5BJ Special µPD78P324GJ(A2)-5BJ Special µPD78P324LP(A) Special µPD78P324LP(A1) Special µPD78P324LP(A2) Special Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 µPD78P324, 78P324(A) DIFFERENCES AMONG µPD78P324, 78P324(A), 78P324(A1), AND 78P324(A2) Product Name µPD78P324 µPD78P324(A) µPD78P324(A1) µPD78P324(A2) Parameter Quality grade Operating ambient temperature (TA) Standard Special –10 to +70 °C –40 to +85 °C –40 to +110 °C –40 to +125 °C Operating frequency 8 to 16 MHz 8 to 12.5 MHz Minimum instruction execution time 250 ns (when operated at 16 MHz) 320 ns (when operated at 12.5 MHz) Permissible pin injection current characteristics on overvoltage application None Provided DC characteristics Differ in the analog pin input leak current, the VDD supply current, and the data retention current. AC characteristics Differ in the bus timing. A/D converter characteristics Differ in the analog input voltage and the A/D converter data retention current. One-time PROM product EPROM product Provided Provided None 3 µPD78P324, 78P324(A) PIN CONFIGURATION (Top View) (1) Normal operation mode P42/AD2 P41/AD1 P40/AD0 ASTB P90/RD P91/WR P92/TAS P93/TMD VSS EA P07/RTP7 P06/RTP6 P05/RTP5 P04/RTP4 P03/RTP3 P02/RTP2 P01/RTP1 NC (a) 74-pin plastic QFP(20 x 20 mm); 74-pin ceramic WQFN PØ0/RTP0 WDTO VSS NC X1 X2 RESET P85/TO11 P84/TO10 P83/TO03 P82/TO02 P81/TO01 P80/TO00 NC P34/SCK P33/SI/SB1 P32/SO/SB0 P31/RXD P30/TXD NC P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVREF AVDD VDD P20/NMI P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P25/INTP4 P26/INTP5 P27/INTP6 NC µ PD78P324KD µ PD78P324GJ-5BJ µ PD78P324GJ(A)-5BJ µ PD78P324GJ(A1)-5BJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 µ PD78P324GJ(A2)-5BJ P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 NC P56/A14 P57/A15 VDD AVSS P70/AN0 P71/AN1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Caution As a measure against noise, please connect the NC pin to VSS. (It is also possible to leave this pin unconnected.) Remark 4 Pin-compatible with µPD78324GJ. µPD78P324, 78P324(A) P72/AN2 P73/AN3 P74/AN4 2 P75/AN5 3 P76/AN6 4 P77/AN7 5 AVREF P20/NMI 6 VDD P21/INTP0 7 AV DD P22/INTP1 8 1 68 67 66 65 64 63 62 61 60 P71/AN1 11 59 P70/AN0 P32/SO/SB0 12 58 AVSS P33/SI/SB1 13 57 VDD P34/SCK 14 56 P57/A15 P80/TO00 15 55 P56/A14 54 P55/A13 49 P50/A8 X2 22 48 P47/AD7 X1 23 47 P46/AD6 VSS 24 46 P45/AD5 WDTO 25 45 P44/AD4 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P43/AD3 P01/RTP1 RTP0/P00 P42/AD2 21 P41/AD1 P51/A9 RESET P40/AD0 P52/A10 50 ASTB 51 µ PD78P324LP(A2) P90/RD µ PD78P324LP(A1) 20 P91/WR 19 P85/TO11 P92/TAS P84/TO10 P93/TMD P53/A11 VSS 52 EA µ PD78P324LP(A) P07/RTP7 18 P06/RTP6 P54/A12 P05/RTP5 53 P83/TO03 P04/RTP4 17 µ PD78P324KC P03/RTP3 P82/TO02 P02/RTP2 16 µ PD78P324LP P81/TO01 Remark P23/INTP2 P31/RXD P24/INTP3 9 10 P25/INTP4 P30/TXD P26/INTP5 P27/INTP6/T1 (b) 68-pin plastic QFJ(■ ■ 950 mil); 68-pin ceramic WQFN Pin-compatible with µPD78324LP. 5 µPD78P324, 78P324(A) P00-P07 : Port0 RESET : Reset P20-P27 : Port2 X1, X2 : Crystal P30-P34 : Port3 WDTO : Watchdog Timer Output P40-P47 : Port4 EA : External Access P50-P57 : Port5 TMD : Turbo Mode P70-P77 : Port7 TAS : Turbo Access Strobe P80-P85 : Port8 WR : Write Strobe P90-P93 : Port9 RD : Read Strobe NMI : Nonmakable Interrupt ASTB : Address Strobe INTP0-INTP6 : Interrupt from Peripherals AD0-AD7 : Address/Data Bus RTP0-RTP7 : Realtime Port A8-A15 : Address Bus TI : Timer Input AN0-AN7 : Analog Input TXD : Transmit Data AVREF : Analog Reference Voltage RXD : Receive Data AVSS : Analog VSS SB0/SO : Serial Bus/Serial Output AVDD : Analog VDD SB1/SI : Serial Bus/Serial Input VDD : Power Supply SCK : Serial Clock VSS : Ground TO00-TO03 : Timer Output : NC : Non-connection TO10, TO11 6 µPD78P324, 78P324(A) (2) PROM programming mode (RESET = H, AVDD = L) VSS VPP A7 A6 A5 A4 A3 A2 A1 NC A0 (Open) VSS NC (G) (Open) RESET A14 A13 A12 A11 A10 A8 NC A16 A15 PGM CE OE NC (L) (G) AVDD VDD A9 NC Cautions µ PD78P324KD (G) µ PD78P324GJ-5BJ VDD µ PD78P324GJ(A)-5BJ (L) µ PD78P324GJ(A1)-5BJ NC µ PD78P324GJ(A2)-5BJ (L) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 1 55 2 54 3 53 4 52 5 51 6 50 7 49 8 48 9 47 10 46 11 45 12 44 13 43 14 42 15 41 16 40 17 39 18 38 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 (G) D3 D4 D5 D6 D7 (L) D2 D1 D0 (Open) (a) 74-pin plastic QFP (20 x 20 mm); 74-pin ceramic WQFN 1. Codes marked by brackets refer to processing by pins unused in PROM programming mode. L : Connect to VSS individually via a resistor. G : Connect to VSS. Open : Do not connect anything. 2. As a measure against noise, please connect the NC pin to VSS. (It is also possible to leave this pin unconnected.) 7 µPD78P324, 78P324(A) 7 6 5 4 3 (G) AVDD 2 1 68 67 66 65 64 63 62 61 60 OE 10 CE 11 59 PGM 12 58 A15 13 57 A16 14 56 A8 15 A10 16 µ PD78P324LP 54 A11 17 µ PD78P324KC 53 A12 18 µ PD78P324LP(A) 52 A13 19 µ PD78P324LP(A1) 51 A14 20 µ PD78P324LP(A2) 50 RESET 21 49 (Open) 22 48 D7 23 47 D6 24 46 D5 25 45 D4 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 D3 VDD (L) D2 D1 D0 (Open) (L) VSS A7 VPP A6 A5 A1 A0 A4 (Open) A3 VSS (G) 55 A2 (G) Caution 8 VDD 9 A9 (L) (G) (b) 68-pin plastic QFJ(■ ■ 950 mil); 68-pin ceramic WQFN Codes marked by brackets refer to processing by pins unused in PROM programming mode. L : Connect to VSS individually via a resistor. G : Connect to VSS. Open : Do not connect anything. A0-A16 : Address Bus RESET D0-D7 : Data Bus AVDD CE : Chip Enable VPP : Programming Mode Set : : Programming Power Supply OE : Output Enable NC : Non-connection PGM : Programming Mode 8 PROM Peripheral RAM BCU (P20) NMI INTP0-INTP5 (P21-P26) (P80) TO00 (P81) TO01 (P82) TO02 (P83) TO03 (P84) TO10 (P85) TO11 (P27) T1/INTP6 PROGRAMMABLE INTERRUPT CONTROLLER TINER/COUNTER UNIT (REAL TIME PULSE UNIT) GENERAL REGISTERS 128 bytes & DATA MEMORY 128 bytes 32K bytes ALU 768 bytes MICRO SEQUENCE CONTROL SYSTEM CONTROL & BUS CONTROL & PREFETCH CONTROL X1 X2 RESET ASTB RD WR TAS TMD EA/VPP* A8-A15 (P50-P57) AD0-AD7 (P40-P47) A0-A16* D0-D7* PGM* CE* OE* ECC MICRO ROM INTERNAL BLOCK DIAGRAM EXU Main RAM (P34) SCK (P32) SO/SB0 (P33) SI/SB1 SERIAL INTERFFACE (SBI) (UART) A/D CONVERTER (10 BITS) WDT PORT (P30) TXD 9 µPD78P324, 78P324(A) *: When in PROM programming mode P00-P07 (REALTIME PORT) P20-P27 P30-P34 P40-P47 P50-P57 P70-P77 P80-P85 P90-P93 AVREF AVSS AVDD AN0-AN7 (P70-P77) Remark WDTO 2 VDD 2 VSS (P31) RXD µPD78P324, 78P324(A) TABLE OF CONTENTS 1. LIST OF PIN FUNCTIONS ........................................................................................................... 11 1.1 NORMAL OPERATION MODE ........................................................................................................... 11 1.2 PROM PROGRAMMING MODE (RESET = H, AVDD = L) ................................................................. 13 1.3 PIN I/O CIRCUIT AND UNUSED-PIN PROCESSING ....................................................................... 14 2. DIFFERENCE BETWEEN µPD78P324 AND µPD78324 .............................................................. 16 3. PROM PROGRAMMING .............................................................................................................. 17 3.1 OPERATION MODE ............................................................................................................................ 18 3.2 PROCEDURE FOR PROM WRITE ...................................................................................................... 19 3.3 PROCEDURE FOR PROM READ ........................................................................................................ 21 4. ERASURE CHARACTERISTICS (µPD78P324KC/KD ONLY) ..................................................... 22 5. ERASURE WINDOW SEAL (µPD78P324KC/KD ONLY) ........................................................... 22 6. ONE-TIME PROM PRODUCT SCREENING ................................................................................ 22 7. ELECTRICAL SPECIFICATIONS .................................................................................................. 23 8. PACKAGE DRAWINGS ................................................................................................................ 65 9. RECOMMENDED SOLDERING CONDITIONS ........................................................................... 69 APPENDIX A. CONVERSION SOCKET PACKAGE DRAWING AND RECOMMENDED SUBSTRATE INSTALLATION PATTERN .................................. 71 APPENDIX B. TOOLS ......................................................................................................................... 10 73 B.1 DEVELOPMENT TOOLS ..................................................................................................................... 73 B.2 EVALUATION TOOLS ........................................................................................................................ 77 B.3 EMBEDDED SOFTWARE .................................................................................................................... 77 µPD78P324, 78P324(A) 1. LIST OF PIN FUNCTIONS 1.1 NORMAL OPERATION MODE (1) Port pins Pin Name I/O P00-P07 I/O Function Port 0. 8-bit I/O port. I/O specifiable per bit. (Operable as a real-time output port as well.) Shared Pin Name RTP0-RTP7 P20 NMI P21 INTP0 P22 INTP1 P23 Input P24 Port 2. 8-bit input-only port. INTP2 INTP3 P25 INTP4 P26 INTP5 P27 INTP6/TI P30 TXD P31 P32 RXD I/O Port 3. 5-bit I/O port. I/O specifiable per bit. SO/SB0 P33 SI/SB1 P34 SCK P40-P47 I/O Port 4. 8-bit I/O port. I/O specifiable in units of eight bits. P50-P57 I/O Port 5. 8-bit I/O port. I/O specifiable per bit. A8-A15 P70-P77 Input Port 7. 8-bit input-only port. AN0-AN7 AD0-AD7 P80 TO00 P81 TO01 P82 I/O P83 Port 8. 6-bit I/O port. I/O specifiable per bit. TO02 TO03 P84 TO10 P85 TO11 P90 RD P91 I/O P92 P93 Port 9. 4-bit I/O port. I/O specifiable per bit. WR TAS TMD 11 µPD78P324, 78P324(A) (2) Pins other than ports (1/2) Pin Name I/O Function Shared Pin Name RTP0-RTP7 Output Real-time output port performing pulse outputs synchronously with the trigger symbols from the real-time pulse unit (RPU). P00-P07 INTP0 P21 INTP1 P22 INTP2 INTP3 P23 Input External interrupt request input of edge detection. A valid edge can be selected by the external interrupt mode register. P24 INTP4 P25 INTP5 P26 INTP6 P27/TI NMI Input Non-maskable interrupt request input of edge detection. A valid edge can be selected by the external interrupt mode register. TI Input External counter clock input to Timer 1 (TM1). RXD Input Serial data input of the asynchronous serial interface (UART). P31 TXD Output Serial data output of the asynchronous serial interface (UART). P30 SI Input Serial data input in three-wire mode of the clock synchronous serial interface. P33/SB1 SO Output Serial data input in three-wire mode of the clock synchronous serial interface. P32/SB0 SB0 I/O SB1 Serial data output in three-wire mode of the clock synchronous serial interface. P20 P27/INTP6 P32/SO P33/SI SCK I/O Serial clock I/O of the clock synchronous serial interface. AD0-AD7 I/O Address data bus for accessing external memory. P40-P47 A8-A15 Output Address bus for accessing external memory. P50-P57 RD P34 Read signal output to external memory. P90 Write signal output to external memory. P91 Output WR TAS Output Control signal output for accessing the turbo access manager (µPD71P301)Note. TMD P93 TO00 P80 TO01 P81 TO02 P82 Output Note 12 P92 Output from the real-time pulse unit. TO03 P83 TO10 P84 TO11 P85 The turbo access manager (µPD71P301) is a maintenance product. µPD78P324, 78P324(A) (2) Pins other than ports (2/2) 1.2 Pin Name I/O Function Shared Pin Name ASTB Output Access to external memory. Timing signal output for externally latching the lower address which is output from the AD0-AD7 pin. — WDTO Output Output of the signal which indicates that the watchdog timer generated a non-maskable interrupt. — EA Input Normally, the EA pin is connected to VDD. By connecting the EA pin to Vss, the system is placed in ROM-less mode to access external memory. The level of the EA pin cannot be switched over during operation. — AN0-AN7 Input Analog input to the A/D converter AVREF Input Reference voltage input of the A/D converter. — AVDD — Analog power of the A/D converter. — AVSS — Ground of the A/D converter. — RESET Input Input of the system reset. — X1 Input — X2 — Connection of the crystal oscillator for system clock generation. When clocks are supplied externally, they are input to the X1 pin and their reverse signals are input to the X2 pin. (The X2 pin can also be left unconnected.) VDD — Positive power voltage. — VSS — Ground. — NC — Internally unconnected. Please connect this to Vss. (It can also be left unconnected.) — P70-P77 — PROM PROGRAMMING MODE (RESET = H, AVDD = L) Pin Name I/O Function AVDD Input PROM programming mode setting A0-A16 Input Address bus D0-D7 I/O PGM Input Program input CE Input PROM enable input OE Input Read strobe to PROM RESET VPP Data bus Write power VDD Positive power voltage — VSS Ground NC Internally unconnected. Please connect this to VSS. (It can also be left unconnected.) 13 µPD78P324, 78P324(A) 1.3 PIN I/O CIRCUIT AND UNUSED-PIN PROCESSING The I/O circuits of the pins are shown in Table 1-1 and Figure 1-1 some of them in a simplified form. Table 1-1. I/O Circuit Types of Pins and Recommended Connection Methods When Unused Pin Name P00/RTP0-P07/RTP7 I/O Circuit Type Recommended Connection Method When Unused 5 Input status: Connected to VDD or VSS via a resistor individually. Output status: No connection required. 2 Connected to VSS. P20/NMI P21/INTP0-P26/INTP5 P27/INTP6/TI P30/TXD P31/RXD 5 P32/SO/SB0 P33/SI/SB1 8 P34/SCK P40/AD0-P47/AD7 P50/A8-P57/A15 P70/AN0-P77/AN7 P80/TO00-P83/TO03 P84/TO10, P85/TO11 5 9 P92/TAS Connected to Vss. 5 Input status: Connected to VDD or Vss via a resistor individually. Output status: No connection required. P90/RD P91/WR Input status: Connected to VDD or VSS via a resistor individually. Output status: No connection required. 5 P93/TMD WDTO 3 ASTB 4 EA 1 — RESET 2 — AVDD — Connected to VDD. — Connected to VSS. VPP — Connected to VDD. NC — Connected to VSS. (It is also possible to leave this unconnected.) No connection required. AVREF AVSS 14 µPD78P324, 78P324(A) Figure 1-1. I/O Circuits of Pins Type 1 Type 5 VDD VDD data P-ch IN/OUT P-ch IN output disable N-ch N-ch input disable Type 2 VDD Type 8 data P-ch IN/OUT IN output disable N-ch This is a Schmitt-triggered input which has the hysteresis characteristic. Type 3 Type 9 VDD P-ch IN P-ch Comparator N-ch OUT Vref (Threshold voltage) N-ch input enable Type 4 VDD data P-ch OUT output disable N-ch This is the push-pull input which is capable of output highimpedance (off for both P-ch and N-ch). 15 µPD78P324, 78P324(A) 2. DIFFERENCES BETWEEN µPD78P324 AND µPD78324 The µPD78P324 is a product in which the µPD78324’s internal mask ROM is replaced by a 32KB PROM. Therefore, these two products share the same functions, except for differences deriving from the ROM specifications (for example, Write and Verify, etc.). Their differences are shown in Table 2-1 below. Table 2-1. Differences between µPD78P324 and µPD78324 Product Name µPD78P324 µPD78324 Parameter Internal program memory (Electric write) One-time PROM (Write enabled only once) EPROM (Rewrite enabled) Mask ROM ECC circuit With Without PROM programming pin With Without • 68-pin plastic QFJ • 74-pin plastic QFP Package • 68-pin ceramic WQFN • 74-pin ceramic WQFN • 68-pin plastic QFJ • 74-pin plastic QFP Electrical characteristics Differ in current consumption, etc. Others As they differ in their circuit size and mask layout, their noise resistance volume and noise reflection differ. Cautions 1. The PROM product and the mask ROM product differ in their noise resistance volume and noise reflection. If replacement of the PROM product with the mask ROM product in the process of trial to mass production is being considered, ensure to make a sufficient evaluation with the CS product (not ES product) of the mask ROM product. 2. The µPD78P324(A)/(A1)/(A2) are one-time PROM products only. The differences between the µPD78P324(A)/(A1)/(A2) and the µPD78324(A)/(A1)/(A2) are the same as those shown in the table above, except in terms of the EPROM product. 16 µPD78P324, 78P324(A) 3. PROM PROGRAMMING The µPD78P324 incorporates an electrically writable 32768-by-8-bit program PROM and an 8192-by-6-bit ECC (error correcting code) PROM. ECC corrects the errors in codes written in the program PROM, thus improving the reliability of the PROM content. Figure 3-1 shows the memory map in programming mode. Figure 3-1. Memory Map in Programming Mode A004H A003H ECC (for ECW) A000H 9FFFH (4 x 8) ECW PROM for ECCNote (8192 x 6) 8000H 7FFFH Program PROM (32768 x 8) 0000H Note On the ECC PROM, the lower 6 bits are valid. When programming, set the RESET pin and the AVDD pin to PROM programming mode. The programming characteristics of the µPD78P324 are compatible with the µPD27C1001A. However, the programming mode is compatible only with the byte program mode of the µPD27C1001A. For setting on the PROM programmer, please select the byte program mode of the 27C1001A mode. When using the ECC circuit, reset the lowest bit (A000.0) of the lowest byte of the ECW (ECC control word) to enable the operation of the ECC circuit. ECW is a 4-byte register which controls the operation of the ECC circuit. ECC and ECW are generated automatically with the ECCGEN (ECC generator) which comes with the RA78K3 assembler package. (ECC is generated in the lower 6 bits; and the upper 2 bits are fixed to 1.) 17 µPD78P324, 78P324(A) Table 3-1. Pin Functions in Programming Mode Function Normal Operation Mode Programming Mode P00-P07, P80, P20, P81-P85, P33, P34 A0-A16 P40-P47 D0-D07 Program pulse P32 PGM Chip enable P31 CE Output enable P30 OE Address input Data input Program voltage VPP Mode voltage 3.1 RESET, AVDD OPERATION MODE When placing the microcomputer in programming Write/Verify mode, set it to RESET = H and AVDD = L. In this mode, an operation mode in Table 3-2 can be selected by further setting the CE and OE pins. When reading the content of the PROM, set it to Read mode. Process the unused pins in accordance with the instructions in the PIN CONFIGURATION. Table 3-2. Operation Mode of PROM Programming Mode RESET AVDD CE OE PGM Program Write L H L Program verify L L H VPP X L L X H H Read L L H Output disable L H X Standby H X X Remark 18 x: L or H H L D0-D7 Data input Data output +12.5 V Program inhibit VDD +6.5 V High impedance Data output +5 V +5 V High impedance High impedance µPD78P324, 78P324(A) 3.2 PROCEDURE FOR PROM WRITE The procedure for writing into the PROM is as follows (see Figure 3-3). (1) Fix to RESET = H; and AVDD = L. Other unused pins are processed as directed by the PIN CONFIGURATION. (2) Supply +6.5 V to the VDD pin; and +12.5 V to the VPP pin. Enter the low level into the CE pin. (3) Enter the initial address into A0-A16. (4) Enter the Write data into D0-D7. (5) Enter the 0.1 ms program pulse (active low) into the PGM pin. (6) Verify mode. Check if the Write data has been written or not. Enter the active low pulse into the OE pin and read the Write data from D0-D7. • When written: Move to (8). • When not able to write: Repeat (4) to (6). If it is not possible to write even when the repetition has been made ten times, move to (7). (7) Stop the Write operation as a defective device. (8) Increment the address. (9) Repeat (4) to (8) until the final address. The timing of the above (2) to (7) steps is shown in Figure 3-2. Figure 3-2. PROM Write/Verify Timing Program A0-A16 D0-D7 Program verify Address input Hi-Z Data input Hi-Z Data output Hi-Z + 12.5V VPP VDD + 6.5V VDD VDD CE (input) PGM (input) OE (input) 19 µPD78P324, 78P324(A) Figure 3-3. Write Procedure Flowchart (1) Start writing (2) Supply the supply voltage (3) Supply the initial address (4) Supply the Write data (5) Supply the program pulse (6) Write disabled ( less than 10 times ) Write disabled ( 10th times ) Verify mode Write OK (8) ≤Final address Address increment (9) Final address >Final address (10) 20 Write complete (7) Defective device µPD78P324, 78P324(A) 3.3 PROCEDURE FOR PROM READ The PROM content is read to the external data bus (D0-D7) in accordance with the following procedure: (1) Fix to RESET = H; and AVDD = L. Other unused pins are processed as directed by the PIN CONFIGURATION. (2) Supply +5 V to the VDD and VPP pins. (3) Enter the address of the data read into the A0-A16 pin. (4) Read mode (CE = L; OE = L) (5) Data is output to the D0-D7 pin. The timing of the above (2) to (5) is shown in Figure 3-4. Figure 3-4. PROM Read Timing A0-A14 Address input CE (input) OE (input) Hi-Z D0-D7 Hi-Z Data output 21 µPD78P324, 78P324(A) 4. ERASURE CHARACTERISTICS (µPD78P324KC/KD ONLY) The µPD78P324KC/KD can erase (FFH) the content of the data written in the program memory and perform rewriting. The data content is erased by radiating light with a wavelength shorter than about 400 nm on the erasure window. Normally, ultraviolet light with a wavelength of 254 nm is radiated. The volume of light required for erasing the data content completely is as follows: • Ultraviolet ray intensity x erasure time: 15 W·s/cm2 or more • Erasure time: 15 to 20 mins (This is so when using an ultraviolet lamp of 12,000 µW/cm2. However, a longer time may be required due to performance degradation of the ultraviolet ray lamp or dirt deposited on the erasure window, etc.) For erasure, make sure to place the ultraviolet ray lamp at a location within 2.5 cm from the erasure window. If the ultraviolet ray lamp is equipped with a filter, make sure that the filter is removed for radiation. 5. ERASURE WINDOW SEAL (µPD78P324KC/KD ONLY) If the erasure window part of the µPD78P324KC/KD is exposed to sunlight or fluorescent light for too long, the EPROM data may be erased or the internal circuits may malfunction. To prevent such an accident, please ensure that the erasure window part is covered with a protective seal except when the data is going to be erased. The EPROM package with window is shipped with a protective seal that is NEC’s guarantee of quality. 6. ONE-TIME PROM PRODUCT SCREENING Structurally, it is not possible for NEC to test the one-time PROM products (µPD78P324GJ-5BJ/(A)/(A1)/ (A2) and 78P324LP/(A)/(A1)/(A2) completely before shipment. Therefore, it recommended that, after writing the required data, the screening be implemented to verify the PROM after storing the product in the following temperature and condition. Storage Temperature Storage Time 125 °C 24 hrs NEC provides at a charge services including the one-time PROM writing, sealing, screening and verifying under the title of QTOP microcomputer. For further details, please contact an NEC salesperson. 22 µPD78P324, 78P324(A) 7. ELECTRICAL SPECIFICATIONS (1) µPD78P324 Electrical Specifications (1/9) Absolute Maximum Ratings (TA = 25 °C) Parameter Condition Symbol Rating Unit –0.5 to +7.0 V –0.5 to VDD +0.5 V VPP –0.5 to +13.5 V AVSS –0.5 to +0.5 V –0.5 to VDD +0.5 V –0.5 to VDD +0.5 V All output pins 4.0 mA Total of all output pins 90 mA All output pins –1.0 mA Total of all output pins –20 mA VDD AVDD Supply voltage Input voltage VI Output voltage VO Low-level output current IOL High-level output current Note 1 IOH Analog input voltage VIAN A/D converter reference input voltage Note 2 AVREF AVDD > VDD –0.5 to VDD +0.5 VDD ≥ AVDD –0.5 to AVDD +0.5 AVDD > VDD –0.5 to VDD +0.5 VDD ≥ AVDD –0.5 to AVDD +0.5 V V Operating ambient temperature TA –10 to +70 °C Storage temperature Tstg –65 to +150 °C Notes 1. Except P70/AN0-P77/AN7. 2. P70/AN0-P77/AN7 pins. Caution If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding these ratings. Recommended Operating Range Oscillation Frequency TA VDD 8MHz ≤ fXX ≤ 16MHz –10 to +70 °C +5.0 V ±10 % Capacitance (TA = 25 °C, VSS = VDD = 0 V) Parameter Input capacitance Symbol Condition CI Output capacitance CO I/O capacitance CIO f = 1 MHz; 0 V except measured pins MIN. TUP. MAX. Unit 10 pF 20 pF 20 pF 23 µPD78P324, 78P324(A) (1) µPD78P324 Electrical Specifications (2/9) Oscillator Characteristics (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V) Oscillator Recommended Circuit X2 Ceramic oscillator or crystal oscillator X1 C2 MAX. Unit Oscillation frequency (fXX) 8 16 MHz X1 input frequency (fX) 8 16 MHz X1 input rise time, fall time (tXR, tXF) 0 20 ns X1 input high-/low-level width (tWXH, tWXL) 25 80 ns X2 HCMOS inverter or External clock X1 X2 No connection required HCMOS inverter Caution MIN. VSS C1 X1 Parameter When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. • Make the wiring as short as possible. • Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. • Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. • Do not fetch signals from the oscillation circuit. 24 µPD78P324, 78P324(A) (1) µPD78P324 Electrical Specifications (3/9) Recommended Oscillation Circuit Constants Ceramic Oscillator Recommended Constant Manufacturer Murata Mfg. Co., Ltd. Product Name Frequency (MHz) CSA8.00MT 8.0 CSA12.0MT 12.0 CSA14.74MXZ040 14.74 CSA16.00MX040 16.0 CST8.00MTW 8.0 CST12.0MTW 12.0 CST14.74MXW0C3 14.74 CST16.00MXW0C3 16.0 C1 (pF) C2 (pF) 30 30 15 15 Incorporated Incorporated 25 µPD78P324, 78P324(A) (1) µPD78P324 Electrical Specifications (4/9) DC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V) Parameter Low-level input voltage Symbol Condition VIL MIN. TYP. 0 MAX. Unit 0.8 V VIH1 Note 1 2.2 VIH2 Note 2 0.8 VDD Low-level output voltage VOL IOL = 2.0mA High-level output voltage VOH IOH = –400µA Input leakage current ILI Note 3 0 V ≤ VI ≤ VDD ±10 µA Analog pin input leakage current ILIAN Note 4 0 V ≤ VIAN ≤ AVREF ±10 µA Output leakage current ILO ±10 µA High-level input voltage V 0.45 VDD–1.0 V V 0 V ≤ VO ≤ VDD IDD1 Operation mode 70 95 mA IDD2 HALT mode 35 55 mA VDDDR STOP mode IDDDR STOP mode VDD supply current Data retention voltage Data retention current 2.5 V VDDDR = 2.5 V 2 10 µA VDDDR=5.0 V±10% 10 50 µA Notes 1. Pins other than pins in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins. 3. Pins except P20/NMI, EA/VPP, X1, X2 4. When not sampling the analog input 26 µPD78P324, 78P324(A) (1) µPD78P324 Electrical Specifications (5/9) AC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter Symbol Condition MIN. MAX. Unit 250 ns System clock cycle time tCYK 125 Address setup time (vs. ASTB ↓) tSAST 32 ns Address hold time (vs. ASTB ↓) tHSTA 32 ns Address → RD ↓ delay time tDAR 85 ns RD ↓ → address float time tFRA 10 ns Address → data input time tDAID 222 ns RD ↓ → data input time tDRID 112 ns ASTB ↓ → RD ↓ delay time tDSTR 42 ns Data hold time (vs. RD ↑) tHRID 0 ns RD ↑ → address active time tDRA 50 ns RD low-level width tWRL 147 ns ASTB high-level width tWSTH 37 ns Address → WR ↓ delay time tDAW 85 ns ASTB ↓ → data output time tDSTOD 102 ns WR ↓ → data output time tDWOD 40 ns ASTB ↓ → WR ↓ delay time tDSTW 42 ns Data setup time (vs. WR ↑) tSODW 147 ns Data hold time (vs. WR ↑) tHWOD 32 ns WR ↑ → ASTB ↑ delay time tDWST 42 ns WR low-level width tWWL 147 ns 27 µPD78P324, 78P324(A) (1) µPD78P324 Electrical Specifications (6/9) tCYK-dependent Bus Timing Definition Remarks Symbol Calculation formula MIN./MAX. Unit tSAST 0.5T–30 MIN. ns tHSTA 0.5T–30 MIN. ns tDAR T–40 MIN. ns tDAID (2.5+n) T–90 MAX. ns tDRID (1.5+n) T–75 MAX. ns tDSTR 0.5T–20 MIN. ns tDRA 0.5T–12 MIN. ns tWRL (1.5+n) T–40 MIN. ns tWSTH 0.5T–25 MIN. ns tDAW T–40 MIN. ns tDSTOD 0.5T+40 MAX. ns tDSTW 0.5T–20 MIN. ns tSODW 1.5T–40 MIN. ns tHWOD 0.5T–30 MIN. ns tDWST 0.5T–20 MIN. ns tWWL (1.5+n) T–40 MIN. ns 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. Among the parameters for bus timing, only those listed in this table are dependent on tCYK. 28 µPD78P324, 78P324(A) (1) µPD78P324 Electrical Specifications (7/9) Serial Operation (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V) Parameter Symbol Serial clock cycle time Serial clock low-level width Serial clock high-level width Condition MIN. MAX. Unit SCK output Internal divide-by-eight 1 µs SCK input External clock 1 µs SCK output Internal divide-by-eight 420 ns SCK input External clock 420 ns SCK output Internal divide-by-eight 420 ns SCK input External clock 420 ns tCYSK tWSKL tWSKH SI setup time (vs. SCK ↑) tSRXSK 80 ns SI hold time (vs. SCK ↑) tHSKRX 80 ns SCK ↓ → SO delay time tDSKTX R = 1 kΩ , C = 100pF 210 ns tCYK-dependent Serial Operation Symbol Condition SCK output Calculation Formula MIN./MAX. Unit Internal divide-by-eight 8T MIN. ns External clock 8T MIN. ns Internal divide-by-eight 4T–80 MIN. ns External clock 4T–80 MIN. ns Internal divide-by-eight 4T–80 MIN. ns External clock 4T–80 MIN. ns tCYSK SCK input SCK output tWSKL SCK input SCK output tWSKH SCK input Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK. 29 µPD78P324, 78P324(A) (1) µPD78P324 Electrical Specifications (8/9) Other Operations (TA = –10 to +70 °C, VDD = +5 V ±10 %, VDD = 0 V) Parameter Symbol Condition NMI high-/low-level width tWNIH, tWNIL Analog noises removed INTP0 high-/low-level width MIN. MAX. Unit 4 µs tWIOH, tWIOL 1 µs INTP1 high-/low-level width tWI1H, tWI1L 1 µs INTP2 high-/low-level width tWI2H, tWI2L 1 µs INTP3 high-/low-level width tWI3H, tWI3L 1 µs INTP4 high-/low-level width tWI4H, tWI4L 1 µs INTP5 high-/low-level width tWI5H, tWI5L 1 µs INTP6 high-/low-level width tWI6H, tWI6L 1 µs RESET high-/low-level width tWRSH, tWRSL 3.5 µs TI high-/low-level width tWTIH, tWTIL 1 µs 200 µs VDD rise/fall time Analog noises removed tRVD, tFVD Other tCYK-dependent Operations Remarks Symbol Calculation formula MIN./MAX. Unit tWIOH 8T MIN. ns tWIOL 8T MIN. ns tWI1H 8T MIN. ns tWI1L 8T MIN. ns tWI2H 8T MIN. ns tWI2L 8T MIN. ns tWI3H 8T MIN. ns tWI3L 8T MIN. ns tWI4H 8T MIN. ns tWI4L 8T MIN. ns tWI5H 8T MIN. ns tWI5L 8T MIN. ns tWI6H 8T MIN. ns tWI6L 8T MIN. ns tWTIH 8T MIN. ns tWTIL 8T MIN. ns 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Only the parameters listed in this table depend on tCYK. 30 µPD78P324, 78P324(A) (1) µPD78P324 Electrical Specifications (9/9) AC Timing Test Point VDD 0V 0.8VDD or 2.2V 0.8VDD or 2.2V Test point 0.8V 0.8V A/D Converter Characteristics (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD) Parameter Symbol Condition MIN. Resolution TYP. MAX. 10 Total errorNote1 Unit bit 4.5 V ≤ AVREF ≤ AVDD ±0.4 %FSR 3.5 V ≤ AVREF ≤ AVDD ±0.7 %FSR ±1/2 LSB Quantization error Conversion time tCONV 144 tCYK Sampling time tSAMP 24 tCYK Zero-scale errorNote1 Full-scale errorNote 1 Non-linear errorNote 1 Analog input voltageNote 2 VIAN Analog input impedance RAN 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB AVDD V 0 When not sampled 10 When sampled Reference voltage AVREF AVREF current AIREF AVDD supply current AIDD Operation mode A/D converter data retention current AIDDDR STOP mode MΩ Note 3 3.4 AVDD V 1.0 3.0 mA 2.0 6.0 mA AVDDDR = 2.5 V 2 15 µA AVDDDR=5 V±10% 10 50 µA Notes 1. Quantization error excluded. 2. When –0.3 V ≤ VIAN ≤ 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits. When AVREF ≤ VIAN ≤ AVDD, the conversion result is 3FFH. 3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (The values in the diagram are TYP. values; therefore, they are not assured.) 20kΩ Analog input pin 30pF 10pF ( input capacitance included ) 31 µPD78P324, 78P324(A) (2) µPD78P324(A) Electrical Specifications (1/9) Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Rating Unit –0.5 to +7.0 V –0.5 to VDD +0.5 V VPP –0.5 to +13.5 V AVSS –0.5 to +0.5 V –0.5 to VDD +0.5 V –0.5 to VDD +0.5 V All output pins 4.0 mA Total of all output pins 90 mA All output pins –1.0 mA Total of all output pins –20 mA Condition VDD AVDD Supply voltage Input voltage VI Output voltage VO Low-level output current IOL High-level output current Analog input voltage A/D converter reference input voltage Notes 1, 2 IOH VIAN AVREF Notes 2, 3 AVDD > VDD –0.5 to VDD +0.5 VDD ≥ AVDD –0.5 to AVDD +0.5 AVDD > VDD –0.5 to VDD +0.5 VDD ≥ AVDD –0.5 to AVDD +0.5 V V Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Notes 1. Except P70/AN0-P77/AN7. 2. The overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application is excluded. 3. P70/AN0-P77/AN7 pins. Caution If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding these ratings. 32 µPD78P324, 78P324(A) (2) µPD78P324(A) Electrical Specifications (2/9) Permissible Pin Injection Current Characteristics in Overvoltage Application (TA = –40 to +85 °C, VDD = +5 V ±10%, VSS = 0 V) Parameter Symbol Input ports other than ANn (n = 0-7) IIJH1 Positive injection current (VIN > VDD) TYP. MAX. Unit Peak value 10 mA Mean value 0.5 mA Peak value 3 mA Mean value 1 mA Peak value 100 mA Mean value 5 mA Peak value –4 mA Mean value –0.4 mA Peak value –4 mA Mean value –0.3 mA Peak value –40 mA Mean value –3 mA 1 pin IIJH2 IIJH ANn (n = 0-7) Total of all input pins Input ports other than ANn (n = 0-7) IIJL1 1 pin Negative injection current (VIN < VSS) IIJL2 IIJL Cautions MIN. Condition ANn (n = 0-7) Total of all input pins 1. When the injection current has run into the analog input pin (ANn: n = 0-7), the A/D conversion result of the analog input contiguous to the current injection pin has the value of the standard in which the injection current is not running plus ±2LSB. 2. The mean value (absolute value) of the pin injected current is as follows: Mean value = ((1/T) ∫ T | i(t) | 3/2 dt)2/3 0 In this, i(t) refers to the pin injected current. The maximum value of |i(t)| is the peak value. Recommended Operating Range Oscillation Frequency TA VDD 8MHz ≤ fXX ≤ 16MHz –40 to +85 °C +5.0 V ±10 % Capacitance (TA = 25 °C, VSS = VDD = 0 V) Parameter Input capacitance Symbol Condition CI Output capacitance CO I/O capacitance CIO f = 1 MHz; 0 V except measured pins MIN. TUP. MAX. Unit 10 pF 20 pF 20 pF 33 µPD78P324, 78P324(A) (2) µPD78P324(A) Electrical Specifications (3/9) Oscillator Characteristics (TA = –40 to +85 °C, VDD = +5 V ±10 %, VSS = 0 V) Oscillator Recommended Circuit X2 Ceramic oscillator or crystal oscillator X1 C2 MAX. Unit Oscillation frequency (fXX) 8 16 MHz X1 input frequency (fX) 8 16 MHz X1 input rise time, fall time (tXR, tXF) 0 20 ns X1 input high-/low-level width (tWXH, tWXL) 25 80 ns X2 HCMOS inverter or External clock X1 X2 No connection required HCMOS inverter Caution MIN. VSS C1 X1 Parameter When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. • Make the wiring as short as possible. • Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. • Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. • Do not fetch signals from the oscillation circuit. 34 µPD78P324, 78P324(A) (2) µPD78P324(A) Electrical Specifications (4/9) DC Characteristics (TA = –40 to +85 °C, VDD = +5 V ±10 %, VSS = 0 V) Parameter Low-level input voltage Symbol Condition VIL MIN. TYP. 0 MAX. Unit 0.8 V VIH1 Note 1 2.2 VIH2 Note 2 0.8 VDD Low-level output voltage VOL IOL = 2.0mA High-level output voltage VOH IOH = –400µA Input leakage current ILI Note 3 0 V ≤ VI ≤ VDD ±10 µA Analog pin input leakage current ILIAN Note 4 0 V ≤ VIAN ≤ AVREF ±1 µA Output leakage current ILO ±10 µA High-level input voltage V 0.45 VDD–1.0 V V 0 V ≤ VO ≤ VDD IDD1 Operation mode 70 95 mA IDD2 HALT mode 35 55 mA VDDDR STOP mode IDDDR STOP mode VDD supply current Data retention voltage Data retention current 2.5 V VDDDR = 2.5 V 2 10 µA VDDDR=5.0 V±10% 10 50 µA Notes 1. Pins other than pins in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins. 3. Pins except P20/NMI, EA/VPP, X1, X2 4. When not sampling the analog input 35 µPD78P324, 78P324(A) (2) µPD78P324(A) Electrical Specifications (5/9) AC Characteristics (TA = –40 to +85 °C, VDD = +5 V ±10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter Symbol Condition MIN. MAX. Unit 250 ns System clock cycle time tCYK 125 Address setup time (vs. ASTB ↓) tSAST 32 ns Address hold time (vs. ASTB ↓) tHSTA 32 ns Address → RD ↓ delay time tDAR 85 ns RD ↓ → address float time tFRA 10 ns Address → data input time tDAID 222 ns RD ↓ → data input time tDRID 112 ns ASTB ↓ → RD ↓ delay time tDSTR 42 ns Data hold time (vs. RD ↑) tHRID 0 ns RD ↑ → address active time tDRA 50 ns RD low-level width tWRL 147 ns ASTB high-level width tWSTH 37 ns Address → WR ↓ delay time tDAW 85 ns ASTB ↓ → data output time tDSTOD 102 ns WR ↓ → data output time tDWOD 40 ns ASTB ↓ → WR ↓ delay time tDSTW 42 ns Data setup time (vs. WR ↑) tSODW 147 ns Data hold time (vs. WR ↑) tHWOD 32 ns WR ↑ → ASTB ↑ delay time tDWST 42 ns WR low-level width tWWL 147 ns 36 µPD78P324, 78P324(A) (2) µPD78P324(A) Electrical Specifications (6/9) tCYK-dependent Bus Timing Definition Remarks Symbol Calculation formula MIN./MAX. Unit tSAST 0.5T–30 MIN. ns tHSTA 0.5T–30 MIN. ns tDAR T–40 MIN. ns tDAID (2.5+n) T–90 MAX. ns tDRID (1.5+n) T–75 MAX. ns tDSTR 0.5T–20 MIN. ns tDRA 0.5T–12 MIN. ns tWRL (1.5+n) T–40 MIN. ns tWSTH 0.5T–25 MIN. ns tDAW T–40 MIN. ns tDSTOD 0.5T+40 MAX. ns tDSTW 0.5T–20 MIN. ns tSODW 1.5T–40 MIN. ns tHWOD 0.5T–30 MIN. ns tDWST 0.5T–20 MIN. ns tWWL (1.5+n) T–40 MIN. ns 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. Among the parameters for bus timing, only those listed in this table are dependent on tCYK. 37 µPD78P324, 78P324(A) (2) µPD78P324(A) Electrical Specifications (7/9) Serial Operation (TA = –40 to +85 °C, VDD = +5 V ±10 %, VSS = 0 V) Parameter Symbol Condition SCK output Serial clock cycle time SCK output Unit Internal divide-by-eight 1 µs External clock 1 µs Internal divide-by-eight 420 ns External clock 420 ns Internal divide-by-eight 420 ns External clock 420 ns tWSKL SCK input SCK output Serial clock high-level width MAX. tCYSK SCK input Serial clock low-level width MIN. tWSKH SCK input SI setup time (vs. SCK ↑) tSRXSK 80 ns SI hold time (vs. SCK ↑) tHSKRX 80 ns SCK ↓ → SO delay time tDSKTX R = 1 kΩ , C = 100pF 210 ns tCYK-dependent Serial Operation Symbol Condition SCK output Calculation Formula MIN./MAX. Unit Internal divide-by-eight 8T MIN. ns External clock 8T MIN. ns Internal divide-by-eight 4T–80 MIN. ns External clock 4T–80 MIN. ns Internal divide-by-eight 4T–80 MIN. ns External clock 4T–80 MIN. ns tCYSK SCK input SCK output tWSKL SCK input SCK output tWSKH SCK input Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK. 38 µPD78P324, 78P324(A) (2) µPD78P324(A) Electrical Specifications (8/9) Other Operations (TA = –40 to +85 °C, VDD = +5 V ±10 %, VDD = 0 V) Parameter Symbol Condition NMI high-/low-level width tWNIH, tWNIL Analog noises removed INTP0 high-/low-level width MIN. MAX. Unit 4 µs tWIOH, tWIOL 1 µs INTP1 high-/low-level width tWI1H, tWI1L 1 µs INTP2 high-/low-level width tWI2H, tWI2L 1 µs INTP3 high-/low-level width tWI3H, tWI3L 1 µs INTP4 high-/low-level width tWI4H, tWI4L 1 µs INTP5 high-/low-level width tWI5H, tWI5L 1 µs INTP6 high-/low-level width tWI6H, tWI6L 1 µs RESET high-/low-level width tWRSH, tWRSL 3.5 µs TI high-/low-level width tWTIH, tWTIL 1 µs 200 µs VDD rise/fall time Analog noises removed tRVD, tFVD Other tCYK-dependent Operations Remarks Symbol Calculation formula MIN./MAX. Unit tWIOH 8T MIN. ns tWIOL 8T MIN. ns tWI1H 8T MIN. ns tWI1L 8T MIN. ns tWI2H 8T MIN. ns tWI2L 8T MIN. ns tWI3H 8T MIN. ns tWI3L 8T MIN. ns tWI4H 8T MIN. ns tWI4L 8T MIN. ns tWI5H 8T MIN. ns tWI5L 8T MIN. ns tWI6H 8T MIN. ns tWI6L 8T MIN. ns tWTIH 8T MIN. ns tWTIL 8T MIN. ns 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Only the parameters listed in this table depend on tCYK. 39 µPD78P324, 78P324(A) (2) µPD78P324(A) Electrical Specifications (9/9) AC Timing Test Point VDD 0V 0.8VDD or 2.2V 0.8VDD or 2.2V Test point 0.8V 0.8V A/D Converter Characteristics (TA = –40 to +85 °C, VDD = +5 V ±10 %, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD) Parameter Symbol Condition MIN. Resolution TYP. MAX. 10 Total errorNote 1 Unit bit 4.5 V ≤ AVREF ≤ AVDD ±0.4 %FSR 3.5 V ≤ AVREF ≤ AVDD ±0.7 %FSR ±1/2 LSB Quantization error Conversion time tCONV 144 tCYK Sampling time tSAMP 24 tCYK Zero-scale errorNote 1 Full-scale errorNote 1 Non-linear errorNote 1 Analog input voltageNote 2 VIAN Analog input impedance RAN 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB AVDD V 0 When not sampled 10 When sampled Reference voltage AVREF AVREF current AIREF AVDD supply current AIDD Operation mode A/D converter data retention current AIDDDR STOP mode MΩ Note 3 3.4 AVDD V 1.0 3.0 mA 2.0 6.0 mA AVDDDR = 2.5 V 2 15 µA AVDDDR=5 V±10% 10 50 µA Notes 1. Quantization error excluded. 2. When VIAN = 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits. When AVREF ≤ VIAN ≤ AVDD, the conversion result is 3FFH. 3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (The values in the diagram are TYP. values; therefore, they are not assured.) 20kΩ Analog input pin 30pF ( input capacitance included ) 40 10pF µPD78P324, 78P324(A) (3) µPD78P324(A1) Electrical Specifications (1/9) Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Rating Unit –0.5 to +7.0 V –0.5 to VDD +0.5 V VPP –0.5 to +13.5 V AVSS –0.5 to +0.5 V –0.5 to VDD +0.5 V –0.5 to VDD +0.5 V All output pins 4.0 mA Total of all output pins 90 mA All output pins –1.0 mA Total of all output pins –20 mA Condition VDD AVDD Supply voltage Input voltage VI Output voltage VO Low-level output current IOL High-level output current Analog input voltage A/D converter reference input voltage Notes 1, 2 IOH VIAN AVREF Notes 2, 3 AVDD > VDD –0.5 to VDD +0.5 VDD ≥ AVDD –0.5 to AVDD +0.5 AVDD > VDD –0.5 to VDD +0.5 VDD ≥ AVDD –0.5 to AVDD +0.5 V V Operating ambient temperature TA –40 to +110 °C Storage temperature Tstg –65 to +150 °C Notes 1. Except P70/AN0-P77/AN7. 2. The overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application is excluded. 3. P70/AN0-P77/AN7 pins. Caution If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding these ratings. 41 µPD78P324, 78P324(A) (3) µPD78P324(A1) Electrical Specifications (2/9) Permissible Pin Injection Current Characteristics in Overvoltage Application (TA = –40 to +110 °C, VDD = +5 V ±10%, VSS = 0 V) Parameter Symbol Input ports other than ANn (n = 0-7) IIJH1 Positive injection current (VIN > VDD) TYP. MAX. Unit Peak value 10 mA Mean value 0.5 mA Peak value 3 mA Mean value 1 mA Peak value 100 mA Mean value 5 mA Peak value –4 mA Mean value –0.4 mA Peak value –4 mA Mean value –0.3 mA Peak value –40 mA Mean value –3 mA 1 pin IIJH2 IIJH ANn (n = 0-7) Total of all input pins Input ports other than ANn (n = 0-7) IIJL1 1 pin Negative injection current (VIN < VSS) IIJL2 IIJL Cautions MIN. Condition ANn (n = 0-7) Total of all input pins 1. When the injection current has run into the analog input pin (ANn: n = 0-7), the A/D conversion result of the analog input contiguous to the current injection pin has the value of the standard in which the injection current is not running plus ±2LSB. 2. The mean value (absolute value) of the pin injected current is as follows: Mean value = ((1/T) ∫ T | i(t) | 3/2 dt)2/3 0 In this, i(t) refers to the pin injected current. The maximum value of |i(t)| is the peak value. Recommended Operating Range Oscillation Frequency TA VDD 8MHz ≤ fXX ≤ 12.5 MHz –40 to +110 °C +5.0 V ±10 % Capacitance (TA = 25 °C, VSS = VDD = 0 V) Parameter Input capacitance Symbol CI Output capacitance CO I/O cpapacitance CIO 42 Condition f = 1 MHz; 0 V except measured pins MIN. TUP. MAX. Unit 10 pF 20 pF 20 pF µPD78P324, 78P324(A) (3) µPD78P324(A1) Electrical Specifications (3/9) Oscillator Characteristics (TA = –40 to +110 °C, VDD = +5 V ±10 %, VSS = 0 V) Oscillator Recommended Circuit X2 Ceramic oscillator or crystal oscillator X1 C2 MAX. Unit Oscillation frequency (fXX) 8 12.5 MHz X1 input frequency (fX) 8 12.5 MHz X1 input rise time, fall time (tXR, tXF) 0 20 ns X1 input high-/low-level width (tWXH, tWXL) 46 100 ns X2 HCMOS inverter or External clock X1 X2 No connection required HCMOS inverter Caution MIN. VSS C1 X1 Parameter When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. • Make the wiring as short as possible. • Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. • Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. • Do not fetch signals from the oscillation circuit. 43 µPD78P324, 78P324(A) (3) µPD78P324(A1) Electrical Specifications (4/9) DC Characteristics (TA = –40 to +110 °C, VDD = +5 V ±10 %, VSS = 0 V) Parameter Low-level input voltage Symbol Condition VIL MIN. TYP. 0 MAX. Unit 0.8 V VIH1 Note 1 2.2 VIH2 Note 2 0.8 VDD Low-level output voltage VOL IOL = 2.0mA High-level output voltage VOH IOH = –400µA Input leakage current ILI Note 3 0 V ≤ VI ≤ VDD ±10 µA Analog pin input leakage current ILIAN Note 4 0 V ≤ VIAN ≤ AVREF ±2 µA Output leakage current ILO ±10 µA High-level input voltage V 0.45 VDD–1.0 V V 0 V ≤ VO ≤ VDD IDD1 Operation mode 65 87 mA IDD2 HALT mode 25 48 mA VDDDR STOP mode IDDDR STOP mode VDD supply current Data retention voltage Data retention current 2.5 V VDDDR = 2.5 V 2 100 µA VDDDR=5.0 V±10% 10 1000 µA Notes 1. Pins other than pins in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins. 3. Pins except P20/NMI, EA/VPP, X1, X2 4. When not sampling the analog input 44 µPD78P324, 78P324(A) (3) µPD78P324(A1) Electrical Specifications (5/9) AC Characteristics (TA = –40 to +110 °C, VDD = +5 V ±10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter Symbol Condition MIN. MAX. Unit 250 ns System clock cycle time tCYK 160 Address setup time (vs. ASTB ↓) tSAST 40 ns Address hold time (vs. ASTB ↓) tHSTA 50 ns Address → RD ↓ delay time tDAR 120 ns RD ↓ → address float time tFRA 10 ns Address → data input time tDAID 310 ns RD ↓ → data input time tDRID 165 ns ASTB ↓ → RD ↓ delay time tDSTR 60 ns Data hold time (vs. RD ↑) tHRID 0 ns RD ↑ → address active time tDRA 68 ns RD low-level width tWRL 191 ns ASTB high-level width tWSTH 55 ns Address → WR ↓ delay time tDAW 120 ns ASTB ↓ → data output time tDSTOD 120 ns WR ↓ → data output time tDWOD 40 ns ASTB ↓ → WR ↓ delay time tDSTW 60 ns Data setup time (vs. WR ↑) tSODW 191 ns Data hold time (vs. WR ↑) tHWOD 50 ns WR ↑ → ASTB ↑ delay time tDWST 60 ns WR low-level width tWWL 195 ns 45 µPD78P324, 78P324(A) (3) µPD78P324(A1) Electrical Specifications (6/9) tCYK-dependent Bus Timing Definition Remarks Symbol Calculation formula MIN./MAX. Unit tSAST 0.5T–40 MIN. ns tHSTA 0.5T–30 MIN. ns tDAR T–40 MIN. ns tDAID (2.5+n) T–90 MAX. ns tDRID (1.5+n) T–75 MAX. ns tDSTR 0.5T–20 MIN. ns tDRA 0.5T–12 MIN. ns tWRL (1.5+n) T–49 MIN. ns tWSTH 0.5T–25 MIN. ns tDAW T–40 MIN. ns tDSTOD 0.5T+40 MAX. ns tDSTW 0.5T–20 MIN. ns tSODW 1.5T–49 MIN. ns tHWOD 0.5T–30 MIN. ns tDWST 0.5T–20 MIN. ns tWWL (1.5+n) T–45 MIN. ns 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. Among the parameters for bus timing, only those listed in this table are dependent on tCYK. 46 µPD78P324, 78P324(A) (3) µPD78P324(A1) Electrical Specifications (7/9) Serial Operation (TA = –40 to +110 °C, VDD = +5 V ±10 %, VSS = 0 V) Parameter Symbol Condition SCK output Serial clock cycle time SCK output Unit Internal divide-by-eight 1280 µs External clock 1280 µs Internal divide-by-eight 560 ns External clock 560 ns Internal divide-by-eight 560 ns External clock 560 ns tWSKL SCK input SCK output Serial clock high-level width MAX. tCYSK SCK input Serial clock low-level width MIN. tWSKH SCK input SI setup time (vs. SCK ↑) tSRXSK 80 ns SI hold time (vs. SCK ↑) tHSKRX 80 ns SCK ↓ → SO delay time tDSKTX R = 1 kΩ , C = 100pF 210 ns tCYK-dependent Serial Operation Symbol Condition SCK output Calculation Formula MIN./MAX. Unit Internal divide-by-eight 8T MIN. ns External clock 8T MIN. ns Internal divide-by-eight 4T–80 MIN. ns External clock 4T–80 MIN. ns Internal divide-by-eight 4T–80 MIN. ns External clock 4T–80 MIN. ns tCYSK SCK input SCK output tWSKL SCK input SCK output tWSKH SCK input Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK. 47 µPD78P324, 78P324(A) (3) µPD78P324(A1) Electrical Specifications (8/9) Other Operations (TA = –40 to +110 °C, VDD = +5 V ±10 %, VDD = 0 V) Parameter Symbol Condition NMI high-/low-level width tWNIH, tWNIL Analog noises removed INTP0 high-/low-level width MIN. MAX. Unit 4 µs tWIOH, tWIOL 1280 ns INTP1 high-/low-level width tWI1H, tWI1L 1280 ns INTP2 high-/low-level width tWI2H, tWI2L 1280 ns INTP3 high-/low-level width tWI3H, tWI3L 1280 ns INTP4 high-/low-level width tWI4H, tWI4L 1280 ns INTP5 high-/low-level width tWI5H, tWI5L 1280 ns INTP6 high-/low-level width tWI6H, tWI6L 1280 ns RESET high-/low-level width tWRSH, tWRSL 3.5 µs TI high-/low-level width tWTIH, tWTIL 1280 ns tRVD, tFVD 200 µs VDD rise/fall time Analog noises removed Other tCYK-dependent Operations Remarks Symbol Calculation formula MIN./MAX. Unit tWIOH 8T MIN. ns tWIOL 8T MIN. ns tWI1H 8T MIN. ns tWI1L 8T MIN. ns tWI2H 8T MIN. ns tWI2L 8T MIN. ns tWI3H 8T MIN. ns tWI3L 8T MIN. ns tWI4H 8T MIN. ns tWI4L 8T MIN. ns tWI5H 8T MIN. ns tWI5L 8T MIN. ns tWI6H 8T MIN. ns tWI6L 8T MIN. ns tWTIH 8T MIN. ns tWTIL 8T MIN. ns 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Only the parameters listed in this table depend on tCYK. 48 µPD78P324, 78P324(A) (3) µPD78P324(A1) Electrical Specifications (9/9) AC Timing Test Point VDD 0V 0.8VDD or 2.2V 0.8VDD or 2.2V Test point 0.8V 0.8V A/D Converter Characteristics (TA = –40 to +110 °C, VDD = +5 V ±10 %, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD) Parameter Symbol MIN. Condition Resolution TYP. MAX. 10 Total errorNote 1 Unit bit 4.5 V ≤ AVREF ≤ AVDD ±0.4 %FSR 3.5 V ≤ AVREF ≤ AVDD ±0.7 %FSR ±1/2 LSB Quantization error Conversion time tCONV 144 tCYK Sampling time tSAMP 24 tCYK Zero-scale errorNote 1 Full-scale errorNote 1 Non-linear errorNote 1 Analog input voltageNote 2 VIAN Analog input impedance RAN 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB AVDD V 0 When not sampled 10 When sampled Reference voltage AVREF AVREF current AIREF AVDD supply current AIDD Operation mode A/D converter data retention current AIDDDR STOP mode MΩ Note 3 3.4 AVDD V 1.0 3.0 mA 2.0 6.0 mA AVDDDR = 2.5 V 2 100 µA AVDDDR=5 V±10% 10 1000 µA Notes 1. Quantization error excluded. 2. When VIAN = 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits. When AVREF ≤ VIAN ≤ AVDD, the conversion result is 3FFH. 3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (The values in the diagram are TYP. values; therefore, they are not assured.) 20kΩ Analog input pin 30pF 10pF ( input capacitance included ) 49 µPD78P324, 78P324(A) (4) µPD78P324(A2) Electrical Specifications (1/9) Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Rating Unit –0.5 to +7.0 V –0.5 to VDD +0.5 V VPP –0.5 to +13.5 V AVSS –0.5 to +0.5 V –0.5 to VDD +0.5 V –0.5 to VDD +0.5 V All output pins 4.0 mA Total of all output pins 90 mA All output pins –1.0 mA Total of all output pins –20 mA Condition VDD AVDD Supply voltage Input voltage VI Output voltage VO Low-level output current IOL High-level output current Analog input voltage A/D converter reference input voltage Notes 1, 2 IOH VIAN AVREF Notes 2, 3 AVDD > VDD –0.5 to VDD +0.5 VDD ≥ AVDD –0.5 to AVDD +0.5 AVDD > VDD –0.5 to VDD +0.5 VDD ≥ AVDD –0.5 to AVDD +0.5 V V Operating ambient temperature TA –40 to +125 °C Storage temperature Tstg –65 to +150 °C Notes 1. Except P70/AN0-P77/AN7. 2. The overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application is excluded. 3. P70/AN0-P77/AN7 pins. Caution If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding these ratings. 50 µPD78P324, 78P324(A) (4) µPD78P324(A2) Electrical Specifications (2/9) Permissible Pin Injection Current Characteristics in Overvoltage Application (TA = –40 to +125 °C, VDD = +5 V ±10%, VSS = 0 V) Parameter Symbol Input ports other than ANn (n = 0-7) IIJH1 Positive injection current (VIN > VDD) MIN. MAX. Unit Peak value 10 mA Mean value 0.5 mA Peak value 3 mA Mean value 1 mA Peak value 100 mA Mean value 5 mA Peak value –4 mA Mean value –0.4 mA Peak value –4 mA Mean value –0.3 mA Peak value –40 mA Mean value –3 mA Condition TYP. 1 pin IIJH2 IIJH ANn (n = 0-7) Total of all input pins Input ports other than ANn (n = 0-7) IIJL1 1 pin Negative injection current (VIN < VSS) IIJL2 IIJL ANn (n = 0-7) Total of all input pins Cautions. 1. When the injection current has run into the analog input pin (ANn: n = 0-7), the A/D conversion result of the analog input contiguous to the current injection pin has the value of the standard in which the injection current is not running plus ±2LSB. 2. The mean value (absolute value) of the pin injected current is as follows: Mean value = ((1/T) ∫ T | i(t) | 3/2 dt)2/3 0 In this, i(t) refers to the pin injected current. The maximum value of |i(t)| is the peak value. Recommended Operating Range Oscillation Frequency TA VDD 8MHz ≤ fXX ≤ 12.5 MHz –40 to +125 °C +5.0 V ±10 % Capacitance (TA = 25 °C, VSS = VDD = 0 V) Parameter Input capacitance Symbol Condition CI Output capacitance CO I/O capacitance CIO f = 1 MHz; 0 V except measured pins MIN. TUP. MAX. Unit 10 pF 20 pF 20 pF 51 µPD78P324, 78P324(A) (4) µPD78P324(A2) Electrical Specifications (3/9) Oscillator Characteristics (TA = 40 to +125 °C, VDD = +5 V ±10 %, VSS = 0 V) Oscillator Recommended Circuit X2 Ceramic oscillator or crystal oscillator X1 C2 MAX. Unit Oscillation frequency (fXX) 8 12.5 MHz X1 input frequency (fX) 8 12.5 MHz X1 input rise time, fall time (tXR, tXF) 0 20 ns X1 input high-/low-level width (tWXH, tWXL) 46 100 ns X2 HCMOS inverter or External clock X1 X2 No connection required HCMOS inverter Caution MIN. VSS C1 X1 Parameter When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. • Make the wiring as short as possible. • Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. • Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. • Do not fetch signals from the oscillation circuit. 52 µPD78P324, 78P324(A) (4) µPD78P324(A2) Electrical Specifications (4/9) DC Characteristics (TA = –40 to +125 °C, VDD = +5 V ±10 %, VSS = 0 V) Parameter Low-level input voltage Symbol Condition VIL MIN. TYP. 0 MAX. Unit 0.8 V VIH1 Note 1 2.2 VIH2 Note 2 0.8 VDD Low-level output voltage VOL IOL = 2.0mA High-level output voltage VOH IOH = –400µA Input leakage current ILI Note 3 0 V ≤ VI ≤ VDD ±10 µA Analog pin input leakage current ILIAN Note 4 0 V ≤ VIAN ≤ AVREF ±2 µA Output leakage current ILO ±10 µA High-level input voltage V 0.45 VDD–1.0 V V 0 V ≤ VO ≤ VDD IDD1 Operation mode 65 87 mA IDD2 HALT mode 25 48 mA VDDDR STOP mode IDDDR STOP mode VDD supply current Data retention voltage Data retention current 2.5 V VDDDR = 2.5 V 2 100 µA VDDDR=5.0 V±10% 10 1000 µA Notes 1. Pins other than pins in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins. 3. Pins except P20/NMI, EA/VPP, X1, X2 4. When not sampling the analog input 53 µPD78P324, 78P324(A) (4) µPD78P324(A2) Electrical Specifications (5/9) AC Characteristics (TA = –40 to +125 °C, VDD = +5 V ±10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter Symbol Condition MIN. MAX. Unit 250 ns System clock cycle time tCYK 160 Address setup time (vs. ASTB ↓) tSAST 40 ns Address hold time (vs. ASTB ↓) tHSTA 50 ns Address → RD ↓ delay time tDAR 120 ns RD ↓ → address float time tFRA 10 ns Address → data input time tDAID 310 ns RD ↓ → data input time tDRID 165 ns ASTB ↓ → RD ↓ delay time tDSTR 60 ns Data hold time (vs. RD ↑) tHRID 0 ns RD ↑ → address active time tDRA 68 ns RD low-level width tWRL 191 ns ASTB high-level width tWSTH 55 ns Address → WR ↓ delay time tDAW 120 ns ASTB ↓ → data output time tDSTOD 120 ns WR ↓ → data output time tDWOD 40 ns ASTB ↓ → WR ↓ delay time tDSTW 60 ns Data setup time (vs. WR ↑) tSODW 191 ns Data hold time (vs. WR ↑) tHWOD 50 ns WR ↑ → ASTB ↑ delay time tDWST 60 ns WR low-level width tWWL 195 ns 54 µPD78P324, 78P324(A) (4) µPD78P324(A2) Electrical Specifications (6/9) tCYK-dependent Bus Timing Definition Remarks Symbol Calculation formula MIN./MAX. Unit tSAST 0.5T–40 MIN. ns tHSTA 0.5T–30 MIN. ns tDAR T–40 MIN. ns tDAID (2.5+n) T–90 MAX. ns tDRID (1.5+n) T–75 MAX. ns tDSTR 0.5T–20 MIN. ns tDRA 0.5T–12 MIN. ns tWRL (1.5+n) T–49 MIN. ns tWSTH 0.5T–25 MIN. ns tDAW T–40 MIN. ns tDSTOD 0.5T+40 MAX. ns tDSTW 0.5T–20 MIN. ns tSODW 1.5T–49 MIN. ns tHWOD 0.5T–30 MIN. ns tDWST 0.5T–20 MIN. ns tWWL (1.5+n) T–45 MIN. ns 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. Among the parameters for bus timing, only those listed in this table are dependent on tCYK. 55 µPD78P324, 78P324(A) (4) µPD78P324(A2) Electrical Specifications (7/9) Serial Operation (TA = 40 to +125 °C, VDD = +5 V ±10 %, VSS = 0 V) Parameter Symbol Condition SCK output Serial clock cycle time SCK output Unit Internal divide-by-eight 1280 µs External clock 1280 µs Internal divide-by-eight 560 ns External clock 560 ns Internal divide-by-eight 560 ns External clock 560 ns tWSKL SCK input SCK output Serial clock high-level width MAX. tCYSK SCK input Serial clock low-level width MIN. tWSKH SCK input SI setup time (vs. SCK ↑) tSRXSK 80 ns SI hold time (vs. SCK ↑) tHSKRX 80 ns SCK ↓ → SO delay time tDSKTX R = 1 kΩ , C = 100pF 210 ns tCYK-dependent Serial Operation Symbol Condition SCK output Calculation Formula MIN./MAX. Unit Internal divide-by-eight 8T MIN. ns External clock 8T MIN. ns Internal divide-by-eight 4T–80 MIN. ns External clock 4T–80 MIN. ns Internal divide-by-eight 4T–80 MIN. ns External clock 4T–80 MIN. ns tCYSK SCK input SCK output tWSKL SCK input SCK output tWSKH SCK input Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK. 56 µPD78P324, 78P324(A) (4) µPD78P324(A2) Electrical Specifications (8/9) Other Operations (TA = –40 to +125 °C, VDD = +5 V ±10 %, VDD = 0 V) Parameter Symbol Condition NMI high-/low-level width tWNIH, tWNIL Analog noises removed INTP0 high-/low-level width MIN. MAX. Unit 4 µs tWIOH, tWIOL 1280 ns INTP1 high-/low-level width tWI1H, tWI1L 1280 ns INTP2 high-/low-level width tWI2H, tWI2L 1280 ns INTP3 high-/low-level width tWI3H, tWI3L 1280 ns INTP4 high-/low-level width tWI4H, tWI4L 1280 ns INTP5 high-/low-level width tWI5H, tWI5L 1280 ns INTP6 high-/low-level width tWI6H, tWI6L 1280 ns RESET high-/low-level width tWRSH, tWRSL 3.5 µs TI high-/low-level width tWTIH, tWTIL 1280 ns tRVD, tFVD 200 µs VDD rise/fall time Analog noises removed Other tCYK-dependent Operations Remarks Symbol Calculation formula MIN./MAX. Unit tWIOH 8T MIN. ns tWIOL 8T MIN. ns tWI1H 8T MIN. ns tWI1L 8T MIN. ns tWI2H 8T MIN. ns tWI2L 8T MIN. ns tWI3H 8T MIN. ns tWI3L 8T MIN. ns tWI4H 8T MIN. ns tWI4L 8T MIN. ns tWI5H 8T MIN. ns tWI5L 8T MIN. ns tWI6H 8T MIN. ns tWI6L 8T MIN. ns tWTIH 8T MIN. ns tWTIL 8T MIN. ns 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Only the parameters listed in this table depend on tCYK. 57 µPD78P324, 78P324(A) (4) µPD78P324(A2) Electrical Specifications (9/9) AC Timing Test Point VDD 0V 0.8VDD or 2.2V 0.8VDD or 2.2V Test point 0.8V 0.8V A/D Converter Characteristics (TA = –40 to +125 °C, VDD = +5 V ±10 %, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD) Parameter Symbol Condition MIN. Resolution TYP. MAX. 10 Total errorNote 1 Unit bit 4.5 V ≤ AVREF ≤ AVDD ±0.4 %FSR 3.5 V ≤ AVREF ≤ AVDD ±0.7 %FSR ±1/2 LSB Quantization error Conversion time tCONV 144 tCYK Sampling time tSAMP 24 tCYK Zero-scale errorNote 1 Full-scale errorNote 1 Non-linear errorNote 1 Analog input voltageNote 2 VIAN Analog input impedance RAN 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB 4.5 V ≤ AVREF ≤ AVDD ±1.5 ±2.5 LSB 3.4 V ≤ AVREF ≤ AVDD ±1.5 ±4.5 LSB AVDD V 0 When not sampled 10 When sampled Reference voltage AVREF AVREF current AIREF AVDD supply current AIDD Operation mode A/D converter data retention current AIDDDR STOP mode MΩ Note 3 3.4 AVDD V 1.0 3.0 mA 2.0 6.0 mA AVDDDR = 2.5 V 2 100 µA AVDDDR=5 V±10% 10 1000 µA Notes 1. Quantization error excluded. 2. When VIAN = 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits. When AVREF ≤ VIAN ≤ AVDD, the conversion result is 3FFH. 3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (The values in the diagram are TYP. values; therefore, they are not assured.) 20kΩ Analog input pin 30pF ( input capacitance included ) 58 10pF µPD78P324, 78P324(A) Non-serial Read Operation tCYK (CLK) P50-P57 (Output) Upper address Upper address tDAID P40-P47 (Input/Output) Hi-Z tSAST Lower address(Output) Hi-Z Hi-Z Data (Input) tWSTH Hi-Z Lower address(Output) tHRID ASTB (Output) tHSTA tFRA RD (Output) tDSTR tDRID tDRA tDAR tWRL Non-serial Write Operation (CLK) P50-P57 (Output) Upper address Upper address tSAST P40-P47 (Input/Output) Lower address(Output) Data (Output) Undfined tWSTH Lower address(Output) tHWOD ASTB (Output) tDWST tHSTA tDSTOD WR (Output) tDSTW tSODW tDWOD tDAW tWWL 59 µPD78P324, 78P324(A) Serial Operation tCYSK tWSKH tWSKL SCK tDSKTX SO SI tSRXSK tHSKRX Interrupt Input Timing tWNIH tWNIL 0.8VDD NMI 0.8V tWInH 1NTPn Remark 60 n = 0-6 tWInL µPD78P324, 78P324(A) Reset Input Timing tWRSH tWRSL 0.8VDD 0.8V RESET TI Pin Input Timing tWTIH tWTIL TI Data Retention Timing 90% VDD 10% tFVD VDDDR tRVD 61 µPD78P324, 78P324(A) DC Programming Characteristics (TA = 25 ±5 °C, VSS = 0 V) Parameter Symbol SymbolNote 1 Condition MIN. TYP. MAX. Unit High-level input voltage VIH VIH 2.4 VDDP+0.3 V Low-level input voltage VIL VIL –0.3 0.8 V Input leakage current ILI ILI 0 ≤ VI ≤ VDDPNote 2 ±10 µA High-level output voltage VOH VOH IOH = –400 µA Low-level output voltage VOL VOL IOL = 2.0 µA 0.45 V Input current IA9 — A9(P20/NMI) pin, 0 ≤ VO ≤ VDDP ±10 µA Output leakage current ILO — 0 ≤VO ≤ VDDP, OE = VIH ±10 µA VDDP supply voltage VDDP VPP supply voltage VPP VPP supply current IDD IPP Program memory Write mode 6.25 65 6.75 V Program memory Read mode 4.5 5.0 5.5 V Program memory Write mode 12.2 12.5 12.8 V VPP VPP = VDDP V Program memory Write mode 30 mA Program memory Read mode 50 mA Program memory Write mode CE = PGM 50 mA 100 µA IDD IPP Program memory Read mode VPP = VDD Notes 1. Refers to the symbol of the corresponding µPD27C1001A. 2. VDDP refers to the VDD pin in programming. 62 V VCC Program memory Read mode VDDP supply current 2.4 1 µPD78P324, 78P324(A) AC Programming Characteristics (TA = 25±5 °C, VSS = 0 V) In PROM Write Mode Parameter SymbolNote1 Condition MIN. TYP. MAX. Unit Address setup time tAS 2 µs CE set time tCES 2 µs Input data setup time tDS 2 µs Address hold time tAH 2 µs Input data hold time tDH 2 µs Output data hold time tDF 0 VPP setup time tVPS 2 µs VDDP setup time tVDSNote 2 2 µs Initial program pulse width tPW 0.095 OE set time tOES 2 OE → valid data delay time tOE 130 0.1 0.105 ns ms µs 200 ns MAX. Unit Notes 1. Corresponds to the symbol of µPD27C1001A (tVDS excluded). 2. The symbol of tVDS on µPD27C1001A is tVCS. In PROM Read Mode Parameter SymbolNote1 Condition MIN. TYP. Address → data output time tACC CE = OE = VIL 2 µs CE ↓ → data output time tCE OE = VIL 1 µs OE ↓ → data output time tOE CE = VIL 1 µs Data hold time (vs. OE ↑, CE ↑)Note 2 tDF CE = VIL or OE = VIL 0 130 ns Data hold time (vs. address) tOH CE = OE = VIL 0 ns Notes 1. Corresponds to the symbol of µPD27C1001A. 2. tDF refers to the time when either OE or CE became VIH first. 63 µPD78P324, 78P324(A) PROM Write Mode Timing Program Program verify A0-A16 tDF tAS D0-D7 Hi-Z Hi-Z Data input tDS Hi-Z Data output tAH tDH VPP VPP VDDP tVPS VDDP + 1.5 VDDP VDDP tVDS VIH CE VIL tCES tPW VIH PGM VIL tOES tOE VIH OE VIL Cautions 1. Ensure to apply VDDP before VPP, and disconnect it after VPP. 2. Ensure that VPP does not exceed +13.5 V even when the overshoot is included. 3. Taking out or putting in while +12.5 V is applied to VPP may cause adverse effects on the reliability. PROM Read Mode Timing Vailed address A0-A16 CE OE Note 1 D0-D7 tACC Hi-Z tOE Note 1 tDF Note 2 tOH Data output Hi-Z Notes 1. To read within the range of tACC, please make sure that the delay time from CE’s falling edge of the OE input is up to tACC-tOE. 2. tDF refers to the time when either OE or CE became VIH first. 64 µPD78P324, 78P324(A) PACKAGE DRAWINGS 74-Pin Plastic QFP(■ ■ 20) A F2 B 56 57 38 37 F1 Q R S D C detail of lead end 74 19 18 1 G1 G2 H I M J K M P 8. N L NOTE ITEM Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. Remark The package and material of the ES product MILLIMETERS INCHES A 23.2±0.4 0.913 +0.017 –0.016 B 20.0±0.2 0.787 +0.009 –0.008 C 20.0±0.2 0.787 +0.009 –0.008 D 23.2±0.4 0.913 +0.017 –0.016 are equivalent to those for mass production. F1 2.0 0.079 F2 1.0 0.039 G1 2.0 0.079 G2 1.0 0.039 H 0.40±0.10 0.016 +0.004 –0.005 I 0.20 0.008 J 1.0 (T.P.) 0.039 (T.P.) K 1.6±0.2 L 0.8±0.2 0.063±0.008 0.031 +0.009 –0.008 M 0.15+0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P Q 3.7 0.146 R 0.1±0.1 5°±5° 0.004±0.004 5°±5° S 4.0 MAX. 0.158 MAX. S74GJ-100-5BJ-3 65 µPD78P324, 78P324(A) 68 PIN PLASTIC QFJ ( 950 mil) A B C D F E H G U J 68 1 I T Q K M N M P P68L-50A1-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. Remark The package and material of the ES product are equivalent to those for mass production. 66 ITEM MILLIMETERS INCHES A 25.2 ± 0.2 0.992 ± 0.008 B 24.20 0.953 C 24.20 0.953 D 25.2 ± 0.2 0.992 ± 0.008 E 1.94 ± 0.15 0.076+0.007 –0.006 F 0.6 0.024 G 4.4 ± 0.2 0.173+0.009 –0.008 H 2.8 ± 0.2 0.110+0.009 –0.008 I 0.9 MIN. 0.035 MIN. J 3.4 0.134 K 1.27 (T.P.) 0.050 (T.P.) M 0.40 ± 1.0 0.016+0.004 –0.005 N 0.12 0.005 P 23.12 ± 0.20 0.910+0.009 –0.008 Q 0.15 0.006 T R 0.8 R 0.031 U 0.20 +0.10 –0.05 0.008+0.004 –0.002 µPD78P324, 78P324(A) 74 PIN CERAMIC WQFN A K Q B D C T W S 74 Y H U I 1 M R G E F J X74KW-100A-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. Remark The package and material of the ES product are equivalent to those for mass production. ITEM MILLIMETERS INCHES A 20.0 ± 0.4 0.787+0.017 –0.016 B 18.0 0.709 C 18.0 0.709 D 20.0 ± 0.4 0.787+0.017 –0.016 E 1.94 0.076 F 2.14 0.084 G 4.0 MAX. 0.158 MAX. H 0.51 ± 0.10 0.020 ± 0.004 I 0.10 0.004 J 1.0 (T.P.) 0.039 (T.P.) K 1.0 ± 0.2 0.039 –0.008 Q C 0.3 C 0.012 R 2.0 0.079 S 2.0 0.079 T R 2.0 R 0.079 U 10.0 0.394 W 0.7 ± 0.2 0.028 –0.009 Y C 1.5 C 0.059 +0.009 +0.008 67 µPD78P324, 78P324(A) 68 PIN CERAMIC WQFN A L K B Q P 68 1 S D C U T Y E G F H I M J R X68KW-50A-1 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. Remark 68 ITEM MILLIMETERS INCHES A 24.13 ± 0.4 0.950 ± 0.016 B 21.5 0.846 C 21.5 0.846 ES product are equivalent to those D 24.13 ± 0.4 0.950 ± 0.016 for mass production. E 1.65 0.065 F 2.03 0.080 G 3.50 MAX. 0.138 MAX. H 0.64 ± 0.10 0.025+0.005 –0.004 I 0.12 0.005 J 1.27 (T.P.) 0.05 (T.P.) K 1.27 ± 0.2 0.05 ± 0.008 L 2.16 ± 0.2 0.085 ± 0.008 P R 0.2 R 0.008 Q C 1.02 C 0.04 R 1.905 0.075 S 1.905 0.075 T R 3.0 R 0.118 U 12.0 0.472 Y C 0.5 C 0.020 The package and material of the µPD78P324, 78P324(A) 9. RECOMMENDED SOLDERING CONDITIONS Please solder the package of this product under the conditions recommended as follows. For details of the recommended conditions for soldering, please refer to the information document “Semiconductor Device Mounting Technology Manual” (IEI-1207). For soldering methods and conditions other than those recommended below, please contact NEC sales personnel. Table 9-1. Soldering Conditions for Surface-Mount Type (1) µPD78P324GJ-5BJ : 74-pin plastic QFP (20 x 20 mm) µPD78P324LP : 68-pin plastic QFJ (■ ■ 950 mil) µPD78P324LP(A) : 68-pin plastic QFJ (■ ■ 950 mil) µPD78P324LP(A1) : 68-pin plastic QFJ (■ ■ 950 mil) µPD78P324LP(A2) : 68-pin plastic QFJ (■ ■ 950 mil) Soldering Method Soldering Condition Recommended Condition Symbol Infrared reflow Package peak temperature : 230 °C; time : within 30 secs (210 °C or more); count: once; day limit : 7 daysNote (hereafter, pre-baked for 36 hrs at 125 °C) IR30-367-1 VPS Package peak temperature : 215 °C; time : within 40 secs (200 °C or more); count: once; day limit : 7 daysNote (hereafter, pre-baked for 36 hrs at 125 °C) VP15-367-1 Wave soldering Solder bath temperature: no more than 260 °C; time : within 10 secs; count: once; preheating temperature : 120 °C max. (package surface temperature); day limit : 7 daysNote (hereafter, pre-baked for 36 hours at 125 °C) WS60-367-1 Pin temperature : no more than 300 °C; time : within 3 secs (per device side) — Pin part heating Note Refers to the number of days for storage after the dry pack is opened. The storage conditions are 25 °C and no more than 65 %RH. Caution Avoid using multiple soldering methods at the same time (except the pin part heating method). 69 µPD78P324, 78P324(A) Table 9-2. Soldering Conditions for Surface-Mount Type (2) µPD78P324GJ(A)-5BJ : 74-pin plastic QFP (20 x 20 mm) µPD78P324GJ(A1)-5BJ : 74-pin plastic QFP (20 x 20 mm) µPD78P324GJ(A2)-5BJ : 74-pin plastic QFP (20 x 20 mm) Soldering Method Infrared reflow VPS Wave soldering Pin part heating Note Soldering Condition Package peak temperature: 235 °C; time: within 30 secs (210 °C or more); count: twice; day limit: 7 daysNote (hereafter, pre-baked for 36 hrs at 125 °C) <Caution> (1) The second reflow should be started after the temperature of the device which would have been changed by the first reflow has returned to normal. (2) Please avoid flux water washing after the first reflow. Recommended Condition Symbol IR35-367-2 Package peak temperature: 215 °C; time: within 40 secs (200 °C or more); count: within twice; day limit: 7 daysNote (hereafter, pre-baked for 36 hrs at 125 °C) <Caution> (1) The second reflow should be started after the temperature of the device which would have been changed by the first reflow has returned to normal. (2) Please avoid flux water washing after the first reflow. VP15-367-2 Solder bath temperature: no more than 260 °C; time: within 10 secs; count: once; preheating temperature: up to 120 °C (package surface temperature); day limit: 7 daysNote (hereafter, pre-baked for 36 hours at 125 °C) WS60-367-1 Pin temperature: no more than 300 °C; time: within 3 secs (per device side) — Refers to the number of days for storage after the dry pack is opened. The storage conditions are 25 °C and no more than 65 %RH. Caution 70 Avoid using two or more soldering methods at the same time (except the pin part heating method). µPD78P324, 78P324(A) APPENDIX A. CONVERSION SOCKET PACKAGE DRAWING AND RECOMMENDED SUBSTRATE INSTALLATION PATTERN Figure A-1. Conversion Socket (EV-9200G-74) Package Drawing (Reference) A M N O L K T J C D S R F Q B E EV-9200G-74 C 1.5 1 P No.1 pin index EV-9200G-74-G0 ITEM MILLIMETERS INCHES A 25.0 0.984 G B 20.35 0.801 H C 20.35 0.801 I D 25.0 0.984 E 4-C 2.8 4-C 0.11 F 1.0 0.039 G 11.0 0.433 H 22.0 0.866 I 24.7 0.972 J 5.0 0.197 K 22.0 0.866 L 24.7 0.972 M 8.0 0.315 N 7.8 0.307 O 2.5 0.098 P 2.0 0.079 Q 1.35 0.053 R 0.35 ± 0.1 0.014+0.004 –0.005 S φ 2.3 φ 0.091 T φ 1.5 φ 0.059 71 µPD78P324, 78P324(A) Figure A-2. Recommended Pattern for Conversion Socket (EV-9200G-74) Substrate Installation (Reference) G H D E F J I K C B A EV-9200G-74-P0 ITEM MILLIMETERS A 25.7 1.012 B 21.0 0.827 C +0.002 1.0±0.02 × 18=18.0±0.05 0.039+0.002 –0.001 × 0.709=0.709 –0.003 D +0.002 1.0±0.02 × 18=18.0±0.05 0.039+0.002 –0.001 × 0.709=0.709 –0.003 E 21.0 0.827 F 25.7 1.012 G 11.00 ± 0.08 0.433+0.004 –0.003 H 5.00 ± 0.08 0.197+0.003 –0.004 I 0.6 ± 0.02 0.024+0.001 –0.002 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution 72 INCHES Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207). µPD78P324, 78P324(A) APPENDIX B. TOOLS B.1 DEVELOPMENT TOOLS The following development tools have been made available for development of the system using the µPD78P324. Language Processors 78K/III series relocatable assembler (RA78K/III) Refers to the relocatable assembler which can be used commonly for the 78K/III series. Equipped with the macro function, the relocatable assembler is aimed at improved development efficiency. The assembler is also accompanied by the structured assembler which can describe the program control structure explicitly, thus making it possible to improve the productivity and the maintainability of the program. Host machine Part number OS PC-9800 series 78K/III series C compiler (CC78K/III) Supply medium 3.5-inch 2HD µS5A13RA78K3 5-inch 2HD µS5A10RA78K3 3.5-inch 2HC µS7B13RA78K3 5-inch 2HC µS7B10RA78K3 MS-DOSTM IBM PC/ATTM and its compatible machine PC DOSTM HP9000 series 300TM HP-UXTM SPARCstationTM SunOSTM Cartridge tape (QIC-24) µS3K15RA78K3 Refers to the C compiler which can be commonly used in the 78K/III series. This compiler is a program converting the programs written in the C language to those object codes which are executable by microcomputers. When using this compiler, the 78K/III series relocatable assembler (RA78K/III) is required. Host machine Part number OS PC-9800 series Remark µS3H15RA78K3 Supply medium 3.5-inch 2HD µS5A13CC78K3 5-inch 2HD µS5A10CC78K3 3.5-inch 2HC µS7B13CC78K3 5-inch 2HC µS7B10CC78K3 MS-DOS IBM PC/AT and its compatible machine PC DOS HP9000 series 300 HP-UX SPARCstation SunOS Cartridge tape (QIC-24) µS3H15CC78K3 µS3K15CC78K3 Relocatable assembler and C compiler operations are assured only on the host machine and the OS above. 73 µPD78P324, 78P324(A) PROM Write Tools Hardware PG-1500 This PROM programmer is capable of programming by manipulating a PROMincorporated single-chip microcomputer from a stand-alone or host machine after connecting the accompanying board and the separately available programmer adapter. It can also program representative PROMs ranging from 256 Kbits to 4 Mbits. UNISITE 2900 3900Note These are PROM programmers made by Data I/O Japan. PA-78P324GJ These are the PROM programmer adapters for writing programs into the µPD78P324 on general-purpose PROM programmer such as PG-1500. PA-78P324GJ: for µPD78P324GJ PA-78P324LP: for µPD78P324LP PA-78P324KC: for µPD78P324KC PA-78P324KD: for µPD78P324KD PA-78P324LP PA-78P324KC PA-78P324KD Software PG-1500 controller A PG-1500 and a host machine are connected with the serial interface or the parallel interface to control the PG-1500 on the host machine. Host machine Part number OS PC-9800 series IBM PC/AT and its compatible machine Note 3.5-inch 2HD µS5A13PG1500 5-inch 2HD µS5A10PG1500 3.5-inch 2HC µS7B13PG1500 5-inch 2HC µS7B10PG1500 MS-DOS PC DOS Being evaluated. Remark 74 Supply medium The PG-1500 controller operation is assured only on the host machine and the OS above. µPD78P324, 78P324(A) Debugging Tools Hardware IE-78327-R IE-78320-RNote EP-78320GJ-R EP-78320L-R IE-78327-R control program (IE controller) These are the in-circuit emulators which can be used for the development and debugging of application systems. Debugging is performed by connecting them to a host machine. The IE-78327-R can be used commonly for both the µPD78322 subseries and the µPD78328 subseries. The IE-78320-R can be used for the µPD78322 subseries. These are the emulation probes for connecting the IE-78327-R or IE-78320-R to a target system. EP-78320GJ-R: for 74-pin plastic QFP EP-78320L-R: for 68-pin plastic QFJ This program is for controlling the IE-78327-R from a host machine. It can execute commands automatically, thus enabling more efficient debugging. Host machine Part number OS PC-9800 series IBM PC/AT and its compatible machine Software IE-78320-R control programNote (IE controller) Supply medium 3.5-inch 2HD µS5A13IE78327 5-inch 2HD µS5A10IE78327 3.5-inch 2HC µS7B13IE78327 5-inch 2HC µS7B10IE78327 MS-DOS PC DOS This program is for controlling the IE-78320-R from a host machine. It can execute commands automatically, thus enabling more efficient debugging. Host machine Part number OS PC-9800 series IBM PC/AT and its compatible machine Remarks Supply medium 3.5-inch 2HD µS5A13IE78320 5-inch 2HD µS5A10IE78320 5-inch 2HC µS7B10IE78320 MS-DOS PC DOS 1. The operation of each software is assured only on the host machine and the OS above. 2. µPD78322 subseries: µPD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1), 78320(A2), 78322(A), 78322(A1), 78322(A2), 78323(A), 78323(A1), 78323(A2), 78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1), 78P324(A2) µPD78328 subseries: µPD78327, 78328, 78P328, 78327(A), 78328(A) Note The existing product IE-78320-R is a maintenance product. If you are going to newly purchase an in-circuit emulator, please use the alternative product IE-78327-R. 75 µPD78P324, 78P324(A) Development Tool Configurations Host machine PC-9800 series IBM PC/AT or its compatible machine RS-232-C Emulation probes IE-78327-R in-circuit emulator Software RS-232-C EP-78320GJ-R EP-78320L-R PROM programmer Relocatable assembler (With structured assembler) PG-1500 controller IE controller Socket for connecting the emulation probe and the target system Note PROM-incorporated products PG-1500 EV-9200G-74 µ PD78P324GJ µ PD78P324LP µ PD78P324KC µ PD78P324KD + + + Socket for plastic QFJ Programmer adapters Target system PA-78P324GJ Note PA-78P324LP PA-78P324KC PA-78P324KD The socket is supplied with the emulation probe. Remarks 1. It is also possible to use the host machine and the PG-1500 by connecting them directly by the RS232-C. 2. In the diagram above, representative software supply media and 3.5-inch FDs. 76 µPD78P324, 78P324(A) B.2 EVALUATION TOOLS To evaluate the functions of the µPD78P324, the following tools are made available. Part Number Host Machine EB-78320-98 PC-9800 series EB-78320-PC IBM PC/AT or its compatible machine Note Function By connecting to a host machine, it is possible to evaluate the functions equipped by the µPD78P324 in a simple manner. The command system of this product basically conforms to that of IE-78327-R and IE-78320R. Therefore, it is easy to move to the development work of application systems by IE-78327-R or IE-78320-R. In addition a turbo access manager (µPD71P301)Note can be mounted on the board. The turbo access manager (µPD71P301) is a maintenance product. Cautions 1. This product is not a development tool of µPD78P324 application systems. 2. This product is not equipped with the emulation function for executing the PROM incorporated in the µPD78P324. B.3 EMBEDDED SOFTWARE The following embedded software programs are available to perform program development and maintenance more efficiently. Eeal-time OS Real-time OS (RX78K/III) The RX78K/III is designed to provide a multi-task environment in the field of control application where real-time operation is required. By using this real-time OS, the performance of the whole system can be improved by allocating CPU’s idle time to other processings. The RX78K/III provides the system call based on the µITRON specifications. The RX78K/III package provides tools (configurators) for creating RX78K/III’s nucleus and multiple information table. Host machine Part number OS PC-9800 series IBM PC/AT and its compatible machine Caution Supply medium 3.5-inch 2HD µS5A13RX78320 5-inch 2HD µS5A10RX78320 3.5-inch 2HC µS7B13RX78320 5-inch 2HC µS7B10RX78320 MS-DOS PC DOS To purchase the operating system above, you need to fill in a purchase application form beforehand and sign a contract allowing you to use the software. Remark When using the real-time OS RX78K/III, you need the assembler package RA78K/III (optional) as well. 77 µPD78P324, 78P324(A) Fuzzy Inference Development Support System Fuzzy knowledge data creation tools (FE9000, FE9200) This program supports inputting/editing/evaluating (through simulation) of the fuzzy knowledge data (fuzzy rules and membership functions). Host machine Part number OS PC-9800 series IBM PC/AT and its compatible machine Translator (FT78K3)Note Supply medium 3.5-inch 2HD µS5A13FE9000 5-inch 2HD µS5A10FE9000 3.5-inch 2HC µS7B13FE9000 5-inch 2HC µS7B10FE9000 MS-DOS PC DOS Winsows This program converts the fuzzy knowledge data obtained with fuzzy knowledge data creation tools to an assembler source program for RA78K/III. Host machine Part number OS PC-9800 series IBM PC/AT and its compatible machine Fuzzy inference module (FI78K/III)Note Supply medium 3.5-inch 2HD µS5A13FT78K3 5-inch 2HD µS5A10FT78K3 3.5-inch 2HC µS7B13FT78K3 5-inch 2HC µS7B10FT78K3 MS-DOS PC DOS This program executes fuzzy inference. Fuzzy inference is executed by being linked to the fuzzy knowledge data converted by the translator. Host machine Part number OS PC-9800 series IBM PC/AT and its compatible machine Fuzzy inference debugger (FD78K/III) Supply medium 3.5-inch 2HD µS5A13FI78K3 5-inch 2HD µS5A10FI78K3 3.5-inch 2HC µS7B13FI78K3 5-inch 2HC µS7B10FI78K3 MS-DOS PC DOS This is a support software program for evaluating and adjusting the fuzzy knowledge data at a hardware level by using the in-circuit emulator. Host machine Part number OS PC-9800 series IBM PC/AT and its compatible machine Note 78 Under development Supply medium 3.5-inch 2HD µS5A13FD78K3 5-inch 2HD µS5A10FD78K3 3.5-inch 2HC µS7B13FD78K3 5-inch 2HC µS7B10FD78K3 MS-DOS PC DOS µPD78P324, 78P324(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. QTOP is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corp. PC/AT and PC DOS are trademarks of IBM Corp. HP9000 series 300 and HP-UX are trademarks of Hewlett-Packard. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems Inc. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. 79 µPD78P324, 78P324(A) The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: µPD78P324KC, 78P324KD The customer must judge the need for license: µPD78P324GJ-5BJ/(A)/(A1)/(A2)/, 78P324LP/(A)/(A1)/(A2) No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11