UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 REVISION HISTORY REVISION DESCRIPTION Preliminary Rev. 0.1 Original. Rev. 1.0 1.Revised Access time : 55/70/100nsB55/70ns 2.Revised Standby current : Delete 20uA(TYP.) L-version 3.Revised extended temp : -20℃~80℃B-20℃~85℃ 4.Revised block diagram 5.Revised DC ELECTRICAL CHARACTERISTICS： a. 55ns Icc MAX. : 45B35mA b. 70ns Icc MAX. : 35B25mA c. 55ns Icc TYP. : 30B25mA d. 70ns Icc TYP. : 25B20mA e. ISB1 of LL-version Typical : 3uAB2uA Maximum : 25uAB10uA 6.Revised AC ELECTRICAL CHARACTERISTICS： a. tBLZ : 5nsB10ns (min.) b. tOH : 0nsB10ns (min.) 7.Revised DATA RETENTION CHARACTERISTICS： a. IDR : Typical : 0.5uAB1uA , Maximum : 20uAB6uA 8.Revised 48-pin TFBGA package outline dimension： a. Rev. 0.1 ball diameter=0.3mm b. Rev.1.0 ball diameter=0.35mm Rev. 1.1 Add order information for lead free product UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Released Date Sep 5, 2001 Jul 25, 2002 May 09, 2003 P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 FEATURES GENERAL DESCRIPTION The UT62L6416 is a 1,048,576-bit low power CMOS static random access memory organized as 65,536 words by 16 bits. Fast access time : 55/70ns CMOS Low power operating Operating current : 35/25mA (Icc max) Standby current : 2uA(TYP.) LL-version Single 2.7V~3.6V power supply Operating temperature: Commercial : 0℃~70℃ Extended : -20℃~85℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Data retention voltage: 1.5V (min) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 44-pin 400mil TSOPⅡ 48-pin 6mm × 8mm TFBGA The UT62L6416 operates from a single 2.7V ~ 3.6V power supply and all inputs and outputs are fully TTL compatible. The UT62L6416 is design for upper and lower byte access by data byte control ( UB LB ). FUNCTIONAL BLOCK DIAGRAM A0-A15 DECODER 64Kx16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 Lower Byte I/O9-I/O16 Upper Byte CE OE WE LB UB CONTROL CIRCUIT UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 PIN CONFIGURATION A4 A3 1 44 A5 43 42 A6 A2 2 3 A1 4 41 OE A0 40 UB I/O1 7 I/O2 8 I/O3 9 I/O4 10 11 Vcc Vss I/O5 12 13 UT62L6416 CE 5 6 A LB OE A0 A1 A2 NC B I/O9 UB A3 A4 CE I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 NC A7 I/O4 Vcc A7 39 LB 38 37 I/O16 36 I/O14 35 I/O13 34 Vss E Vcc I/O13 NC NC I/O5 Vss 33 32 Vcc I/O12 F I/O15 I/O14 A14 A15 I/O6 I/O7 31 I/O11 G I/O16 NC A12 A13 WE I/O8 H NC A8 A9 A10 A11 NC 1 2 3 4 5 6 I/O15 I/O6 14 I/O7 15 30 I/O10 I/O8 16 17 29 I/O9 WE A15 18 28 27 NC A8 A14 A13 19 20 26 A9 25 A10 A12 21 22 24 23 A11 NC NC TFBGA TSOP II PIN DESCRIPTION SYMBOL A0 - A15 I/O1 - I/O16 CE DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input WE OE Output Enable Input LB UB VCC VSS NC Upper-Byte Control Power Supply Ground No Connection Lower-Byte Control UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 TRUTH TABLE MODE Standby Output Disable Read Write Note: CE OE WE LB UB H X L L L L L L L L X X H H L L L X X X X X H H H H H L L L X H L X L H L L H L X H X L H L L H L L SUPPLY CURRENT I/O OPERATION I/O1-I/O8 I/O9-I/O16 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT DIN High – Z High – Z DIN DIN DIN ISB, ISB1 ISB, ISB1 ICC,ICC1,ICC2 ICC,ICC1,ICC2 ICC,ICC1,ICC2 H = VIH, L=VIL, X = Don't care. ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Commercial Operating Temperature Extended Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL RATING VTERM TA TA TSTG PD IOUT Tsolder UNIT -0.5 to 4.6 0 to 70 -20 to 85 -65 to 150 1 50 260 V ℃ ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, TA = 0℃ to 70℃ / -20℃ to 85℃(E)) PARAMETER Power Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Power Supply Current Average Operation Current SYMBOL VCC *1 VIH *2 VIL ILI ILO VOH VOL ICC MIN. 2.7 2.2 -0.2 -1 -1 2.2 - TYP. 3.0 25 20 MAX. 3.6 VCC+0.3 0.6 1 1 0.4 35 25 UNIT V V V µA µA V V mA mA 100%duty, II/O=0mA, CE ≦0.2V, Tcycle= 1µs other pins at 0.2V or Vcc-0.2V, Tcycle= 500ns - 4 5 mA - 8 10 mA 1. CE =VIH, other pins =VIL or VIH, - 0.3 0.5 mA 2. UB = LB = VIH, other pins =VIL or VIH, -LL =VCC-0.2V, 1. - 2 10 µA VSS ≦VIN ≦VCC VSS ≦VI/O ≦VCC; Output Disabled IOH= -1mA IOL= 2.1mA Cycle time=min, 100%duty, I/O=0mA, CE =VIL ; Icc1 Icc2 Standby Current (TTL) TEST CONDITION ISB CE Standby Current (CMOS) ISB1 55 70 other pins at 0.2V or Vcc-0.2V, 2. UB = LB =VCC-0.2V, other pins at 0.2V or Vcc-0.2V, Notes: 1. Overshoot : Vcc+3.0v for pulse width less than 10ns. 2. Undershoot : Vss-3.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 30pF, IOH/IOL = -1mA / 2.1mA AC ELECTRICAL CHARACTERISTICS (VCC =2.7V~3.6V, TA =0℃ to 70℃ / -20℃ to 85℃(E)) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change LB , UB Access Time LB , UB to High-Z Output LB , UB to Low-Z Output SYMBOL tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ tBLZ UT62L6416-55 MIN. 55 10 5 10 10 MAX. 55 55 30 20 20 55 25 - UT62L6416-70 MIN. 70 10 5 10 10 MAX. 70 70 35 25 25 70 30 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z SYMBOL tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW UT62L6416-55 MIN. 55 50 50 0 45 0 25 0 5 45 MAX. 30 - LB , UB Valid to End of Write *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 UT62L6416-70 MIN. 70 60 60 0 55 0 30 0 5 60 MAX. 30 - UNIT ns ns ns ns ns ns ns ns ns ns ns P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE tBA LB , UB t BHZ tBLZ OE t CHZ tOE tCLZ tOHZ t OH tOLZ Dout High-Z High-Z Data Valid Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, LB or UB =low. 3.Address must be valid prior to or coincident with CE =low, LB or UB =low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tW C Address tAW CE t CW t AS tW P tW R WE tBW LB , UB t W HZ t OW High-Z Dout (4) tDW tDH (4) Din Data Valid WRITE CYCLE 2 ( CE Controlled) (1,2,5,6) tW C A ddress tA W CE tW R tA S tC W tW P WE tB W LB , U B tW H Z D out H igh-Z (4) tD W tD H D in D ata V alid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 WRITE CYCLE 3 ( LB , UB Controlled) (1,2,5,6) tWC Address tAW CE tAS tCW tWR tWP WE tBW LB , UB tWHZ High-Z Dout tDW Din tDH Data Valid Notes : 1. WE , CE , LB , UB must be high during all address transitions. 2.A write occurs during the overlap of a low CE , low WE , LB or UB =low. 3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE , LB , UB low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃ / -20℃ to 85℃(E)) PARAMETER Vcc for Data Retention SYMBOL VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tCDR TEST CONDITION CE ≧ VCC-0.2V Vcc=1.5V - LL CE ≧ VCC-0.2V See Data Retention Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 1 6 µA 0 - - ms 5 - - ms DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) ( CE controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR CE VIH tR CE ≧ VCC-0.2V VIH Low Vcc Data Retention Waveform (2) ( LB , UB controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR LB,UB VIH tR LB,UB ≧ VCC-0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 VIH P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 PACKAGE OUTLINE DIMENSION θ 44 pin 400mil TSOP-Ⅱ PACKAGE OUTLINE DIMENSION SYMBOLS A A1 A2 b c D E E1 e L 2D y Θ DIMENSIONS IN MILLMETERS MIN NOM MAX. 1.00 1.20 0.05 0.15 0.95 1.00 1.05 0.30 0.35 0.45 0.12 0.21 18.313 18.415 18.517 11.854 11.836 11.838 10.058 10.180 10.282 0.800 0.40 0.50 0.60 0.805 0.00 0.076 o o 0 5 DIMENSIONS IN INCHS MIN. NOM. MAX. 0.039 0.047 0.002 0.006 0.037 0.039 0.041 0.012 0.014 0.018 0.0047 0.083 0.721 0.725 0.728 0.460 0.466 0.470 0.398 0.400 0.404 0.0315 0.0157 0.020 0.0236 0.0317 0.000 0.003 o o 0 5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 48 pin 6mm×8mm TFBGA PACKAGE OUTLINE DIMENSION UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 ORDERING INFORMATION COMMERCIAL TEMPERATURE PART NO. UT62L6416MC-55LL UT62L6416MC-70LL UT62L6416BS-55LL UT62L6416BS-70LL EXTENDED TEMPERATURE PART NO. UT62L6416MC-55LLE UT62L6416MC-70LLE UT62L6416BS-55LLE UT62L6416BS-70LLE ACCESS TIME (ns) 55 70 55 70 STANDBY CURRENT (µA) TYP. 2 2 2 2 ACCESS TIME (ns) 55 70 55 70 STANDBY CURRENT (µA) TYP. 2 2 2 2 PACKAGE 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 48 PIN TFBGA 48 PIN TFBGA PACKAGE 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 48 PIN TFBGA 48 PIN TFBGA ORDERING INFORMATION (for lead free product) COMMERCIAL TEMPERATURE PART NO. UT62L6416MCL-55LL UT62L6416MCL-70LL UT62L6416BSL-55LL UT62L6416BSL-70LL EXTENDED TEMPERATURE PART NO. UT62L6416MCL-55LLE UT62L6416MCL-70LLE UT62L6416BSL-55LLE UT62L6416BSL-70LLE ACCESS TIME (ns) 55 70 55 70 STANDBY CURRENT (µA) TYP. 2 2 2 2 ACCESS TIME (ns) 55 70 55 70 STANDBY CURRENT (µA) TYP. 2 2 2 2 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 PACKAGE 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 48 PIN TFBGA 48 PIN TFBGA PACKAGE 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 48 PIN TFBGA 48 PIN TFBGA P80073 UTRON UT62L6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 13 P80073