PRELIMINARY W167B 133-MHz Spread Spectrum FTG for Pentium® II Platforms Features Duty Cycle: ................................................................ 45/55% • Maximized EMI Suppression using Cypress’s Spread Spectrum technology • Three copies of CPU outputs selectable frequency • Three copies of 3V66 selectable frequency output at 3.3V • Ten copies of PCI clocks (selectable frequency), 3.3V • One double strength 14.318-MHz reference output at 3.3V • One copy of 48-MHz USB clock • One copy of selectable 24-/48-MHz for SIO • One copy of CPU-divide-by-2 output as reference input to Direct Rambus™ Clock Generator (Cypress W134) • Three copies of IOAPIC • Available in 48-pin SSOP (300 mils) Key Specifications Supply Voltages: ...................................... VDDQ2 = 2.5V±5% VDDQ3 = 3.3V±5% CPU, CPUdiv2 Output Jitter:....................................... 250 ps CPU, CPUdiv2 Output Skew: ...................................... 175 ps IOAPIC, 3V66 Output Skew: ....................................... 250 ps PCI0:8 Pin to Pin Skew: .............................................. 500 ps Spread Spectrum Modulation:................................... ±0.25% CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads) 3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads) CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads) Table 1. Pin Selectable Frequency SEL133/ CPU 100# SEL2 SEL1 SEL0 MHz 1 1 1 1 133.3 1 1 1 0 138 1 1 0 1 143 1 1 0 0 148 1 0 1 1 150 1 0 1 0 152.5 1 0 0 1 155 1 0 0 0 160 0 1 1 1 100.2 0 1 1 0 105 0 1 0 1 114 0 1 0 0 120 0 0 1 1 66.8 0 0 1 0 124 0 0 0 1 128.5 0 0 0 0 133.9 Block Diagram Pin Configuration 3V66 MHz 66.7 69 71.5 74 75 76.3 77.5 80 66.8 70 76 80 66.8 82.7 64.3 67 PCI IOAPIC MHz MHz 33.3 16.7 34.5 17.3 35.8 17.9 37 18.5 37.5 18.8 38.1 19.1 38.8 19.4 40 20 33.4 16.7 35 17.5 38 19 40 20 33.4 16.7 41.3 20.7 32.1 16.1 33.5 16.7 [1] VDDQ3 X1 X2 XTAL OSC REF2X VDDQ2 3 ÷2 SEL133/100# CPU_[0:2] CPUdiv2 PLL 1 VDDQ3 3V66_[0:2] ÷2/÷1.5 3 PCI0/SEL2* PCI1/SEL1* ÷2 PWRDWN# PCI_[2:9] 8 VDDQ2 Power Down Logic ÷2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 W167B IOAPIC2 REF2X VDDQ3 X1 X2 GND SEL2*/PCI0 SEL1*/PCI1 VDDQ3 PCI2 PCI3 PCI4 PCI5 GND PCI6 PCI7 VDDQ3 PCI8 PCI9 GND 3V66_0 3V66_1 3V66_2 VDDQ3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND VDDQ2 IOAPIC0 IOAPIC1 GND VDDQ2 CPUdiv2 GND VDDQ2 CPU2 GND VDDQ2 CPU1 CPU0 SDATA VDDQ3 GND PWRDN#* SCLK VDDQ3 SIO/24_48#MHz* 48MHz/SEL0* GND SEL133/100# IOAPIC[0:2] 3 Q# VDDQ3 PLL2 SDATA SCLK 48MHz/SEL0* ÷2 Note: 1. Internal 250-kΩ pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH. SIO/24_48#MHz Serial Logic Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 2, 1999 PRELIMINARY W167B Pin Definitions Pin No. Pin Type 35, 36, 39 O CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage swing is controlled by voltage applied to VDDQ2. SEL133/100# 25 I SEL133/100#: Frequency selection input pin as shown in Table 1. PCI0/SEL2 7 I/O PCI Clock Output 0 and Selection Bit 2: As an output, this pin works in conjunction with PCI2:9. When an input, this pin functions as part of the frequency selection address (see Table 1). PCI1/SEL1 8 I/O PCI Clock Output 1 and Selection Bit 1: As an output, this pin works in conjunction with PCI2:9. When an input, this pin functions as part of the frequency selection address (see Table 1). PCI2:9 10, 11, 12, 13, 15, 16, 18, 19 O PCI Clock Outputs 2 through 9: Output voltage swing is controlled by voltage applied to VDDQ3. 3V66_0:2 21, 22, 23 O 66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by voltage applied to VDDQ3. CPUdiv2 42 O CPU-Divide-By-2 Output: This serves as a reference input signal for Direct Rambus Clock Generator (Cypress W134). The output voltage is determined by VDDQ2. 46, 45, 1 O I/O APIC Clock Output 0 through 2: Provide outputs synchronous to CPU clock. See Table 1 and Table 5 for their relation to other system clock outputs. 48MHZ/SEL0 27 I/O 48-MHz Output and Selection Bit 0: Fixed clock output that defaults to 48-MHz following device power-up. When an input, this pin functions as part of the frequency selection address (see Table 1). SIO/24_48#MHz 28 I/O Super I/O Reference Clock Output and SIO Clock Frequency Select: Fixed clock output that provides the reference input clock to a Super I/O device. The output frequency is determined by the input value on this pin during power up. If input is sampled HIGH, the output operates at 24 MHz, otherwise, the output operates at 48 MHz. REF2X 2 O Fixed 14.318-MHz Output: With double strength driving capability. PWRDWN# 31 I Power Down Control X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. SDATA 34 I/O SCLK 30 I Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data Interface section that follows. VDDQ2 37, 40, 43, 47 P Power Connection: Connected to 2.5V power supply. VDDQ3 3, 9, 17, 24, 29, 33 P Power Connection: Connected to 3.3V supply. GND 6, 14, 20, 26, 32, 38, 41, 44, 48 G Ground Connection: Connect all ground pins to the common system ground plane. Pin Name CPU0:2 IOAPIC0:2 Pin Description Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Interface section that follows. 2 PRELIMINARY W167B on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O pin is then latched. Next, the output buffers are enabled, converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. Overview The W167B, a motherboard clock synthesizer, provides 2.5V CPU clock outputs for advanced CPU and a CPU-divide-by-2 reference frequency for Direct Rambus Clock Generator (such as Cypress W134) interface. Fixed output frequencies are provided for other system functions. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock outputs is <40Ω (nominal) which is minimally affected by the 10-kΩ strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. I/O Pin Operation Pins 7, 8, 27, and 28 are dual-purpose l/O pins. Upon powerup these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of these pins is latched and the pins then become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-kΩ “strapping” resistor is connected between each l/O pin and ground or VDD3. Connection to ground sets a latch to “0”, connection to V DD3 sets a latch to “1”. Figure 1 and Figure 2 show two suggested methods for strapping resistor connection. When the clock outputs are enabled following the 2-ms input period, target (normal) output frequency is delivered assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Upon W167B power up, the first 2 ms of operation is used for input logic selection. During this period, these dual-purpose I/O pins are three-stated, allowing the output strapping resistor VDD Output Strapping Resistor Series Termination Resistor 10 kΩ (Load Option 1) W167B Power-on Reset Timer Hold Output Low Output Three-state Q Clock Load R Output Buffer 10 kΩ (Load Option 0) D Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Jumper Options Output Strapping Resistor VDD Series Termination Resistor 10 kΩ W167B R Output Buffer Power-on Reset Timer Hold Output Low Output Three-state Q D Data Latch Figure 2. Input Logic Selection Through Jumper Option 3 Clock Load PRELIMINARY W167B CPU/PCI Frequency Selection Crystal Oscillator CPU frequency is selected with I/O pins 7, 8, 27, (SEL2/PCI0, SEL1/PCI1, 48MHz/SEL0, respectively) and input pin 25 (SEL133/100#). Refer to Table 1 for CPU/PCI frequency programming information. Additional frequency selections are available through the serial data interface. Refer to Table 5 on page 9. The W167B requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The W167B incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 18 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 18 pF should be used. This will typically yield reference frequency accuracies within ±100 ppm. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The W167B outputs are CMOS-type which provide railto-rail output swing. 4 PRELIMINARY W167B Spread Spectrum Feature Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is –0.5% downspread. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) EMI Reduction Spread Spectrum Enabled NonSpread Spectrum Time Figure 4. Typical Modulation Profile 5 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 100% 80% 60% 40% 20% 0% –20% –40% –60% –80% –100% 10% Frequency Shift Figure 3. Typical Clock and SSFTG Comparison PRELIMINARY W167B SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Serial Data Interface The W167B features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W167B initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins Table 2. Serial Data Interface Control Functions Summary Control Function Description Common Application Clock Output Disable Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI slot. CPU Clock Frequency Selection Provides CPU/PCI frequency selections. Frequency is changed in a smooth and controlled fashion. For alternate CPU devices, and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing. Test Mode All clock outputs toggle in relation with X1 input, internal PLL is bypassed. Refer to Table 4. Production PCB testing. (Reserved) Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0. Operation Data is written to the W167B in ten bytes of eight bits each. Bytes are written in the order shown in Table 3. Table 3. Byte Writing Sequence Byte Sequence Byte Name 1 Slave Address 11010010 Bit Sequence Commands the W167B to accept the bits in Data Bytes 0–6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W167B is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Byte Description 2 Command Code Don’t Care Unused by the W167B, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W167B, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 Refer to Table 4 5 Data Byte 1 6 Data Byte 2 The data bits in these bytes set internal W167B registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map. 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 6 PRELIMINARY Writing Data Bytes W167B 7. Table 4 gives the bit formats for registers located in Data Bytes 0–6. Table 5 details additional frequency selections that are available through the serial data interface. Table 6 details the select functions for Byte 0, bits 1 and 0. Each bit in the data bytes control a particular device function except for the “reserved” bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 4. Data Bytes 0–6 Serial Configuration Map Affected Pin Bit(s) Pin No. Bit Control Pin Name Control Function 0 1 Default Data Byte 0 7 -- -- SEL133/100# Refer to Table 5 0 6 -- -- SEL2 Refer to Table 5 0 5 -- -- SEL1 Refer to Table 5 0 4 -- -- SEL0 Refer to Table 5 0 3 -- -- Frequency Table Selection 2 -- -- (Reserved) 1-0 -- -- Functional control 7 27 48MHz Clock Output Disable Low Active 1 6 28 24/48MHz Clock Output Disable Low Active 1 5 -- -- -- -- 0 4 42 CPUdiv2 Low Active 1 3 -- -- -- -- 0 2 39 CPU2 Clock Output Disable Low Active 1 1 36 CPU1 Clock Output Disable Low Active 1 0 35 CPU0 Clock Output Disable Low Active 1 Controlled by external pin (per Table 1) Controlled by BYTE0 (per Table 5) -- -Refer to Table 6 0 0 00 Data Byte 1 (Reserved) Clock Output Disable (Reserved) Data Byte 2 7 16 PCI7 Clock Output Disable Low Active 1 6 15 PCI6 Clock Output Disable Low Active 1 5 13 PCI5 Clock Output Disable Low Active 1 4 12 PCI4 Clock Output Disable Low Active 1 3 11 PCI3 Clock Output Disable Low Active 1 2 10 PCI2 Clock Output Disable Low Active 1 1 8 PCI1 Clock Output Disable Low Active 1 0 7 PCI0 Clock Output Disable Low Active 1 -- -- 0 Data Byte 3 7 -- -- (Reserved) 6 23 3V66_2 Clock Output Disable Low Active 1 5 22 3V66_1 Clock Output Disable Low Active 1 4 21 3V66_0 Clock Output Disable Low Active 1 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 19 PCI9 Clock Output Disable Low Active 1 0 18 PCI8 Clock Output Disable Low Active 1 7 PRELIMINARY W167B Table 4. Data Bytes 0–6 Serial Configuration Map (continued) Affected Pin Bit(s) Pin No. Pin Name Bit Control Control Function 0 1 Default Data Byte 4 7 -- -- -- -- 0 6 1 IOAPIC2 (Reserved) Clock Output Disable Low Active 1 5 45 IOAPIC1 Clock Output Disable Low Active 1 4 46 IOAPIC0 Clock Output Disable Low Active 1 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 2 REF2X Low Active 1 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 -- -- -- (Reserved) -- -- 0 Clock Output Disable Data Byte 5 Data Byte 6 8 PRELIMINARY W167B Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes SEL133/100# SEL2 SEL1 SEL0 CPU MHz 3V66 MHz PCI MHz IOAPIC MHz 1 1 1 1 133.3 66.7 33.3 16.7 1 1 1 0 138 69 34.5 17.3 1 1 0 1 143 71.5 35.8 17.9 1 1 0 0 148 74 37 18.5 1 0 1 1 150 75 37.5 18.8 1 0 1 0 152.5 76.3 38.1 19.1 1 0 0 1 155 77.5 38.8 19.4 1 0 0 0 160 80 40 20 0 1 1 1 100.2 66.8 33.4 16.7 0 1 1 0 105 70 35 17.5 0 1 0 1 114 76 38 19 0 1 0 0 120 80 40 20 0 0 1 1 66.8 66.8 33.4 16.7 0 0 1 0 124 82.7 41.3 20.7 0 0 0 1 128.5 64.3 32.1 16.1 0 0 0 0 133.9 67 33.5 16.7 Table 6. Select Function for Data Byte 0, Bits 0:1 Input Conditions Output Conditions Data Byte 0 Function Bit 1 Bit 0 CPU0:2, PCI0:9 REF2X IOAPIC0:2 48/24MHZ Normal Operation 0 0 Note 2 Note 2 14.318 MHz Note 2 48/24 MHz Test Mode 0 1 TBD TBD TBD TBD TBD Spread Spectrum 1 0 ±0.25% ±0.25% 14.318 MHz ±0.25% 48/24 MHz Three-state 1 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note: 2. CPU, IOAPIC, and PCI frequency selections are listed in Table 1 and Table 5. 9 PRELIMINARY W167B Although the W167B is a receive-only device (no data writeback capability), it does transmit an “acknowledge” data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. How To Use the Serial Data Interface Electrical Requirements Figure 5 illustrates electrical characteristics for the serial interface bus used with the W167B. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistors on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. VDD VDD ~ 2kΩ ~ 2kΩ SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE SDCLK CLOCK IN CLOCK OUT SDATA SCLOCK DATA IN N DATA OUT CLOCK IN N DATA IN DATA OUT CHIP SET (SERIAL BUS MASTER TRANSMITTER) CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER) Figure 5. Serial Interface Bus Electrical Characteristics 10 SDATA N PRELIMINARY W167B Signaling Requirements Sending Data to the W167B As shown in Figure 6, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition). A write sequence is initiated by a “start bit” as shown in Figure 7. A “stop bit” signifies that a transmission has ended. As stated previously, the W167B sends an “acknowledge” pulse after receiving eight data bits in each byte as shown in Figure 8. SDATA SCLOCK Valid Data Bit Change of Data Allowed Figure 6. Serial Data Bus Valid Data Bit SDATA SCLOCK Start Bit Stop Bit Figure 7. Serial Data Bus Start and Stop Bit 11 Stop Condition Slave Address (First Byte) Command Code (Second Byte) SDATA MSB 1 1 0 1 0 0 LSB 1 0 SCLOCK 1 2 3 4 5 6 7 8 Byte Count (Third Byte) MSB A 1 LSB 2 3 4 5 6 7 8 Last Data Byte (Last Byte) MSB A 1 MSB 2 3 4 1 LSB 2 3 4 5 6 SDATA Acknowledgment Bit from Clock Device Signaling by Clock Device 7 8 A PRELIMINARY Figure 8. Serial Data Bus Write Sequence Signaling from System Core Logic Start Condition 12 tSPF tLOW SCLOCK tSTHD tDSU tHIGH tR tF tDHD tSP tSPSU tSTHD t SPSU W167B Figure 9. Serial Data Bus Timing Diagram SDATA PRELIMINARY W167B Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 2 (min.) kV TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias ESDPROT Input ESD Protection DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% Parameter Description Test Condition Min. Typ. Max. Unit 160 mA 90 mA Supply Current IDD-3.3V IDD-2.5 Combined 3.3V Supply Current CPU0:3 =133 MHz[3] Combined 2.5V Supply Current [3] CPU0:3 =133 MHz Logic Inputs (All referenced to VDDQ3 = 3.3V) VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 VDD + 0.3 V IIL Input Low Current[4] –25 µA 10 µA IIH [4] Input High Current [4] IIL Input Low Current, SEL133/100# –5 µA IIH Input High Current, SEL133/100#[4] 5 µA Max. Unit 50 mV Clock Outputs CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2) Test Condition Min. Typ. VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 2.2 IOL Output Low Current VOL = 1.25V 45 65 100 mA IOH Output High Current VOH = 1.25V 45 65 100 mA Min. Typ. Max. Unit 50 mV 48MHz, REF (Referenced to VDDQ3) Test Condition VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 IOL Output Low Current VOL = 1.5V 45 IOH Output High Current VOH = 1.5V PCI, 3V66 (Referenced to VDDQ3) Test Condition V V 65 100 mA 45 65 100 mA Min. Typ. Max. Unit 50 mV VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 IOL Output Low Current VOL = 1.5V 70 100 145 mA IOH Output High Current VOH = 1.5V 65 95 135 mA Notes: 3. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors. 4. W167B logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level). 13 V PRELIMINARY W167B DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued) Parameter Description Test Condition Min. Typ. Max. Unit Crystal Oscillator VTH X1 Input Threshold Voltage[5] CLOAD Load Capacitance, Imposed on External Crystal[6] CIN,X1 X1 Input Capacitance[7] Pin X2 unconnected 1.65 V 18 pF 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Except X1 and X2 5 pF 3.3V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[8] 3V66 Clock Outputs, 3V66_0:2 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments Min. Typ. Max. 66.6 Unit f Frequency Note 9 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 MHz Ω Notes: 5. X1 input threshold voltage (typical) is VDD/2. 6. The W167B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 8. Period, jitter, offset, and skew measured on rising edge at 1.5V. 9. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz. 14 PRELIMINARY W167B PCI Clock Outputs, PCI0:9 (Lump Capacitance Test Load = 30 pF Parameter Description Test Condition/Comments [10] Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 tF Output Fall Edge Rate Measured from 2.4V to 0.4V tD Duty Cycle Measured on rising and falling edge at 1.5V tJC Jitter, Cycle-to-Cycle tSK 4 V/ns 1 4 V/ns 45 55 % Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 500 ps Output Skew Measured on rising edge at 1.5V 500 ps tO 3V66 to PCI Clock Skew Covers all 3V66/PCI outputs. Measured on rising edge at 1.5V. 3V66 leads PCI output. 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 1.5 Ω 15 REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Frequency generated by crystal oscillator 14.318 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ω 25 48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) fD Deviation from 48 MHz (48.008 – 48)/48 m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Note: 10. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz. 15 48.008 MHz +167 ppm 57/17 25 Ω PRELIMINARY W167B 2.5V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, V DDQ2= 2.5V±5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[11] CPU Clock Outputs, CPU0:2 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter Description Test Condition/Comments CPU = 100 MHz Min. Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.25V 7.5 tH High Time Duration of clock cycle above 2.0V 1.87 3.0 ns tL Low Time Duration of clock cycle below 0.4V 1.67 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 7.65 10 10.2 ns Ω 20 20 CPU = 133 MHz CPU = 100 MHz CPUdiv2 Clock Outputs, CPUdiv2 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Min. Measured on rising edge at 1.25V 15 tH High Time Duration of clock cycle above 2.0V 5.25 7.5 ns tL Low Time Duration of clock cycle below 0.4V 5.05 7.3 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 16 20 20 20.4 Unit Period Note: 11. Period, Jitter, offset, and skew measured on rising edge at 1.25V. 15.3 Typ. Max. tP 20 ns Ω PRELIMINARY W167B IOAPIC Clock Output, IOAPIC (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments f Frequency Note 12 tR Output Rise Edge Rate Measured from 0.4V to 2.0V tF Output Fall Edge Rate Measured from 2.0V to 0.4V tD Duty Cycle Measured on rising and falling edge at 1.25V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ordering Information W167B Package Name H Typ Max 16.67 Note: 12. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz. Ordering Code Min Package Type 48-pin SSOP (300 mils) Document #: 38-00816 17 1 Unit MHz 4 V/ns 1 4 V/ns 45 55 % 3 ms 20 Ω PRELIMINARY W167B Package Diagram 48-Pin Small Shrink Outline Package (SSOP, 300 mils) © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.