CYPRESS W209C

PRELIMINARY
W209C
Frequency Generator for Integrated Core Logic
with 133-MHz FSB
Features
Table 1. Frequency Selections
PCI
APIC
SS
113.0
75.3
37.6
18.8
OFF
95.0
95.0
63.3
31.6
15.8
–0.6%
129.0
129.0
86.0
43.0
21.5
OFF
150.0
113.0
75.3
37.6
18.8
OFF
0
150.0
150.0
100.0 50.0
25.0
OFF
0
1
110.0
110.0
73.0
36.6
18.3
OFF
1
1
0
140.0
140.0
93.3
46.7
23.3
OFF
0
1
1
1
144.0
108.0
72.0
36.0
18.0
OFF
0
1
0
0
0
68.3
102.5
68.3
34.1
17.0
OFF
0
1
0
0
1
105.0
105.0
70.0
35.0
17.5
OFF
0
1
0
1
0
138.0
138.0
92.0
46.0
23.0
OFF
0
1
0
1
1
140.0
105.0
70.0
35.0
17.5
OFF
0
1
1
0
0
66.8
100.2
66.8
33.4
16.7
±0.45%
0
1
1
0
1
100.2
100.2
66.8
33.4
16.7
±0.45%
0
1
1
1
0
133.6
133.6
89.1
44.4
22.2
±0.45%
0
1
1
1
1
133.6
100.2
66.8
33.4
16.7
±0.45%
1
0
0
0
0
157.3
118.0
78.6
39.3
19.6
OFF
Key Specifications
1
0
0
0
1
160.0
120.0
80.0
40.0
20.0
OFF
1
0
0
1
0
146.6
110.0
73.3
36.6
18.3
OFF
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
1
0
0
1
1
122.0
91.5
61.0
30.5
15.2
–0.6%
1
0
1
0
0
127.0
127.0
84.6
42.3
21.1
OFF
1
0
1
0
1
122.0
122.0
81.3
40.6
20.3
–0.6%
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clock
• Nine copies of SDRAM clock
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Two copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of selectable 24- or 48-MHz clock
• One copy of double strength 14.31818-MHz reference
clock
• Power-down control
• SMBus interface for turning off unused clocks
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
1
0
0
0
CPU
SDRAM 3V66
75.3
1
0
1
1
0
117.0
117.0
78.0
39.0
19.5
OFF
CPU, 3V66 Output Skew: ........................................... 175 ps
1
0
1
1
1
114.0
114.0
76.0
38.0
19.0
OFF
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps
1
1
0
0
0
80.0
120.0
80.0
40.0
20.0
OFF
1
1
0
0
1
78.0
117.0
78.0
39.0
19.5
OFF
1
1
0
1
0
166.0
166.0
55.3
27.6
13.8
OFF
CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns
1
1
0
1
1
160.0
160.0
53.3
26.7
13.3
OFF
CPU to SDRAM Skew (@ 100 MHz) ................. 4.5 to 5.5 ns
1
1
1
0
0
66.6
100.0
66.6
33.3
16.6
–0.6%
1
1
1
0
1
100.0
100.0
66.6
33.3
16.6
–0.6%
1
1
1
1
0
133.3
133.3
88.9
44.4
22.2
–0.6%
1
1
1
1
1
133.3
100.0
66.6
33.3
16.6
–0.6%
PCI Output Skew: ....................................................... 500 ps
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead) .......................... 1.5 to 3.5 ns
PCI to APIC Skew..................................................... ± 0.5 ns
VDDQ3
Block Diagram
X1
X2
PLL REF FREQ
VDDQ2
SDATA
SCLK
SMBus
Logic
CPU0:1
Divider,
Delay,
and
Phase
Control
Logic
2
APIC
VDDQ3
2
PLL 1
3V66_0:1
FS0*/PCI0
FS1*/PCI1
FS2*/PCI2
5
PCI3:7
SDRAM0:7
PWRDWN#
8
DCLK
VDDQ3
48MHz_0
PLL2
FS4*/48MHz_1
SI0/24_48#MHz*
/2
Cypress Semiconductor Corporation
Document #: 38-07171 Rev. *A
•
3901 North First Street
REF2x/FS3*
VDDQ3
X1
X2
GND
VDDQ3
3V66_0
3V66_1
GND
FS0*/PCI0
FS1*/PCI1
FS2*/PCI2
GND
PCI3
PCI4
VDDQ3
PCI5
PCI6
PCI7
GND
48MHz_0
FS4*/48MHz_1
SI0/24_48#MHz*
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W209C
(FS0:4*)
Pin Configuration [1]
REF2X/FS3*
XTAL
OSC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
APIC
VDDQ2
CPU0
CPU1
GND
VDDQ3
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
DCLK
GND
PWRDWN#^
SCLK
VDDQ3
GND
SDATA
Note:
1. Internal pull-down or pull-up resistors present on inputs marked with
* or ^ respectively. Design should not rely solely on internal pull-up
or pull-down resistor to set I/O pins HIGH or LOW respectively.
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 15, 2002
PRELIMINARY
W209C
I
Pin Definitions
Pin No.
Pin
Type
REF2x/FS3
1
I/O
Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock output. This pin also serves as the select strap to determine device operating frequency
as described in Table 1.
X1
3
I
Crystal Input: This pin has dual functions. It can be used as an external 14.318MHz crystal connection or as an external reference frequency input.
X2
4
I
Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected.
FS0*/PCI0
10
I/O
PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
FS1*/PCI1
11
I/O
PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
FS2*/PCI2
12
I/O
PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
14, 15, 17, 18,
19
O
PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually
turned off via SMBus interface.
3V66_0:1
7,8
O
66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled
by FS0:4 (see Table 1).
48MHz_0
21
O
48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output.
FS4*/
48MHz_1
22
I/O
48-MHz Clock Output/Frequency Selection 4: 3.3V fixed 48-MHz, non-spread
spectrum clock output. This pin also serves as the select strap to determine device
operating frequency as described in Table 1.
SIO/
24_48#MHz*
23
I/O
Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device.
During power up, it also serves as a selection strap. If it is sampled HIGH, the output
frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.
PWRDWN#
29
I
Power Down Control: LVTTL-compatible input that places the device in powerdown mode when held LOW.
45, 44
O
CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies
depending on the configuration of FS0:4. Voltage swing is set by VDDQ2.
41, 40, 39, 37,
36, 35, 33, 32,
31
O
APIC
47
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs. Voltage swing set by VDDQ2.
SDATA
25
I/O
Data pin for SMBus circuitry.
SCLK
28
I
Clock pin for SMBus circuitry.
VDDQ3
2, 6, 16, 24, 27,
34, 42
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI output
buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
VDDQ2
46, 48
P
2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V.
5, 9, 13, 20, 26,
30, 38, 43,
G
Ground Connections: Connect all ground pins to the common system ground
plane.
Pin Name
PCI3:7
CPU0:1
SDRAM0:7,
DCLK
GND
Document #: 38-07171 Rev. *A
Pin Description
SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The operating frequency is controlled by FS0:4 (see Table 1).
Page 2 of 16
PRELIMINARY
W209C
Output Strapping Resistor
Series Termination Resistor
Clock Load
W209C
Power-on
Reset
Timer
Output
Buffer
Hold
Output
Low
Output Three-state
Q
10kΩ
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W209C is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic.
Functional Description
Offsets Among Clock Signal Groups
I/O Pin Operation
Pin # 1, 10, 11, 12, 22, and 23 are dual-purpose l/O pins. Upon
power-up the pin acts as a logic input. An external 10-kΩ strapping resistor should be used. Figure 1 shows a suggested
method for strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
10 ns
0 ns
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below target, but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are
enabled.
20 ns
Figure 2 and Figure 3 represent the phase relationship among
the different groups of clock outputs from W209C when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.
30 ns
40 ns
CPU 100 Period
CPU 66-MHz
SDRAM 100 Period
SDRAM 100-MHz
3V66 66-MHz
Hub-PC
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
Document #: 38-07171 Rev. *A
Page 3 of 16
PRELIMINARY
0 ns
10 ns
W209C
20 ns
30 ns
40 ns
CPU 100 Period
CPU 100-MHz
SDRAM 100 Period
SDRAM 100-MHz
3V66 66-MHz
Hub-PC
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
Figure 3. Group Offset Waveforms (100-MHz CPU Clock, 100-MHz SDRAM Clock)
Power Down Control
W209C provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0ns
25ns
50ns
75ns
Center
1
2
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 4. W209C PWRDWN# Timing Diagram[2, 3, 4, 5]
Notes:
2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W209C.
4. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states.
5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Document #: 38-07171 Rev. *A
Page 4 of 16
PRELIMINARY
W209C
Spread Spectrum Frequency Timing Generator
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 5.
The output clock is modulated with a waveform depicted in
Figure 6. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is ±0.5% of the selected frequency. Figure 6 details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
As shown in Figure 5, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
5dB/div
Typical Clock
Amplitude (dB)
SSFTG
-SS%
Frequency Span (MHz)
+SS%
Figure 5. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
FREQUENCY
MAX.
MIN.
Figure 6. Typical Modulation Profile
Document #: 38-07171 Rev. *A
Page 5 of 16
PRELIMINARY
W209C
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Ack
Data Byte 1
Ack
Data Byte 2
Ack
1 bit
8 bits
1
8 bits
1
...
Byte Count = N
Data Byte N
Ack
Stop
8 bits
1
1
Figure 7. An Example of a Block Write[6]
Serial Data Interface
The W209C features a two-pin, serial data interface that can
be used to configure internal register settings that control particular device functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not
allowed.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be
the number 20 (14h), followed by the 20 bytes of data. The
byte count may not be 0. A block write command is allowed to
transfer a maximum of 32 data bytes. The slave receiver address for W209C is 11010010. Figure 7 shows an example of
a block write.
The command code and the byte count bytes are required as
the first two bytes of any transfer. W209C expects a command
code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement. Table 2 shows an
example of a possible byte count value.
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W209C.
However, these bytes must be included in the data write sequence to maintain proper byte allocation.
Table 2. Example of Possible Byte Count Value
Byte Count Byte
Notes
MSB
LSB
0000
0000
Not allowed. Must have at least one byte
0000
0001
Data for functional and frequency select register (currently byte 0 in spec)
0000
0010
Reads first two bytes of data (byte 0 then byte 1)
0000
0011
Reads first three bytes (byte 0, 1, 2 in order)
0000
0100
Reads first four bytes (byte 0, 1, 2, 3 in order)
0000
0101
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[7]
0000
0110
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[7]
0000
0111
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0010
0000
Max. byte count supported = 32
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused
PCI slots.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be written as 0.
Notes:
6. The acknowledgment bit is returned by the slave/receiver (W209C).
7. Bytes 6 and 7 are not defined for W209C.
Document #: 38-07171 Rev. *A
Page 6 of 16
PRELIMINARY
W209C
W209C Serial Configuration Map
2. All unused register bits (reserved and N/A) should be written to a “0” level.
1. The serial bits will be read by the clock driver in the following
order:
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in higher than normal operating current. The controller will read
back the written value.
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register (1 = Enable, 0 = Disable)[8]
Bit
Pin#
Name
Default
Pin Function
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
23
24/48 MHz
1
(Active/Inactive)
Bit 1
21, 22
48 MHz
1
(Active/Inactive)
Bit 0
-
Reserved
0
Reserved
Byte 1: Control Register (1 = Enable, 0 = Disable)[8]
Bit
Pin#
Name
Default
Pin Description
Bit 7
32
SDRAM7
1
(Active/Inactive)
Bit 6
33
SDRAM6
1
(Active/Inactive)
Bit 5
35
SDRAM5
1
(Active/Inactive)
Bit 4
36
SDRAM4
1
(Active/Inactive)
Bit 3
37
SDRAM3
1
(Active/Inactive)
Bit 2
39
SDRAM2
1
(Active/Inactive)
Bit 1
40
SDRAM1
1
(Active/Inactive)
Bit 0
41
SDRAM0
1
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0 = Disable)[8]
Bit
Pin#
Name
Default
Pin Description
Bit 7
19
PCI7
1
(Active/Inactive)
Bit 6
18
PCI6
1
(Active/Inactive)
Bit 5
17
PCI5
1
(Active/Inactive)
Bit 4
15
PCI4
1
(Active/Inactive)
Bit 3
14
PCI3
1
(Active/Inactive)
Bit 2
12
PCI2
1
(Active/Inactive)
Bit 1
11
PCI1
1
(Active/Inactive)
Bit 0
10
PCI0
1
(Active/Inactive)
Note:
8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Document #: 38-07171 Rev. *A
Page 7 of 16
PRELIMINARY
W209C
Byte 3: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
31
DCLK
1
(Active/Inactive)
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
47
APIC
1
(Active/Inactive)
Bit 2
-
Reserved
0
Reserved
Bit 1
-
Reserved
1
Reserved
Bit 0
-
Reserved
0
Reserved
Byte 4: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Function
Bit 7
-
SEL3
0
See Table 4
Bit 6
-
SEL2
0
See Table 4
Bit 5
-
SEL1
0
See Table 4
Bit 4
-
SEL0
0
See Table 4
Bit 3
-
FS(0:4) Override
0
0 = Select operating frequency by FS(0:4) strapping
1 = Select operating frequency by SEL(0:4) bit settings
Bit 2
-
SEL4
0
See Table 4
Bit 1
-
Reserved
1
Reserved
Bit 0
-
Test Mode
0
0 = Normal
1 = Three-stated
Byte 5: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
-
Reserved
0
Reserved
Bit 1
-
Reserved
0
Reserved
Bit 0
-
Reserved
0
Reserved
Byte 6: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
-
Reserved
1
Reserved
Bit 1
-
Reserved
1
Reserved
Bit 0
-
Reserved
0
Reserved
Document #: 38-07171 Rev. *A
Page 8 of 16
PRELIMINARY
W209C
Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Data Byte 4, Bit 3 = 1
Bit 2
SEL_4
Bit 7
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU
SDRAM
3V66
PCI
APIC
0
0
0
0
0
75.3
113.0
75.3
37.6
18.8
OFF
0
0
0
0
1
95.0
95.0
63.3
31.6
15.8
–0.6%
0
0
0
1
0
129.0
129.0
86.0
43.0
21.5
OFF
0
0
0
1
1
150.0
113.0
75.3
37.6
18.8
OFF
0
0
1
0
0
150.0
150.0
100.0
50.0
25.0
OFF
0
0
1
0
1
110.0
110.0
73.0
36.6
18.3
OFF
0
0
1
1
0
140.0
140.0
93.3
46.7
23.3
OFF
0
0
1
1
1
144.0
108.0
72.0
36.0
18.0
OFF
0
1
0
0
0
68.3
102.5
68.3
34.1
17.0
OFF
0
1
0
0
1
105.0
105.0
70.0
35.0
17.5
OFF
0
1
0
1
0
138.0
138.0
92.0
46.0
23.0
OFF
0
1
0
1
1
140.0
105.0
70.0
35.0
17.5
OFF
0
1
1
0
0
66.8
100.2
66.8
33.4
16.7
±0.45%
0
1
1
0
1
100.2
100.2
66.8
33.4
16.7
±0.45%
0
1
1
1
0
133.6
133.6
89.1
44.4
22.2
±0.45%
0
1
1
1
1
133.6
100.2
66.8
33.4
16.7
±0.45%
1
0
0
0
0
157.3
118.0
78.6
39.3
19.6
OFF
1
0
0
0
1
160.0
120.0
80.0
40.0
20.0
OFF
1
0
0
1
0
146.6
110.0
73.3
36.6
18.3
OFF
1
0
0
1
1
122.0
91.5
61.0
30.5
15.2
–0.6%
1
0
1
0
0
127.0
127.0
84.6
42.3
21.1
OFF
1
0
1
0
1
122.0
122.0
81.3
40.6
20.3
–0.6%
1
0
1
1
0
117.0
117.0
78.0
39.0
19.5
OFF
1
0
1
1
1
114.0
114.0
76.0
38.0
19.0
OFF
1
1
0
0
0
80.0
120.0
80.0
40.0
20.0
OFF
1
1
0
0
1
78.0
117.0
78.0
39.0
19.5
OFF
1
1
0
1
0
166.0
166.0
55.3
27.6
13.8
OFF
1
1
0
1
1
160.0
160.0
53.3
26.7
13.3
OFF
1
1
1
0
0
66.6
100.0
66.6
33.3
16.6
–0.6%
1
1
1
0
1
100.0
100.0
66.6
33.3
16.6
–0.6%
1
1
1
1
0
133.3
133.3
88.9
44.4
22.2
–0.6%
1
1
1
1
1
133.3
100.0
66.6
33.3
16.6
–0.6%
Document #: 38-07171 Rev. *A
Spread
Spectrum
Page 9 of 16
PRELIMINARY
W209C
DC Electrical Characteristics[9]
DC parameters must be sustainable under steady state (DC) conditions.
Absolute Maximum DC Power Supply
Parameter
Description
Min.
Max.
Unit
VDDQ3
3.3V Core Supply Voltage
–0.5
4.6
V
VDDQ2
2.5V I/O Supply Voltage
–0.5
3.6
V
TS
Storage Temperature
–65
150
°C
Min.
Max.
Unit
Absolute Maximum DC I/O
Parameter
Description
Vi/o3
3.3V Core Supply Voltage
–0.5
4.6
V
Vi/o3
2.5V I/O Supply Voltage
–0.5
3.6
V
ESD prot.
Input ESD Protection
2000
V
Note:
9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07171 Rev. *A
Page 10 of 16
PRELIMINARY
W209C
DC Operating Requirements
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
VDD3
3.3V Core Supply Voltage
3.3V±5%
3.135
3.465
V
VDDQ3
3.3V I/O Supply Voltage
3.3V±5%
3.135
3.465
V
VDDQ2
2.5V I/O Supply Voltage
2.5V±5%
2.375
2.625
V
Vih3
3.3V Input High Voltage
VDD3
2.0
VDD + 0.3
V
Vil3
3.3V Input Low Voltage
VSS – 0.3
0.8
V
+5
µA
VDD3 = 3.3V±5%
[10]
0<Vin<VDD3
–5
Voh2
2.5V Output High Voltage
Ioh=(–1 mA)
2.0
Vol2
2.5V Output Low Voltage
Iol=(1 mA)
Voh3
3.3V Output High Voltage
Ioh=(–1 mA)
Vol3
3.3V Output Low Voltage
Iol=(1 mA)
Iil
Input Leakage Current
VDDQ2 = 2.5V±5%
V
0.4
V
VDDQ3 = 3.3V±5%
2.4
V
0.4
V
VDDQ3 = 3.3V±5%
Vpoh3
PCI Bus Output High Voltage
Ioh=(–1 mA)
Vpol3
PCI Bus Output Low Voltage
Iol=(1 mA)
Cin
Input Pin Capacitance
Cxtal
Xtal Pin Capacitance
Cout
Output Pin Capacitance
Lpin
Pin Inductance
Ta
Ambient Temperature
IOL
Output Low Current
IOH
Output High Current
2.4
V
0.55
V
5
pF
22.5
pF
6
pF
0
7
nH
No Airflow
0
70
°C
PCI0:7
VOL = 1.5V
20
40
90
mA
REF2X/FS3
VOL = 1.5V
20
40
90
mA
48 MHz
VOL = 1.5V
20
40
90
mA
24 MHz
VOL = 1.5V
20
40
90
mA
13.5
SDRAM0:12
VOL = 1.5V
60
100
160
mA
CPU0:1
VOL = 1.25V
25
50
95
mA
PCI0:7
VOH= 1.5V
20
40
90
mA
REF2X/FS3
VOH= 1.5V
20
40
90
mA
48 MHz
VOH= 1.5V
20
40
90
mA
24 MHz
VOH= 1.5V
20
40
90
mA
SDRAM0:12
VOH= 1.5V
60
100
160
mA
CPU0:1
VOH= 1.25V
25
50
95
mA
Note:
10. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
Document #: 38-07171 Rev. *A
Page 11 of 16
PRELIMINARY
W209C
AC Electrical Characteristics[9]
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Parameter
Description
66.6-MHz Host
100-MHz Host
133-MHz Host
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Notes
TPeriod
Host/CPUCLK Period
15.0
15.5
10.0
10.5
7.5
8.0
ns
11
THIGH
Host/CPUCLK High Time
5.2
N/A
3.0
N/A
1.87
N/A
ns
14
TLOW
Host/CPUCLK Low Time
5.0
N/A
2.8
N/A
1.67
N/A
ns
15
TRISE
Host/CPUCLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
Host/CPUCLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
SDRAM CLK Period
10.0
10.5
10.0
10.5
10.0
10.5
ns
11
THIGH
SDRAM CLK High Time
3.0
N/A
3.0
N/A
3.0
N/A
ns
14
TLOW
SDRAM CLK Low Time
2.8
N/A
2.8
N/A
2.8
N/A
ns
15
TRISE
SDRAM CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
SDRAM CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
APIC 33-MHz CLK Period
30.0
N/A
30.0
N/A
30.0
N/A
ns
11
THIGH
APIC 33-MHz CLK High Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
14
TLOW
APIC 33-MHz CLK Low Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
15
TRISE
APIC CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
APIC CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
3V66 CLK Period
15.0
16.0
15.0
16.0
15.0
16.0
ns
11, 13
THIGH
3V66 CLK High Time
5.25
N/A
5.25
N/A
5.25
N/A
ns
14
TLOW
3V66 CLK Low Time
5.05
N/A
5.05
N/A
5.05
N/A
ns
15
TRISE
3V66 CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TFALL
3V66 CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TPeriod
PCI CLK Period
30.0
N/A
30.0
N/A
30.0
N/A
ns
11, 12
THIGH
PCI CLK High Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
14
TLOW
PCI CLK Low Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
15
TRISE
PCI CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TFALL
PCI CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
tpZL, tpZH
Output Enable Delay (All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tpLZ, tpZH
Output Disable Delay
(All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tstable
All Clock Stabilization from
Power-Up
3
ms
3
3
Notes:
11. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
12. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
13. TLOW is measured at 0.4V for all outputs.
14. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and
operating within specification.
15. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.
Document #: 38-07171 Rev. *A
Page 12 of 16
PRELIMINARY
W209C
Group Skew and Jitter Limits
Output Group
Pin-Pin Skew Max.
Cycle-Cycle Jitter
Duty Cycle
Nom Vdd
Skew, Jitter
Measure
Point
Typical Output
Impedance
CPU
175 ps
250 ps
45/55
2.5V
1.25V
21 Ω
SDRAM
250 ps
250 ps
45/55
3.3V
1.5V
14 Ω
APIC
250 ps
500 ps
45/55
2.5V
1.25V
16 Ω
48MHz
250 ps
500 ps
45/55
3.3V
1.5V
21 Ω
3V66
175 ps
500 ps
45/55
3.3V
1.5V
14 Ω
PCI
500 ps
500 ps
45/55
3.3V
1.5V
14 Ω
REF
N/A
1000 ps
45/55
3.3V
1.5V
11 Ω
Output
Buffer
Test Point
Test Load
Clock Output Wave
TPERIOD
Duty Cycle
THIGH
2.0
2.5V Clocking
Interface
1.25
0.4
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
3.3V Clocking
Interface
1.5
0.4
TLOW
TRISE
TFALL
Figure 8. Output Buffer
Ordering Information
Ordering Code
W209C
Package Name
H
Package Type
48-pin SSOP (300 mils)
Intel is a registered trademark of Intel Corporation.
Document #: 38-07171 Rev. *A
Page 13 of 16
PRELIMINARY
W209C
Layout Diagram
+3.3V Supply
+2.5V Supply
FB
FB
VDDQ2
VDDQ3
C4
C1
G
C2
G
G
VDDQ3
5Ω
C5 G
10 µF
G
G
C1
C3
1 G
2 V
3 G
4
5 G
6 V
7 G
8
9 G
10
11
12
13 G
14
15 G
16 V
17 G
18
19
20 G
21
22
23
24 G
10 µF
0.005 µf
G
G
48
47
V 46
G 45
44
G
43
V
42
G
41
40
39
G 38
37
36
G 35
V 34
G
33
32
31
G 30
29
28
VDDQ3
Core V 27
G
26
G 25
V
C2
µ
G
G
W209C
G
0.005 µF
G
G
G
G
G C6
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz)
C1 & C3 = 10–22 µF
C2 & C4 = 0.005 µF
G = VIA to GND plane layer
C5 = 47 µF
C6 = 0.1 µF
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
Document #: 38-07171 Rev. *A
Page 14 of 16
PRELIMINARY
W209C
Package Diagram
48-Pin Shrink Small Outline Package (SSOP, 300 mils)
Document #: 38-07171 Rev. *A
Page 15 of 16
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
W209C
Document Title: W209C Frequency Generator for Integrated Core Logic with 133-MHz FSB
Document Number: 38-07171
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110281
11/05/01
SZV
Change from Spec number: 38-00845 to 38-07171
*A
122812
12/21/02
RBI
Add Power up Requirements to Electrical Characteristics Information
Document #: 38-07171 Rev. *A
Page 16 of 16