ETC WF4M16

WF4M16-XDTX5
HI-RELIABILITY PRODUCT
2x2Mx16 5V FLASH MODULE
ADVANCED*
FEATURES
■ Data Polling and Toggle Bit feature for detection of program
or erase cycle completion.
■ Access Time of 90, 120, 150ns
■ Packaging:
• 56 Lead, Hermetic Ceramic, 0.520" CSOP (Package 213).
Fits standard 56 SSOP footprint.
■ Supports reading or programming data to a sector not being
erased.
■ Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation, Separate Power and Ground Planes to
improve noise immunity
■ Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8 chip
• Any combination of sectors can be erased. Also supports
full chip erase.
■ Minimum 100,000 Write/Erase Cycles Minimum
■ Organized as two banks of 2Mx16; User Configurable as
4 x 2Mx8
■ Commercial, Industrial, and Military Temperature Ranges
■ 5 Volt Read and Write. 5V ± 10% Supply.
■ Low Power CMOS
FIG. 1
■ RESET pin resets internal state machine to the read mode.
■ Ready/Busy (RY/BY) output for direction of program or erase
cycle completion.
*
This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
Note: For programming information refer to Flash Programming 16M5
Application Note.
PIN CONFIGURATION FOR WF4M16-XDTX5
PIN DESCRIPTION
56 CSOP
TOP VIEW
CS1
A12
A13
A14
A15
NC
CS2
NC
A20
A19
A18
A17
A16
VCC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
VCC
November 1999 Rev.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
VCC
I/O9
I/O1
I/O8
I/O0
A0
NC
CS3
CS4
I/O2
I/O10
I/O3
I/O11
GND
I/O0-15
Data Inputs/Outputs
BLOCK DIAGRAM
A0-20
Address Inputs
I/O8-15
WE
Write Enable
I/O0-7
RESET
WE
OE
A0-20
RY/BY
2M x 8
2M x 8
CS 1
CS 2
CS 3
CS 4
2M x 8
2M x 8
CS1-4
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
RY/BY
Ready/Busy
RESET
Reset
NOTE:
1. RY/BY is an open drain output and should be pulled-up to Vcc with an
external resistor.
2. CS1 and CS 3 control the same data bus. Reads cannot be done with CS1
and CS3 both active. CS 2 and CS 4 control the same data bus. Reads
cannot be done with CS2 and CS4 both active.
3. Address compatible with Intel 2M8 56 SSOP.
1
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WF4M16-XDTX5
CAPACITANCE
(TA = +25°C)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Ratings
Unit
Voltage on Any Pin Relative to VSS
VT
-2.0 to +7.0
V
Power Dissipation
PT
8
W
Tstg
-65 to +125
°C
IOS
100
100,000 min
mA
cycles
Storage Temperature
Short Circuit Output Current
Endurance - Write/Erase Cycles
(Mil Temp)
Data Retention (Mil Temp)
20
Parameter
Symbol
Conditions
Max
Unit
OE capacitance
COE
VIN = 0 V, f = 1.0 MHz
45
pF
WE capacitance
CWE
VIN = 0 V, f = 1.0 MHz
45
pF
CS capacitance
CCS
VIN = 0 V, f = 1.0 MHz
15
pF
Data I/O capacitance
CI/O
VI/O = 0 V, f = 1.0 MHz
25
pF
Address input capacitance
CAD
VIN = 0 V, f = 1.0 MHz
45
pF
This parameter is guaranteed by design but not tested.
years
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Supply Voltage
V CC
4.5
5.5
Unit
V
Ground
V SS
0
0
V
Input High Voltage
V IH
2.0
V CC + 0.5
V
Input Low Voltage
V IL
-0.5
+0.8
V
Operating Temperature (Mil.)
TA
-55
+125
°C
Operating Temperature (Ind.)
TA
-40
+85
°C
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Conditions
Min
Max
Unit
µA
I LI
V CC = 5.5, V IN = GND to VCC
10
I LOx32
V CC = 5.5, V IN = GND to VCC
10
µA
VCC Active Current for Read (1)
ICC1
CS = VIL, OE = VIH, f = 5MHz, VCC = 5.5
82
mA
V CC Active Current for Program or Erase (2)
I CC2
CS = VIL, OE = VIH, VCC = 5.5
122
mA
V CC Standby Current
I CC3
V CC = 5.5, CS = V IH , f = 5MHz
8.0
mA
Output Low Voltage
V OL
I OL = 12.0 mA, V CC = 4.5
0.45
V
Output High Voltage
V OH
I OH = -2.5 mA, V CC = 4.5
Low V CC Lock-Out Voltage
V LKO
4.2
V
0.85xVcc
3.2
V
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE at VIH .
2. Icc active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions VIL = 0.3V, VIH = V CC - 0.3V
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2
WF4M16-XDTX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 5.0V, T A = -55°C to +125°C)
Parameter
Symbol
-90
Min
Write Cycle Time
tAVAV
tWC
-120
Max
90
Min
-150
Max
120
Min
Unit
Max
150
ns
Chip Select Setup Time
tELWL
tCS
0
0
0
ns
Write Enable Pulse Width
tWLWH
tWP
45
50
50
ns
Address Setup Time
tAVWL
tAS
0
0
0
ns
Data Setup Time
tDVWH
tDS
45
50
50
ns
Data Hold Time
tWHDX
tDH
0
0
0
ns
ns
Address Hold Time
tWLAX
tAH
45
50
50
Write Enable Pulse Width High
tWHWL
tWPH
20
20
20
Duration of Byte Programming Operation (1)
tWHWH1
300
300
300
µs
Sector Erase (2)
tWHWH2
15
15
15
sec
Read Recovery Time before Write
tGHWL
0
V CC Setup Time
t VCS
50
0
44
256
Output Enable Hold Time (4)
10
tOEH
µs
50
44
Chip Erase Time (3)
µs
0
50
Chip Programming Time
ns
256
10
44
sec
256
sec
10
ns
NOTES:
1. Typical value for t WHWH1 is 7µs.
2. Typical value for t WHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
(VCC = 5.0V, T A = -55°C to +125°C)
Parameter
Symbol
-90
Min
Read Cycle Time
-120
Max
90
Min
-150
Max
120
Min
Unit
Max
t AVAV
t RC
150
ns
Address Access Time
t AVQV
t ACC
90
120
150
Chip Select Access Time
t ELQV
t CE
90
120
150
ns
Output Enable to Output Valid
t GLQV
t OE
40
50
55
ns
ns
Chip Select High to Output High Z (1)
t EHQZ
t DF
20
30
35
ns
Output Enable High to Output High Z (1)
t GHQZ
t DF
20
30
35
ns
Output Hold from Addresses, CS or OE Change,
whichever is First
t AXQX
t OH
0
0
0
ns
1. Guaranteed by design, not tested.
3
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WF4M16-XDTX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
-90
Min
-120
Max
Min
-150
Max
Min
Unit
Max
Write Cycle Time
t AVAV
t WC
90
120
150
Write Enable Setup Time
t WLEL
t WS
0
0
0
ns
Chip Select Pulse Width
t ELEH
t CP
45
50
50
ns
Address Setup Time
t AVEL
t AS
0
0
0
ns
Data Setup Time
t DVEH
t DS
45
50
50
ns
Data Hold Time
t EHDX
t DH
0
0
0
ns
Address Hold Time
t ELAX
t AH
45
50
50
ns
t EHEL
t CPH
20
Chip Select Pulse Width High
20
ns
20
ns
Duration of Byte Programming Operation (1)
t WHWH1
300
300
300
µs
Sector Erase Time (2)
t WHWH2
15
15
15
sec
Read Recovery Time
t GHEL
44
sec
256
sec
0
Chip Programming Time
0
44
Chip Erase Time (3)
256
Output Enable Hold Time (4)
t OEH
10
µs
0
44
256
10
10
ns
NOTES:
1. Typical value for t WHWH1 is 7µs.
2. Typical value for t WHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
FIG. 2
AC TEST CONDITIONS
AC TEST CIRCUIT
Parameter
I OL
Current Source
VZ
D.U.T.
≈ 1.5V
(Bipolar Supply)
C eff = 50 pf
I OH
Current Source
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4
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
NOTES:
VZ is programmable from -2V to +7V.
IOL & I OH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of V OH and V OL.
IOL & I OH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
WF4M16-XDTX5
FIG. 3
5
Outputs
WE
OE
CS
High Z
tACC
tCE
tOE
Addresses Stable
Addresses
tRC
Output Valid
tOH
tDF
High Z
AC WAVEFORMS FOR READ OPERATIONS
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WF4M16-XDTX5
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
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6
A0H
tDH
tWPH
Data
tDS
tCS
WE
OE
5.0 V
tWP
tGHWL
CS
tWC
Addresses
5555H
tAS
PA
PD
tAH
tWHWH1
Data Polling
D7
PA
DOUT
tOE
tCE
tRC
tDF
WRITE/ERASE/PROGRAM
OPERATION, WE CONTROLLED
tOH
FIG. 4
WF4M16-XDTX5
FIG. 5
AAH
tDS
tDH
tVCS
VCC
Data
WE
OE
CS
Addresses
tGHWL
tCS
tWP
tAS
tWPH
55H
2AAAH
5555H
tAH
5555H
80H
5555H
AAH
2AAAH
55H
SA
10H/30H
AC WAVEFORMS CHIP/SECTOR
ERASE OPERATIONS
NOTE:
1. SA is the sector address for Sector Erase.
7
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WF4M16-XDTX5
FIG. 6
AAH
tDS
tCS
tWP
8
VCC
Data
WE
tVCS
tGHWL
OE
CS
Addresses
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tDH
tWPH
55H
2AAAH
tAS
5555H
tAH
5555H
80H
5555H
AAH
2AAAH
55H
SA
10H/30H
AC WAVEFORMS FOR DATA POLLING
DURING EMBEDDED ALGORITHM OPERATIONS
WF4M16-XDTX5
FIG. 7
A0H
tDH
tCPH
5.0 V
tDS
Data
CS
OE
tWS
tWC
WE
Addresses
5555H
tGHEL
tCP
tAS
PA
PD
tAH
tWHWH1
Data Polling
D7
PA
DOUT
ALTERNATE CS CONTROLLED
PROGRAMMING OPERATION TIMINGS
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
9
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WF4M16-XDTX5
PACKAGE 213:
56 LEAD, DUAL CAVITY CERAMIC SOP
3.50 (0.138)
± 0.83 (0.032)
23.63 (0.930) ± 0.25 (0.010)
0.18 (0.007)
± 0.03 (0.001)
21.59 (0.850) TYP
1.58 (0.062) TYP
0.51 (0.020)
± 0.13 (0.005)
10.93 (0.430)
± 0.13 (0.005)
12.96 (0.510)
± 0.13 (0.005)
16.13 (0.635)
± 0.13 (0.005)
0.51 (0.020) TYP
+
PIN 1 IDENTIFIER
0.25 (0.010)
± 0.05 (0.002)
0.80 (0.031) TYP
0.51
(0.020) TYP
SEE DETAIL "A"
R 0.18
(0.007)
4.57 (0.180)
MAX
0° / -4°
DETAIL "A"
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
FIG. 8
ALTERNATE PIN CONFIGURATION FOR WF4M16W-XDTX5
PIN DESCRIPTION
56 CSOP
TOP VIEW
CS1
A11
A12
A13
A14
NC
CS2
A20
A19
A18
A17
A16
A15
VCC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
RESET
A10
A9
A8
A0
A1
A2
A3
A4
A5
A6
GND
A7
VCC
I/O9
I/O1
I/O8
I/O0
NC
NC
CS3
CS4
I/O2
I/O10
I/O3
I/O11
GND
I/O0-15
Data Inputs/Outputs
BLOCK DIAGRAM
A0-20
Address Inputs
I/O8-15
WE
Write Enable
I/O0-7
RESET
WE
OE
A0-20
RY/BY
2M x 8
2M x 8
CS 1
CS 2
CS 3
CS 4
2M x 8
2M x 8
CS1-4
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
RY/BY
Ready/Busy
RESET
Reset
NOTE:
1. RY/BY is an open drain output and should be pulled-up to Vcc with an
external resistor.
2. CS 1 and CS3 control the same data bus. Reads cannot be done with CS 1
and CS3 both active. CS 2 and CS4 control the same data bus. Reads
cannot be done with CS 2 and CS4 both active.
3. Address compatible with Intel 1M16 56 SSOP, with the addition of A20
at pin 8. Also refer to Note 2.
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WF4M16-XDTX5
ORDERING INFORMATION
W F 4M16 - XXX DT X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5=5V
DEVICE GRADE:
M = Military, 883 Screened
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
PACKAGE TYPE:
DT = 56 Lead Dual Cavity CSOP (Package 213)
fits standard 56 SSOP footprint
ACCESS TIME (ns)
ORGANIZATION, 2M x 16
User configurable as 4 x 2M x 8
Flash
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11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com