WL800 2.5GHz Frequency Synthesiser Preliminary Information DS4583 1.6 October1997 The WL800 is a low power single chip frequency synthesiser. The circuit is fabricated on Mitel Semiconductor HG process and operates from a supply voltage of 2.7 - 3.6V. It is designed to work with the Mitel Semiconductor WL600C RF and IF circuit and the WL102 WLAN controller chip which together make up the DE6038 frequency hopping Wireless Local Area Network (WLAN) transceiver. PIN 1 IDENT FEATURES ■ Low power consumption ■ 2.5GHz input TQFP 32 ■ 144 frequencies, 1MHz steps (20MHz crystal) ■ Forms complete phase locked loop using external VCO and loop components ■ Serially programmed via 3 wire bus ■ Contains anti-modulation circuit Fig.1 Pin connections - top view RELATED DOCUMENTS WL600C, WL102 datasheets ■ Part of DE6038 Chip-set (WL600C, WL102) ORDERING INFORMATION WL800/KG/TP1R ABSOLUTE MAXIMUM RATINGS Supply Voltage Vcc 4VDC Transmit/Receive and -0.5VDC to Vcc +0.5VDC Standby Input Prescaler Inputs Pins 30 &31 No DC. Externally Capacitively Coupled. Output Current (any output) TBD mA Junction temperature Tj 150°C ESD protection: 2kV Operating temperature -20 to +85°C WL800 DEVICE PIN OUT PIN 2 REFERENCE TYPE DESCRIPTION 1 2 VCC1 CS-DATA VCC IN Power for serial data bus Channel Data in (Synth Programming) 3 4 CS-CLK CS-LOADB 5 6 STDBYB VEE1 7 8 ISET ICP 9 10 VEE3 TXD 11 12 IN IN IN GND Data Clock (Synth Programming) Data Enable (Synth Programming) Power down control Active = Logic 1 Standby = logic 0 Ground connection Set modulation current Set charge pump current GND IN Ground connection Modulation data in COM CAP RCOMP OUT Compensation capacitor for modulation data Resistor for V/I converter 13 14 IDOUT TXRXB OUT IN Modulation data out Transmit/Receive control Transmit = Logic 1 Receive = Logic 0 15 16 VARICAP VCC3 OUT VCC Control V to varicap in VCO Power for charge pump and loop amplifier and modulator 17 18 LOOPFILTER CPUMPREF OUT Loop filter out (Loop Filter Components) Charge pump reference voltage 19 20 CPUMPOUT VEE2 OUT GND Charge pump out (Loop Filter Components) Ground connection 21 22 SYSCLK XTAL OUT Reference (system) clock out Crystal connection (Differential) 23 24 XTALB VCC2 25 26 FREF LKCAP OUT Reference frequency monitor Lock detect capacitor 27 28 LCKDETB FV OUT OUT Lock detect output VCO frequency / (NM+A) monitor 29 30 VEE5 VCC GND VCC Ground connection Power for prescaler, AM counter Ref divider, phase detector and 31 VCOIPB IN lock detector Prescaler IN- 32 VCOIP IN Prescaler IN+ VCC Crystal connection (Differential) Power for reference oscillator WL800 21 12 23 22 REF RCOMP XTALB SYSCLK XTAL1 B XTAL2 OUT 1,16,24,30 Vcc CAP BUFFER VCAP CHARGE COMP COMPCAP 6,9,20,29 14 Vee TXRXB 28 FV 11 IDOUT 13 STANDBY STDBYB 5 DATA BUFFER DIN TXD MOD COMP 10 REF OUT BUFFER REFERENCE OSC DIVIDE BY 20 FREF 25 ISET 7 VCOIP 32 VCOIPB 31 LKCAP 26 PRE AMP PRE-SCALER A COUNTER M COUNTER PHASE DET & CHARGE PUMP INPUT REGISTER DATA CS-DATA 2 CLK CS-CLK 3 ENABLEB CS-LOADB 4 ICP 8 LOCK DETECT 1/3 CPUMP REF 18 CPUMP OUT 19 LKDETB LCKDETB 27 LOOP FILTER 17 VARICAP 15 Fig. 1 WL800 block diagram 3 WL800 ELECTRICAL CHARACTERISTICS These characteristics are guaranteed over the following conditions (unless otherwise stated): TAMB = -20°C, to +85°C, Vcc = 2.7V to 3.6V Characteristic Value MIN Unit TYP MAX Transmit Receive 37 35 50 50 mA mA Supply current in standby 3 5 mA 0 0.4 V 0.8Vcc Vcc 1 V µA 20 Condition Supply current (total) PROGRAMMING INPUTS Logic low voltage Logic high voltage Input current Input level high Data clock frequency (1/tclock) Data/Enable set up time (t set up) 10 MHz ns See Fig. 2 See Fig. 2 Enable hold time (t enable) Positive clock pulse width (tp) 10 20 ns ns See Fig. 2 See Fig. 2 Negative clock pulse width (t neg) 20 ns See Fig. 2 STANDBY INPUT Logic low input voltage 0 0.8 V Circuit powered down Vcc 150 V µA Circuit powered up Circuit powered up -150 µA µs Circuit powered down *References operational (see note 1) 0 0.8 V Receive mode Vcc -0.7 Vcc 10 V µA Transmit mode Logic high input voltage Input current Vcc -0.7 100 Standby to operate time TX/RX INPUT Logic low input voltage Logic high input voltage Input current 3 REFERENCE OUTPUT Reference output frequency MHz Reference clock output voltage Reference output impedance 200 250 600 300 Mark Space ratio Rise time -2% 50/50 +2% 15 Fall time Crystal Drive Levels required 4 20 15 200 mVp-p Ohms With 20MHz crystal With 15pF load With 15pF load ns ns mV Pins 22,23 differential WL800 ELECTRICAL CHARACTERISTICS (continued) These characteristics are guaranteed over the following conditions (unless otherwise stated): TAMB = -20°C, to +85°C, Vcc = 2.7V to 3.6V Characteristic Value Unit Condition MIN TYP MAX 80 110 150 µA Determined by application. On smoothing capacitor I out = 10µA I out = 0 µA LOCK DETECT CIRCUIT Smoothing capacitor charge/ discharge current Threshold voltage Output high voltage Vcc-0.3 1.8 Vcc V V Output low voltage Vee 0.5 V PHASE DETECTOR AND CHARGE PUMP Comparison frequency Charge pump output current 1 ±1 Up down current matching Reference voltage Vcc-1.05 MHz mA 5 % Vcc-0.7 V Divided crystal reference Rpin 8 = 10k CHARGE PUMP OP-AMP First Stage: High output voltage 2.4 V Low output voltage Second Stage: 0.3 Filter drive amplifier output current Filter drive amp output swing V ±1 mA 0.77 Vp-p PRESCALER Input drive voltage Maximum operating frequency 40 3 Input Impedance 200 mV rms GHz -100 +100 µA µA Rsource=20k 100 µA Set by external resistor on pin 7 200 nA µA Leakage Current Equal to 0.5 mod current 330Ω 0.5pF TRANSMIT DATA INPUT Logic low Logic high -60 +60 TX DATA OUT Logic 0 output current Logic 1 output current Output current in receive mode 25 50 25 5 WL800 ELECTRICAL CHARACTERISTICS (continued) These characteristics are guaranteed over the following conditions (unless otherwise stated): TAMB = -20°C, to +85°C, Vcc = 2.7V to 3.6V Characteristic Value MIN TYP Unit Condition MAX MOD. CURRENT INPUT Mod current set pin current 25 µA COMPENSATION CAP PIN Compensation current -25 µA Set by external resistor on 2 % pin 7. R=47k. Compensation capacitor 8.2nF Receive mode Compensation current matching Set by external resistor on pin 7. R = 47k Compensation capacitor voltage CPRef - CPRef CPRef V Compensation capacitor voltage 0.02 88 98 +0.02 +110 mV 1 MHz data, 32bits ‘0’ -120 -98 -88 mV 1 MHz data, 32bits ‘1’ VCAP CHARGE Settling Time 100 µs Receive mode Charging Current 20 mA Receive mode. Vcap initially at 0 V. Offset Voltage 15 mV Receive mode. +52.08 -52.08 nA nA Per 1us of databit 0 Per 1us of databit 1 1.666 mA for 32 bits(1) at 1MHz COMPENSATION VtoI (CAPBUFFER+RCOMP) Compensation current into Loop Filter Max. Compensation current CAPACITOR BUFFER Offset Voltage External Resistor RCOMP 15 mV 58000 Ohms Note: 1. Standby to operate time refers to the time for internal current references to become operational. 6 WL800 FUNCTIONAL DESCRIPTION Reference Frequency Phase Detectors The reference frequency is generated using a 20MHz crystal in conjunction with an on chip oscillator maintaining circuit. A buffer circuit provides a low level voltage output signal at the crystal frequency to drive the logic in the protocol and control chip. The crystal frequency is divided by 20 to provide the reference signal to the phase comparator. A conventional digital phase frequency detector incorporating dead band suppression is used in conjunction with a charge pump to steer the VCO. An internal op-amp maintains the charge pump pin at the same voltage as the charge pump reference by virtual earth principles. The op-amp is split into two parts with the first section having a relatively low current drive capability but including the high gain stages of the amplifier. The second stage has a controlled voltage gain of 1/3 but high input impedance and low output impedance. This minimises loading to the high output impedance of the first stage and provides sufficient drive current via the loop filter to maintain virtual earth at the charge pump output. The output from the first stage is designed to swing close to the positive and negative rails so as to provide maximum voltage swing to the varactor controlling the VCO. A compensating capacitor can be connected to this point to stabilise the amplifier. A lock detect output (active low) is provided to give an indication to the controller that the phase locked loop is locked, preventing transmission on illegal frequencies. Counters / Dividers An external oscillator is used to feed the input of the preamplifier in the synthesiser, (this isolates the counters from the oscillator and reduces the level of drive signal required by the synthesiser). The output of the preamplifier drives a dual modulus prescaler with ratios of 48/49, which in turn then drives the standard A-M counter arrangement. The A counter then provides the modulus control signal back to the prescaler. The counter system has an overall division ratio given by the formula MN+A where N is the lower divide ratio of the prescaler (48). The divide ratio of the M and A counters is programmable to allow the oscillator to be tuned over the required frequency range of 144 channels at 1MHz spacing. The M count ratio can be programmed over the range 49 to 52 and the A counter from 1 to 48 giving a total divide ratio from 2353 to 2544 which is greater than necessary to tune the required frequency range. Programming The programming data for the synthesiser is entered via a three wire serial data bus consisting of Enable, Clock and Data signals. The enable signal is taken low at the start of the programming sequence and remains low for the duration of the 8 serial data bits. A positive clock edge is required to strobe each data bit into the input register. When all 8 data bits are entered, the enable pin is taken high forcing the counters to zero and preloading the new count data when the counter is next clocked . The charge pump is disabled for a short period after the enable pin goes low to prevent glitch energy being transferred to the VCO. Antimodulation The WL800 contains a data buffer circuit which accepts transmit data from the CMOS controller circuit and converts the CMOS input to a tristate current output for driving the transmit spectrum shaping filter. The buffer gives zero current for a logic “1” input, a high current (+2I) for a logic “0” and a current midway between the two (+I) for use during the transmit amplifier power up/down period and during receive. This function prevents the synthesiser centring its frequency on either a logic “1” or “0” and removes the possibility of overmodulation at the start of a transmission. The amplitude of the output current and therefore modulation index of the radio is controlled by an external resistor connected to ground. A data compensation path is included which counteracts the tendency of the PLL to drift back to centre frequency when the data is non-white. This is achieved by charging an external capacitor with a current +I when data is low, and discharging it by a current -I when data is high. The capacitor voltage, which then represents an integrated form of the data is converted to a current via a buffer and an external resistor (RCOMP), and fed into the Loop Filter in addition to the Phase Detector output. During Receive Mode, the capacitor is charged to the Charge Pump Reference voltage. 7 WL800 WL800 PROGRAMMING Notes: Frequency MHz A counter Value M counter Value 6 bit binary A Value d0-d5 bit binary M Value d6-d7 2357 2358 5 6 49 49 101000 011000 00 00 2400 2401 48 1 49 50 000011 100000 00 10 2448 2449 48 1 50 51 000011 100000 10 01 2496 2497 48 1 51 52 000011 100000 01 11 2498 2499 2 3 52 52 010000 110000 11 11 2500 4 52 001000 11 1.The binary data is in reverse order. 2.The data is programmed with bit d7 first and d0 last d0 d1 d2 d3 d4 d5 d6 A counter d7 M counter TIMING DIAGRAM DATA CS_DATA t set up t neg t clock CLOCK CS_CLK CS_LOADB tp DATA ENABLE t enable Fig. 2 Timing diagram 8 WL800 CONTROL SIGNALS Control Line Logic ‘0’ Logic ‘1’ STDBYB TXRXB Standby Receive Active Transmit LCKDETB Locked Unlocked 9 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. 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