TOREX XC61FN3812TH

Series
Voltage Detectors ( Delay Circuit Built-In)
◆CMOS
■Applications
◆Mini Mold Package
●Microprocessor reset circuitry
◆Highly Accurate
2
●Memory battery back-up circuits
: ±2%
●Power-on reset circuits
◆Built-In Delay Circuit (1ms ~ 50ms)
●Power failure detection
(50ms ~ 200ms)
●System battery life and charge voltage monitors
(80ms ~ 400ms)
◆Low Power Consumption : 1.0µA (VIN = 2.0V)
●Delay circuitry
■General Description
■Features
The XC61F series are highly accurate, low power consumption voltage
detectors, manufactured using CMOS and laser trimming technologies. A
delay circuit is built-in to each detector.
Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-channel open drain output configurations are
available.
Since the delay circuit is built-in, peripherals are unecessary and high
density mounting is possible.
Highly Accurate
: Detect voltage ± 2%
Low Power Consumption : TYP 1.0 µA [ VIN=2.0V ]
Detect Voltage Range
: 1.6V ~ 6.0V in 0.1V increments
Operating Voltage Range : 0.7V ~ 10.0V
Detect Voltage Temperature Characteristics
: TYP± 100ppm/°C
Built-In Delay Circuit
: 1ms ~ 50ms, 50ms ~ 200ms, 80ms ~
400ms
Output Configuration
: N-channel open drain or CMOS
Ultra Small Packages
: SOT-23 (150mW) mini-mold
: SOT-89 (500mW) mini-power mold
: TO-92 (300mW)
* No parts are available with an accuracy of ± 1%
■Typical Application Circuits
■Typical Performance
Characteristic
R
VIN
VOUT
VSS
CMOS output
VIN
VOUT
100kΩ
AMBIENT TEMPERATURE vs.
TRANSIENT DELAY TIME
ＸＣ６１ＦＣ３０１２
VSS
N-channel open drain output
200
TDLY (msec)
VIN
VIN
150
100
50
-30
-10
10
30
50
70
Ambient Temp.: Ta(℃)
157
XC61F
Seires
■Pin Configuration
VIN
３
２
VSS
1
VOUT
1
VOUT
SOT-23
(TOP VIEW)
2
２
３
VIN
VSS
SOT-89
(TOP VIEW)
1
2
VOUT VIN
3
1
2
3
VSS
VIN
VSS
VOUT
TO-92 (T Type)
（TOP VIEW）
■Pin Assignment
PIN NUMBER
SOT-23
158
PIN
SOT-89 TO-92 (T) TO-92 (L) NAME
FUNCTION
3
2
2
1
V IN
Supply Voltage Input
2
3
3
2
VSS
Ground
1
1
1
3
VOUT
Output
TO-92 (L Type)
（TOP VIEW）
XC61F
Series
■Product Classification
●Ordering Information
XC61F
XXXXXXX
↑↑↑↑↑↑↑
a bbcd e f
DESIGNATOR
a
b
c
d
DESCRIPTION
Output Configuration :
C = CMOS
N = N-ch open drain
Detect Voltage (VDF) :
25 = 2.5V
38 = 3.8V
Output Delay :
1 = 50ms to 200ms
4 = 80ms to 400ms
5 = 1ms to 50ms
Detect Accuracy :
2 = within ± 2.0%
DESIGNATOR
e
f
DESCRIPTION
Package Type :
M = SOT-23
P = SOT-89
T = TO-92 (Regular)
L = TO-92 (Custom pin
Configuration)
2
Device Orientation :
R = Embossed Tape ( Right )
L = Embossed Tape ( Left )
H: Paper Tape (TO-92)
B: Bag (TO-92)
■Packaging Information
●SOT-23
0.4
+0.1
+0.1
-0.05
0.15 -0.05
+0.2
-0.1
0.2min
1.6
2.8±0.2
0∼0.1
（0.95）
1.1±0.1
1.9±0.2
2.9±0.2
159
XC61F
Seires
●SOT-89
1.5±0.1
0.8
min
2
4.25max
+0.15
-0.2
2.5±0.1
1.6
（0.4）
4.5±0.1
0.42±0.06
0.42±0.06
0.4
+0.03
-0.02
0.47±0.06
1.5±0.1 1.5±0.1
●TO-92
+0.35
-0.45
1.6±0.1
3.7±0.3
10.0min
4.8 -0.5
+0.4
4.65
0.45±0.1
+0.4
2.5 -0.1
160
+0.4
2.5 -0.1
0.4±0.05
XC61F
Series
■Marking
●SOT-23, SOT-89
q w e r
w
r
q
e
SOT-23
(TOP VIEW)
2
SOT-89
(TOP VIEW)
q Represents the integer of the Detect Voltage and the Output Configuration
CMOS output (XC61FC series)
DESIGNATOR
CONFIGURATION
CMOS
A
CMOS
B
CMOS
C
CMOS
D
CMOS
E
CMOS
F
CMOS
H
VOLTAGE (V)
0.w
1.w
2.w
3.w
4.w
5.w
6.w
N-channel open drain (XC61FN series)
DESIGNATOR
CONFIGURATION
VOLTAGE (V)
N-ch
K
0.w
N-ch
L
1.w
N-ch
M
2.w
N-ch
N
3.w
N-ch
P
4.w
N-ch
5.w
R
6.w
N-ch
S
w Represents the decimal number of the Detect Voltage
e Indicates the presence of delay time
DESIGNATOR
5
6
7
DESIGNATOR VOLTAGE (V) DESIGNATOR VOLTAGE (V)
q.5
q.0
5
0
q.6
q.1
6
1
q.7
q.2
7
2
q.3
q.8
8
3
q.9
q.4
9
4
DELAY TIME
50 to 200ms
80 to 400ms
1 to 50ms
r Represents the assembly lot no.
Based on internal standards
●TO-92
61C 1
61C 1
w Represents
w Re the Detect Voltage
q Represents the output
configuration
DESIGNATOR
D
DESIGNATOR OUTPUT CONFIGURATION
2 3 4 5 L
2 3 4 5
w
e
VOLTAGE（V）
C
CMOS
3
3
3
3.3
N
N-ch
5
5
0
5.0
6 7
6 7
w
r Indicates Delay Time
TO-92（T Type）
(TOP VIEW)
TO-92（L Type）
(TOP VIEW)
DESIGNATOR
DELAY TIME
1
50ms∼200ms
4
80ms∼400ms
5
1ms∼50ms
t Represents the Detect Voltage Accuracy
y Represents a least significant digit of
the produced year DESIGNATOR
DETECT VOLTAGE ACCURACY
2
within ±2%
DESIGNATOR PRODUCED YEAR
0
2000
1
2001
u Denotes the production lot number
0 to 9, A to Z repeated(G.I.J.O.Q.W excepted)
161
XC61F
Seires
■Block Diagram
■Absolute
■絶対最大定格
PARAMETER
(1)CMOS output
VIN
UNITS
VIN
12
V
IOUT
50
mA
CMOS
N-ch open drain
VOUT
VSS -0.3 ∼ VIN +0.3
V
VSS -0.3 ∼ 9
150
SOT-23
Continuous Total
Power Dissipation
Vref
Ta=25℃
RATINGS
Input Voltage
VOUT
Delay Circuit
SYMBOL
Output Current
Output Voltage
2
Maximum Ratings
500
Pd
SOT-89
mW
300
TO-92
Operating Ambient Temperature
Topr
-30 ∼ +80
O
C
Storage Temperature
Tstg
-40 ∼ +125
O
C
VSS
(2)N-channel open drain output
VIN
VOUT
Delay Circuit
Vref
VSS
■Electrical Characteristics
Ta＝25℃
PARAMETER
SYMBOL
Detect Voltage
V DF
Hysteresis Range
VHYS
Supply Current
I SS
Operating Voltage
V IN
CONDITIONS
IOUT
P-ch
Detect Voltage
Temperature Characteristics
Transient Delay Time
(VDR VOUT inversion)
VIN=1.5V
=2.0V
=3.0V
=4.0V
=5.0V
VDF=1.6V to 6.0V
VDS=0.5V
VIN=1.0V
=2.0V
=3.0V
=4.0V
=5.0V
VDS=2.1V
VIN=8.0V
( CMOS output )
MAX
VDF (T)
x 1.02
VDF
VDF
VDF
x 0.02
x 0.05
x 0.08
0.9
1.0
1.3
1.6
2.0
2.6
3.0
3.4
3.8
4.2
10.0
0.7
2.2
7.7
10.1
11.5
13.0
CIRCUIT
V
1
V
1
µA
2
V
1
3
mA
4
± 100
VIN changes from
0.6V to 10V
UNITS
-10.0
∆ VDF
∆ Topr • VDF
tDLY *
TYP
VDF (T)
x 0.98
N-ch
Output Current
MIN
VDF (T)
50
200
ppm/°C
-
ms
5
VDF(T)：established detect voltage value
Release Voltage : VDR = V DF + V HYS
* Transient Delay Time : 1ms to 50ms & 80ms to 400ms versions are also available.
Note : The power consumption during power-start to output being stable (release operation) is 2 µA greater than it is after that period
(completion of release operation) because of delay circuit through current.
162
XC61F
Series
■Functional Description
●Functional Description ( CMOS output )
q When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will gradually fall.
When a voltage higher than the detect voltage (VDF) is applied to VIN , output (VOUT) will be equal to the input at VIN.
Note that high impedeance exists at VOUT with the N-channel open drain configuration. If the pin is pulled up, VOUT will be
equal to the pull up voltage.
w When VIN falls below VDF , VOUT will be equal to the ground voltage (VSS) level (detect state).
Note that this also applies to N-channel open drain configurations.
e When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable.
Because the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up
voltage.
r When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to VSS until
VIN reaches the VDR level.
t Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit.
y Following transient delay time, VIN will be output at VOUT.
Note that high impedeance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.
2
Notes :
1.
2.
The difference between VDR and VDF represents the hysteresis range.
Propagation delay time (tDLY) represents the time it takes for VIN to appear at VOUT once the said voltage has exceeded the
VDR level.
●Timing Chart
■タイミングチャート
Input Voltage (VIN)
Detect Release Voltage (VDR)
y
Detect Voltage (VDF)
Minimum Operating Voltage(VMIN)
Ground Voltage (VSS)
Output Voltage (VOUT)
Propagation Delay Time (tDLY)
Ground Voltage (VSS)
q
w
e
r
t
y
163
XC61F
Seires
■Directions for use
●Notes on Use
1.
2.
3.
2
4.
5.
6.
Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded.
When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur
as a result of voltage drops at RIN if load current (IOUT) exists.
It is therefore recommend that no resistor be added. ( refer to N.B. 1 - (1) below )
When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch
output configurations, oscillation may occur as a result of through current at the time of voltage release even if load
current (IOUT ) does not exist. ( refer to N.B. 1 - (2) below )
With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's
supply current flowing through the VIN pin.
If a resistor (RIN ) must be used, then please use with as small a level of input impedance as possible in order to control
the occurences of oscillation as described above.
Further, please ensure that RIN is less than 10kΩ and that CIN is more than 0.1µF (Diagram 1). In such cases, detect and
release voltages will rise due to voltage drops at RIN brought about by the IC's supply current.
Depending on circuit's operation, transient delay time of this IC can be widely changed due to upper limits or lower limits
of operational ambient temparature.
●N.B.
■備考
1. Oscillation
(1) Oscillation as a result of output current with the CMOS output configuration :
When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load
current (IOUT) will flow through RL. Because a voltage drop ( RIN x IOUT) is produced at the RIN resistor, located between
the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the
voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will
commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the
voltage level at the VIN pin will rise and release operations will begin over again.
Oscillation may occur with this " release - detect - release " repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Oscillation as a result of through current :
Since the XC61F series are CMOS ICS, through current will flow when the IC's internal circuit switching operates ( during
release and detect operations ). Consequently, oscillation is liable to occur during release voltage operations as a result
of output current which is influenced by this through current ( Diagram 3 ).
Since hysteresis exists during detect operations, oscillation is unlikely to occur.
RIN
XC61FN Series
VIN
RIN
VOUT
VIN
VSS
CIN
Diagram1. When using an input resistor
164
XC61FC Series
VOUT
VSS
CIN
XC61F
Series
RIN
XC61FC Series
RIN X IOUT
IOUT
VIN
Voltage drop
VOUT
VSS
RL
2
Diagram 2. Oscillation in relation to output current
RIN
XC61FC Series
XC61FN Series
RIN X IOUT
Voltage drop
VIN
VOUT
VSS
ISS*
(includes through current)
Diagram 3. Oscillation in relation to through current
165
XC61F
Seires
■Typical Performance Characteristics
(1) SUPPLY CURRENT vs. INPUT VOLTAGE
ＸＣ６１ＦＮ１６１２
Ta=80℃
2.0
-30℃
1.0
25℃
0
2
4
6
8
4.0
Supply Current: ISS (μA)
3.0
0.0
ＸＣ６１ＦＮ３５１２
ＸＣ６１ＦＮ２５１２
4.0
Supply Current: ISS (μA)
2
Supply Current: ISS (μA)
4.0
3.0
2.0
Ta=80℃
-30℃
1.0
25℃
0.0
10
0
Input Voltage: VIN (V)
2
4
6
8
3.0
2.0
25℃
1.6
VDF
1.5
-20
0
20
40
60
6
8
10
ＸＣ６１ＦＮ３５１２
2.7
VDR
2.6
VDF
2.5
2.4
2.3
-40
80
4
3.8
Detect, Release Voltage: VDF,VDR (V)
VDR
2
Input Voltage: VIN (V)
2.8
Detect, Release Voltage: VDF,VDR (V)
Detect, Release Voltage: VDF,VDR (V)
1.8
1.4
-40
0
Input Voltage: VIN (V)
(2) DETECT VOLTAGE, RELEASE VOLTAGE vs. AMBIENT TEMPERATURE
ＸＣ６１ＦＮ２５１２
ＸＣ６１ＦＮ１６１２
1.7
-30℃
1.0
0.0
10
Ta=80℃
-20
0
20
40
60
80
3.7
VDR
3.6
3.5
VDF
3.4
3.3
3.2
-40
Ambient Temp.: Ta(℃)
Ambient Temp.: Ta(℃)
-20
0
20
40
60
80
Ambient Temp.: Ta(℃)
(3) OUTPUT VOLTAGE vs. INPUT VOLTAGE
1.5
1.0
0.5
0.0
0
1
2
5
VIN-VOUT:100kΩ
Ｔa=-30℃
25℃
80℃
3
Output Voltage: VOUT (V)
2.0
Output Voltage: VOUT (V)
Output Voltage: VOUT (V)
4
VIN-VOUT:100kΩ
Ｔa=-30℃
25℃
80℃
2.5
ＸＣ６１ＦＮ３５１２
ＸＣ６１ＦＮ２５１２
ＸＣ６１ＦＮ１６１２
3.0
2
1
3
2
1
0
0
3
0
Input Voltage: VIN (V)
1
2
3
4
0
Input Voltage: VIN (V)
1400
VIN=1.5V
9
6
1.0V
3
1.0
1.5
2.0
1200
VIN =0.8V
1000
800
600
0.7V
400
200
0
0.2
3
4
5
ＸＣ６１ＦＮ２５１２
0
0.5
VDS (V)
166
Output Current: IOUT (μA)
Output Current: IOUT (mA)
Ta=25℃
12
2
30
Ta=25℃
Output Current: IOUT (mA)
15
1
Input Voltage: VIN (V)
(4) N-CHANNEL DRIVER OUTPUT CURRENT vs. VDS
ＸＣ６１ＦＮ１６１２
ＸＣ６１ＦＮ１６１２
0
0.0
VIN-VOUT:100kΩ
Ta=-30℃
25℃
80℃
4
0.4
0.6
VDS (V)
0.8
1.0
Ta=25℃
25
VIN =2.0V
20
15
1.5V
10
5
0
0.0
0.5
1.0
1.5
VDS (V)
2.0
2.5
XC61F
Series
(4) N-CHANNEL DRIVER OUTPUT CURRENT vs. VDS
ＸＣ６１ＦＮ３５１２
ＸＣ６１ＦＮ２５１２
ＸＣ６１ＦＮ３５１２
1400
60
Ta=25℃
VIN =0.8V
800
600
0.7V
400
200
0
0.0
0.2
0.4
0.6
0.8
50
2.5V
40
30
2.0V
20
1.5V
10
0
0.0
1.0
VIN =3.0V
Output Current: IOUT (μA)
Ta=25℃
1000
Output Current: IOUT (mA)
Output Current: IOUT (μA)
1200
0.5
1.0
1.5
VDS (V)
2.0
2.5
3.0
Ta=25℃
1200
VIN =0.8V
1000
800
0.7V
600
400
2
200
0
0.0
3.5
0.2
0.4
0.6
0.8
1.0
VDS (V)
VDS (V)
(5) N-CHANNEL DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE
25
Output Current: IOUT (mA)
80℃
25℃
7.5
5.0
2.5
0.0
0.0
0.5
1.0
Ta=-30℃
VDS=0.5V
Ta=-30℃
12.5
10.0
40
1.5
20
80℃
25℃
15
10
5
0
0.0
2.0
Output Current: IOUT (mA)
VDS=0.5V
Output Current: IOUT (mA)
ＸＣ６１ＦＮ３５１２
ＸＣ６１ＦＮ２５１２
ＸＣ６１ＦＮ１６１２
15.0
Input Voltage: VIN (V)
0.5
1.0
1.5
2.0
2.5
VDS=0.5V
35
Ta=-30℃
30
80℃
25
25℃
20
15
10
5
0
3.0
0
Input Voltage: VIN (V)
1.0
2.0
3.0
4.0
Input Voltage: VIN (V)
(6) P-CHANNEL DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE
ＸＣ６１ＦＣ４４１２
ＸＣ６１ＦＣ２７１２
20
Ta=25℃
18
VDS =2.1V
16
14
1.5V
12
10
1.0V
8
6
0.5V
4
2
Output Current: IOUT (mA)
Output Current: IOUT (mA)
20
0
Ta=25℃
18
VDS =2.1V
16
14
1.5V
12
10
1.0V
8
6
0.5V
4
2
0
0.0
2.0
4.0
6.0
8.0
10.0
0.0
Input Voltage: VIN(V)
2.0
4.0
6.0
8.0
10.0
Input Voltage: VIN(V)
(7) AMBIENT TEMPERATURE vs. TRANSIENT DELAY TIME
ＸＣ６１ＦＣ３０５２
ＸＣ６１ＦＣ３０４２
ＸＣ６１ＦＣ３０１２
400
200
50
40
100
TDLY (msec)
TDLY (msec)
TDLY (msec)
320
150
240
160
50
-30
-10
10
30
50
Ambient Temp.: Ta(℃)
70
80
-30
30
20
10
-10
10
30
50
Ambient Temp.: Ta(℃)
70
0
-30
-10
10
30
50
70
Ambient Temp.: Ta(℃)
167
XC61F
Seires
(8) INPUT vs. TRANSIENT DELAY TIME
ＸＣ６１ＦC２７１２
230
Ta=25℃
2
TDLY(msec)
200
170
140
110
80
50
0.0
2.0
4.0
6.0
8.0
Input Voltage: VIN (V)
168
10.0