EXAR XRD64L43

Preliminary
XRD64L43
Dual 10-Bit 40MSPS CMOS ADC
July 2003
APPLICATIONS
FEATURES
• 10-Bit Resolution
• Medical Imaging
• Two Monolithic Complete 10-Bit ADCs
• Instrumentation
•
•
•
•
•
•
•
•
•
•
•
40 MSPS Conversion Rate
• Data Aquisition Systems
On-Chip Track-and-Hold
• Digital Comunications
On-Chip Voltage Reference
BENEFITS
Low 5 pF Input Capacitance
•
•
•
•
TTL/CMOS Outputs
Tri-State Output Buffers
Single +3.0V Power Supply Operation
Low Power Dissipation: 200mW-typ @ 2.7V
Reduction of Components
Reduction of System Cost
High Performance @ Low Power Dissipation
Long Term Time and Temperature Stability
Power Down Mode Less Than 5mW
75dB Crosstalk (fin=1.0MHz)
-40°C to +85°C Operation Temperature Range
GENERAL DESCRIPTION
The XRD64L43 is two 10-bit, monolithic, 40 MSPS
ADCs. Manufactured using a standard CMOS process, the XRD64L43 offers low power, low cost and
excellent performance. The on-chip track-and-hold
amplifier(T/H) and voltage reference (VREF) eliminate
the need for external active components, requiring only
an external ADC conversion clock for the application.
The XRD64L43 analog input can be driven with ease
due to the high input impedance.
The design architecture uses 17 time- interleaved 10bit SAR ADCs in each converter to achieve high
conversion rate of 40 MSPS minimum. In order to
insure and maintain accurate 10-bit operation with
respect to time and temperature, XRD64L43 incorporates an auto-calibration circuit which continuously
adjusts and matches the offset and linearity of each
ADC. This auto-calibration circuit is transparent to the
user after the initial 4.2ms calibration (168,000 initial clock
cycles).
The power dissipation is only 200mW at 40 MSPS with +2.7V
power supply.
The digital output data is straight binary format, and the tristate disable function is provided for common bus interface.
The XRD64L43 internal reference provides cost savings
and simplifies the design/development. The output voltage
of the internal reference is set by two external resistors. The
internal reference can be disabled if an external reference is
used for a power savings of 50mW.
ORDERING INFORMATION
Part Number
Package Type
Temperature Range
XRD64L43AIV
64-Lead LQFP
-40°C to +85°C
Rev. P1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017
XRD64L43
Preliminary
VINA+VINA-
10 Bit A/D's
Bandgap
ADC A
A/D 1a
VBG
VFBK
+
-
11
DA9 - DA0,
OTRA
VRHF
TRI_A
A/D 17a
VRHS
K
DIFF
SYNCO
PD
CKIN
CONTROL LOGIC
VRLS
10 Bit A/D's
ADC B
A/D 1b
VRLF
VCMO
11
+
-
A/D 17b
VINB+VINB-
Figure 1. XRD64L43 Simplified Block Diagram
Rev. P1.00
2
DB9 - DB0,
OTRB
TRI_B
OTRB
DIFF
32
DA0
TRI_B
31
DA1
16
DVDD
DGND
15
30
DA2
DGND
14
PD
AGND
13
29
DA3
12
28
DA4
11
27
DOVDD
3
10
26
DOGND
Rev. P1.00
9
AGND
8
25
DVDD
7
DB3
DGND
24
DGND
6
DB4
DOVDD
23
DA5
5
DB5
DOGND
22
DA6
4
DB6
DB2
21
DA7
3
DB7
DB1
20
DA8
2
DB8
DB0
19
DA9
1
DB9
SYNCO
18
OTRA
49
50
51
52
53
54
55
56
XRD64L43
VRLS
AGND
33
VRLF
AGND
34
VRLF
AVDD
35
VRHF
AVDD
36
VRHF
AGND
37
VRHS
VINA-
38
VFBK
VINA+
39
VBG
AGND
40
57
VINB+
41
58
VINB-
42
59
AGND
43
60
AGND
44
61
AVDD
45
62
AGND
46
63
DGND
47
64
VCM0
48
CKIN
17
XRD64L43
Preliminary
TRI_A
XRD64L43
Preliminary
PIN DESCRIPTION
Pin #
1
2
Symbol
VBG
Description
Bandgap Voltage Output
VFBK
Analog Reference Feedback
3
VRHS
Top Voltage Reference Sense
4
VRHF
Top Voltage Reference Force
5
VRHF
Top Voltage Reference Force
6
VRLF
Bottom Voltage Reference Force
7
VRLF
Bottom Voltage Reference Force
8
VRLS
Bottom Voltage Reference Sense
9
AGND
Analog Ground
10
AGND
Analog Ground
11
DGND
Digital Ground
12
DGND
Digital Ground
13
PD
14
DVDD
Digital Supply Voltage
15
TRI_B
Tri-state for the B Channel Outputs, Active High
Power Down, Active High
16
DIFF
17
TRI_A
Hi=Differential Mode, Lo=Single-Ended Mode
Tri-state for the A Channel Outputs, Active High
18
19
CKIN
Clock Input
SYNCO
Data Valid Output (Rising Edge)
20
DB0
Digital Output Bit 0 (LSB) ADC B
21
DB1
Digital Output Bit 1 ADC B
22
DB2
Digital Output Bit 2 ADC B
23
DOGND
Digital Output Ground
24
DOVDD
Digital Output Supply Voltage
25
DGND
26
DB3
Digital Output Bit 3 ADC B
27
DB4
Digital Output Bit 4 ADC B
28
DB5
Digital Output Bit 5 ADC B
29
DB6
Digital Output Bit 6 ADC B
30
DB7
Digital Output Bit 7 ADC B
31
DB8
Digital Output Bit 8 ADC B
32
DB9
Digital Output Bit 9 (MSB) ADC B
33
OTRB
34
DA0
Digital Output Bit 0 (LSB) ADC A
35
DA1
Digital Output Bit 1 ADC A
36
DA2
Digital Output Bit 2 ADC A
37
DA3
Digital Output Bit 3 ADC A
38
DA4
Digital Output Bit 4 ADC A
39
DOVDD
Digital Output Supply Voltage
40
DOGND
Digital Output Ground
41
DVDD
Digital Supply Voltage
Digital Ground
Over Range Digital Output Bit ADC B
Rev. P1.00
4
Preliminary
PIN DESCRIPTION (CONT'D)
Pin #
42
Symbol
DGND
Description
Digital Ground
43
DA5
Digital Output Bit 5 ADC A
44
DA6
Digital Output Bit 6 ADC A
45
DA7
Digital Output Bit 7 ADC A
46
DA8
Digital Output Bit 8 ADC A
47
DA9
Digital Output Bit 9 ADC A
48
OTRA
Over Range Digital Output Bit ADC A
49
VCMO
Differential Common Mode Voltage Output
50
DGND
Digital Ground
51
AGND
Analog Ground
52
AVDD
Analog Supply Voltage
53
AGND
Analog Ground
54
AGND
Analog Ground
55
VINB-
Analog Input B(-)
56
VINB+
Analog Input B(+)
57
AGND
Analog Ground
58
VINA+
Analog Input A(+)
59
VINA-
Analog Input A(-)
60
AGND
Analog Ground
61
AVDD
Analog Supply Voltage
62
AVDD
Analog Supply Voltage
63
AGND
Analog Ground
64
AGND
Analog Ground
Rev. P1.00
5
XRD64L43
XRD64L43
Preliminary
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Test Conditions (Unless Otherwise Specified)
TA = 25°C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40 MSPS, 50% Duty
Cycle, Differential Input Mode
Symbol
Parameter
Min.
Typ.
Max.
Unit
-0.75
+/-0.25
0.75
LSB
Conditions
DC ACCURACY
DNL
Differential Non-Linearity
INL
Integral Non-Linearity
+/-0.5
LSB
MON
Monotonicity
No Missing Codes
Guaranteed by Test
FSE
Full Scale Error
+10
mV
Note 1
ZSE
Zero Scale Error
5
mV
Single Ended Mode
ANALOG INPUT
INVR
Input Voltage Range
1
VRHS - VRLS
V
INRES
Input Resistance
20
KOhms
INCAP
Input Capacitance
5
pF
INBW
Input Bandwidth
400
MHz
VRLF Grounded
-1dB Small Signal
REFERENCE INPUT, INTERNAL BANDGAP REFERENCE AND REFERENCE BUFFER
RLADDER
Ladder Resistance
RSENSE
Sense Resistance
RLADTCO
Ladder Resistance Tempco
Bandgap Output Voltage
VBG
100
1.15
125
150
Ohms
2
Ohms
+0.8
Ohms/°C
1.25
1.35
Note 1
V
Range
VBGTC
Bandgap Reference
30
ppm/°C
Tempco
VRLF
0.0
VRHF
VRLF+
0.0
2.0
V
AVdd-0.3
V
Internal Reference Buffer
AVdd
V
External
1.0
VRHF
External Reference
VRLF+
2.5
1.0
VRHF PSRR Internal Reference Buffer
6
mV/V
VCMO, Common Mode Voltage
VCMO
Common Mode Voltage
1.15
1.25
Isource
Current Source
200
500
Notes:
1
Full Scale ADC reference is VRHS - VRLS.
Rev. P1.00
6
1.35
V
uA
XRD64L43
Preliminary
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Test Conditions (Unless Otherwise Specified)
TA = 25°C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40MSPS, 50% Duty
Cycle, Differential Input Mode
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
DYNAMIC PERFORMANCE Fs = 40MHz
SNR
Signal-to-Noise Ratio
SINAD
Not Including Harmonics
fin = 1.0 MHz
58
60
dB
fin = 4.0 MHz
57
60
dB
fin = 10.0 MHz
57
59
dB
Signal-to Noise and
Distortion
Including Harmonics
fin = 1.0 MHz
58
60
dB
fin = 4.0 MHz
57
59
dB
fin = 10 MHz
56
58
dB
fin = 1.0 MHz
9.3
9.7
Bit
fin = 4.0 MHz
9.2
9.5
Bit
fin = 10 MHz
9.0
9.2
Bit
ENOB EFFECTIVE NUMBER OF BITS
SFDR SPURIOUS FREE DYNAMIC RANGE
SFDR
fin = 1.0 MHz
70
dB
Crosstalk
fin = 1.0 MHz
75
dB
IMD
fin1 = 2.5 MHz
70
dB
Intermodulation Distortion
fin2 = 3.5 MHz
CONVERSION AND TIMING CHARACTERISTICS (CL = 10pF)
MAXCON
Maximum Conversion
MINCON
Minimum Conversion
100
KSPS
Latency
17
cycles
Aperture Jitter Time
12
ps
Digital Output Rise Time
3
ns
Digital Output Fall Time
3
ns
Output Data Propagation
6
25
ns
6
20
ns
Guaranteed by Design
5
20
ns
Guaranteed by Design
50
60
%
Guaranteed by Design
Lat
APJT
tr
tf
tpd
40
50
MSPS
Guaranteed by Design
Peak-to Peak
Delay
tden
Output Data Enable
Delay
tdis
Output Data Disable
Delay
CLKDC
Clock Duty Cycle
40
Rev. P1.00
7
XRD64L43
Preliminary
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Test Conditions (Unless Otherwise Specified)
TA = 25°C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40 MSPS, 50% Duty
Cycle, Differential Input Mode
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
DIGITAL INPUTS
DVINH
Digital Input High Voltage
DVINL
Digital Input Low Voltage
2.5
V
DIINH
Digital Input High Leakage
CKIN
Clock Input
-1.0
0.05
1.0
µA
DIFF
Differential/Single-Ended
-1.0
-0.25
1.0
uA
Internal pull-up resistor
A/B Channel Tri-State
-125.0
-90.0
-50.0
uA
Internal pull-down resistor
Power Down
-125.0
-90.0
-50.0
uA
Internal pull-down resistor
0.5
V
Input
TRI_A/TRI_B
PD
DIINL
Digital Input Low Leakage
CKIN
Clock Input
-5.0
0.05
5.0
nA
DIFF
Differential/Single-Ended
50.0
90.0
125.0
uA
Internal pull-up resistor
A/B Channel Tri-State
-1.0
0.25
1.0
uA
Internal pull-down resistor
Power Down
-1.0
0.25
1.0
uA
Internal pull-down resistor
5
8
pF
Input
TRI_A/TRI_B
PD
DINC
Digital Input capacitance
DIGITAL OUTPUTS (CL = 10 pF)
DOHV
DOLV
Digital Output High
DVdd
DVdd-
Voltage
-0.4V
0.3V
Digital Output Low
V
IOH = 1.5 mA
IOL = 1.5 mA
0.3
0.4
V
0.2
100
nA
Voltage
IOZ
High-Z Leakage
-100
Rev. P1.00
8
XRD64L43
Preliminary
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Test Conditions (Unless Otherwise Specified)
TA = 25°C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40 MSPS, 50% Duty
Cycle, Differential Input Mode
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.7
3.0
3.3
V
2.7
AVDD
3.3
V
Conditions
POWER SUPPLIES
AVDD
Analog Power Supply
Voltage
DVDD
Digital Power Supply
DVDD = AVDD
Range
Fs = 40 MHz, AVDD = DVDD = 2.7V, CL = 10pF, Fin = 10MHz (Includes Iref Current)
AIDD
Analog Supply Current
55
mA
DIDD
Digital Supply Current
13
mA
DOIDD
Output Driver Current
6
mA
PDISS
Power Dissipation
200
mW
Fs = 40 MHz, AVDD = DVDD = 3.3V, CL = 10pF, Fin = 10MHz (Includes Iref Current)
AIDD
Analog Supply Current
37
70
mA
DIDD
Digital Supply Current
15
20
mA
DOIDD
Output Driver Current
15
20
mA
225
365
mW
100
300
µA
PDISS
Power Dissipation
POWER DOWN CURRENT
IPD
Power Down Current
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3
VDD to GND
+7.0V
VRT & VRB
VIN
All Inputs
All Outputs
VDD +0.5 to GND -0.5V
VDD +0.5 to GND -0.5V
VDD +0.5 to GND -0.5V
VDD +0.5 to GND -0.5V
Storage Temperature
Lead Temperature (Soldering 10 seconds)
300°C
Maximum Junction Temperature
150°C
Package Power Dissipation Ratings (TA= +70°C)
TQFP
θJA = 89.4°C/W
ESD
2000V min
-65°C to 150°C
Notes:
1
2
3
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation at or above this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky
diode clamps from input pin to the supplies. All inputs have protection diodes which will protect the
device from short transients outside the supplies of less than 100mA for less than 100ms.
VDD refers to AVDD and DVDD. GND refers to AGND and DGND
Rev. P1.00
9
XRD64L43
Preliminary
APPLICATION SECTION
Bandgap
XRD64L43
VBG
VoltageReferences
The top ladder voltage for the XRD64L43 can be provided
from an internal bandgap reference. The bandgap reference
and its feedback path, Pins 1 and 2 respectively, can be used
to set the voltage for VRHF. Select Rf and Ri (if gain is
necessary) so that VRHF=VBG(1+Rf/Ri). The internal
bandgap voltage is 1.24 volts. The XRD64L43 has a low
impedence ladder, therefore, the typical value for Rf and Ri
is 10K (Rf and Ri are recommended to be greater than
5K).See Figure 2. for a simplified diagram. Decoupling caps
on the sense inputs to AGND should be used to reduce
injectioin of high-frequency noise.
AVdd
VFBK
VRHF
VRHS
Resistive Ladder
VRLS
VRLF
Figure 3. Voltage Reference Provided by an External Source as Direct Inputs
Bandgap
VBG
XRD64L43
Single-Ended Inputs
The XRD64L43 can be used in either single-ended or
differential input mode. For differential inputs, see the
Differential Inputs Section. Single-ended inputs minimize the amount of external components necessary to
interface with the XRD64L43. The common inputs,
VINA(-) and VINB(-) should be tied to ground. VINA(+)
and VINB(+) can be used to apply direct inputs to the
XRD64L43. Figure 4. is a simplied diagram for singleended inputs. Pin 16, DIFF should be held low to select
single-ended inputs.
VFBK
Ri
Rf
VRHF
VRHS
Resistive Ladder
VRLS
VRLF
Figure 2. Voltage Reference Generated from the
Internal Bandgap Voltage w/gain
Input A
VINA(+)
VINA(-)
50
External voltage references can be forced at VRHF and
VRLF. If VRHF and VRLF are driven externally, VFBK
should be connected to AVdd, which tri-states the
bandgap reference. Direct inputs or inputs driven by
external amplifiers can be used to drive the ladder
reference voltages of the XRD64L43. See Figure 3. for
a simplified diagram. The sense inputs are intended for
sensing purposes only and care must be taken to insure that
no current flow be present in the sense lines.
VINB(+)
VINB(-)
Input B
50
Figure 4. Single-Ended Inputs for the XRD64L43
Rev. P1.00
10
Preliminary
Differential Inputs
The XRD64L43 can be used in either differential or
single-ended input mode. For single-ended inputs, see
the Single-Ended Inputs Section. Differential inputs
reduce system noise by removing noise components
common at both input pins. Figure 5. is a simplified
diagram that is used as a common test circuit with our
XRD64L43ES application board. This circuit is used to
evaluate the dynamic performance of the XRD64L43
using differential inputs. Pin 16, DIFF should be held
high to select differential inputs.
Auto-Calibration
The XRD64L43 incorporates an auto-calibration circuit which continuously adjusts and matches the
offset and linearity of each ADC. This auto-calibration circuit is transparent to the user after the initial
4.2ms calibration (168,000 initial clock cycles).
Note: To avoid auto-calibration after power down, do
not disable CKIN. CKIN can be slowed down significantly
to save power without losing calibration.
22
Transformer
Input A
VINA(+)
VCMO
VINA(-)
22
50
22
Transformer
Input B
VINB(+)
VINB(-)
22
50
Figure 5. Common Test Circuit for the
Differential Input Mode
SYNCO, Data Valid Delay and Latency
SYNCO is an output pin provided by the XRD64L43.
Valid data is available on the rising edge of SYNCO,
see Figure 6. The Latency for the XRD64L43 is 17
clock cycles.
CKIN
N+1
N
Valid Data
N-17
N+2
N-16
XRD64L43
N-15
tden=20ns
SYNCO
tsynco=2ns (typical)
Figure 6. SYNCO, Data Valid Delay and Latency
for the XRD64L43
Rev. P1.00
11
Figure 7a. XRD64L43ES - Application Circuit for the XRD64L43
XRD64L43
Preliminary
Rev. P1.00
12
Figure 7b. XRD64L43ES - Application Circuit for the XRD64L43
Preliminary
Rev. P1.00
13
XRD64L43
Figure 7c. XRD64L43ES - Application Circuit for the XRD64L43
XRD64L43
Preliminary
Rev. P1.00
14
XRD64L43
Preliminary
XRD64L43 INTEGRAL NONLINEARITY
XRD64L43 DIFFERENTIAL NONLINEARITY
ERROR Fc = 40MHz
0.8
INL ERROR in LSB
0.8
0.4
0.2
0
-0.2
-0.4
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
950
1000
900
850
800
750
700
650
600
550
500
450
400
350
OUTPUT CODE
OUTPUT CODE
Figure 9. Integral Non-Linearity, Differential
Input Mode, Fc=40MHz, Fin=1.5kHz, VRHF=2.5V,
VDD=3V
Figure 8. Differential Non-Linearity, Differential
Input Mode, Fc=40MHz, Fin=1.5kHz, VRHF=2.5V,
VDD=3V
XRD64L43 Crosstalk Fs=40MSPS
Singel-Ended and Differential Modes
Channel 1=1MHz, Channel 2=(1.5MH z10.5MH z)
XRD64L43 IMD
Fin1 = 2.51Mhz, Fin2 = 3.4375Mhz
8192-Point FFT, Fclock =40.0MHz, Differential input mode
Crosstalk (dB)
0.00
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
-110.00
-120.00
Fbin
1.060
2.124
3.188
4.253
5.317
6.382
7.446
8.511
9.575
10.640
11.704
12.769
13.833
14.897
15.962
17.026
18.091
19.155
Relative Power in db
300
250
200
150
0
951
1001
901
851
801
751
701
651
601
551
501
451
401
351
301
251
201
151
101
1
51
100
-0.8
-0.8
50
DNL Error in LSB
0.6
0
-20
-40
-60
-80
-100
Single-Ended Input
Differential Input
1.5
3
4.5
6
7.5
9
10.5
Input Frequency (MHz)
Frequency
Figure 11. Crosstalk vs Input Frequency,
VDD=3V, Differential and Single Ended Inputs
Figure 10. Intermodulation Distortion,
Fin1=2.51MHz, Fin2=3.4375MHz, 8192-point FFT,
Fc=40MHz, Differential Input Mode
Rev. P1.00
15
XRD64L43
Preliminary
0
0
S in g l e T o n e 8 1 9 2 P o in t F F T
SingleT one 8192 Point F FT
SFD R -73.18
S IN A D - 5 9 . 7 7
-20
SFDR
-71 .19
S IN A D - 5 9 . 8 9
-40
R e l a t iv e P o w e r in d B
Re lativ e P o w e r i n d B
-20
-60
-80
-100
-120
-40
-60
-80
-100
-120
-140
-140
-160
DC
2.4
4 .9
7.3
9 .8
12.2
14.6
17.1
-160
1 9 .5
DC
Fr e q u e nc y i n M H z
2 .4
7.3
9.8
12.2
14.6
17.1
1 9 .5
F req u e n c y i n M Hz
Figure 13. FFT Spectrum @Fclock = 40.0MHz,
Fin = 4.0MHz, DIFFERENTIAL INPUT MODE
Figure 12. FFT Spectrum @Fclock = 40.0MHz,
Fin = 1.0MHz, DIFFERENTIAL INPUT MODE
0
S N R v s Inp ut Frequency
R e l a t i v e P o w e r in d B
S ingleTone 8192 Po int FF T
S F D R - 6 7 .1 2
S IN A D - 5 8 .2 8
-20
R e l a t iv e P o w e r in d B
4.9
-40
-60
-80
-100
-120
7 0 .0 0
D iff e r e n t ia l I n p u t
6 0 .0 0
5 0 .0 0
S in g l e - e n d e d
4 0 .0 0
3 0 .0 0
2 0 .0 0
C lock R a t e : 4 0 M H z
A V D D , D V D D @ 3 .0 v
1 0 .0 0
-140
7 .3
9.8
12.2
14.6
1 7 .1
19.5
8
7
5
4
3
2
30
4.9
14
2.4
10
DC
1
0
0 .0 0
-160
f IN ( M H z )
F r e qu e n c y i n M H z
Figure 15. SNR vs Input Frequency, Differential
and Single Ended Inputs, VDD=3V
Figure 14. FFT Spectrum @Fclock = 40.0MHz,
Fin = 10.0MHz, DIFFERENTIAL INPUT MODE
Rev. P1.00
16
XRD64L43
Preliminary
SINAD vs Input Frequency
S u p p ly C u r re n t v s S a m p le C l o c k F r e q u e n c y
70.00
Differential Input
70
S up ply Curre nt (m A )
60.00
Relative Power in dB
50.00
Single-ended
40.00
30.00
20.00
ClockRate: 40MHz
AVDD,DVDD @3.0v
A ID D
60
50
40
30
TA = 25°C, 1MHz< Fi n<10M H z
DIDD
20
10
10.00
D O ID D
0
10
20
30
14
10
8
7
5
4
3
2
1
0
0.00
15
25
30
35
40
45
50
55
60
fs (M SP S )
fIN (MHz)
Figure 16. SINAD vs Input Frequency, Differential and Single Ended Inputs, VDD=3V
Figure 17. Supply Current vs Sample Clock
Frequency
V CM O a n d V B G v s Tem p
R in v s T e m p er a tu re
2 6 .5
1.26
2 6 .4
VCM O
2 6 .3
1.25
2 6 .2
K oh m
(Voltage)
1.255
VBG
1.245
2 6 .1
26
1.24
2 5 .9
@ VDD =3.0V
2 5 .8
1.235
-40
+ 25
+ 85
2 5 .7
-40
T e m p (D e g r e e C )
+25
+85
Tem p. (°C )
Figure 18. VCMO and VBG vs Temperature
Figure 19. Rin of VINA+, VINB+ vs Temperature
at Fc=40MSPS
Rev. P1.00
17
XRD64L43
Preliminary
64 LEAD LOW-PROFILE QUAD FLAT PACK
(10 mm x 10 mm X 1.4 mm LQFP, 1.0 mm Form)
Rev. 3.00
33
48
49
32
64
17
16
1
α
Note: The control dimension is in millimeters.
SYMBOL
A
A1
A2
B
C
D
D1
e
L
α
INCHES
MIN
MAX
0.055
0.063
0.002
0.006
0.053
0.057
0.007
0.011
0.004
0.008
0.465
0.480
0.390
0.398
0.020
BSC
0.018
0.030
0°
7°
Rev. P1.00
18
MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.17
0.27
0.09
0.20
11.80
12.20
9.90
10.10
0.50 BSC
0.45
0.75
0°
7°
Preliminary
Notes
Rev. P1.00
19
XRD64L43
XRD64L43
Preliminary
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of
patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending
upon a user’s specific application. While the information in this publication has been carefully checked; no
responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the
circumstances.
Copyright 2000 EXAR Corporation
Datasheet July 2003
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. P1.00
20