54AC175 • 54ACT175 Quad D Flip-Flop General Description The ’AC/’ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. n n n n n n Buffered positive edge-triggered clock Asynchronous common reset True and complement output Outputs source/sink 24 mA ’ACT175 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC175: 5962-89552 — ’ACT175: 5962-89693 Features n Edge-triggered D-type inputs Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100278-1 IEEE/IEC DS100278-3 Pin Assignment for LCC DS100278-2 Pin Names Description D0–D3 Data Inputs CP Clock Pulse Input MR Master Reset Input Q0–Q3 True Outputs Q0–Q3 Complement Outputs DS100278-4 FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100278 www.national.com 54AC175 • 54ACT175 Quad D Flip-Flop August 1998 Functional Description Truth Table The ’AC/’ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The ’AC/’ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Inputs Outputs @ tn, MR = H @ tn+1 Dn Qn Qn L L H H H L H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse Logic Diagram DS100278-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. 175˚C DC Characteristics for ’AC Family Devices Symbol VIH VIL VOH VOL IIN Parameter VCC 54AC TA = −55˚C to +125˚C (V) Guaranteed Limits Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 Maximum Input Units Conditions VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOL = 12 mA 3.0 0.50 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA V IOL = 24 mA IOL = 24 mA VI = VCC, GND Leakage Current (Note 3) IOLD Minimum Dynamic 5.5 50 mA IOHD Output Current 5.5 −50 mA 3 VOLD = 1.65V Max VOHD = 3.85V Min www.national.com DC Characteristics for ’AC Family Devices Symbol ICC Parameter Maximum Quiescent (Continued) VCC 54AC TA = −55˚C to +125˚C (V) Guaranteed Limits 5.5 160.0 Units µA Supply Current Conditions VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol VIH VIL VOH VOL IIN Parameter VCC 54ACT TA = −55˚C to +125˚C (V) Guaranteed Limits Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input Units Conditions V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 5) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 5) VIN = VIL or VIH IOL = 24 mA 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V Leakage Current ICCT Maximum ICC/Input (Note 6) IOLD Minimum Dynamic 5.5 50 mA IOHD Output Current 5.5 −50 mA VOLD = 1.65V Max VOHD = 3.85V Min ICC Maximum Quiescent 5.5 160.0 µA VIN = VCC Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. www.national.com 4 AC Electrical Characteristics Symbol fmax tPLH tPHL tPLH tPHL 54AC TA = −55˚C to +125˚C CL = 50 pF VCC Parameter (V) (Note 8) Min Maximum Clock 3.3 95 Frequency 5.0 95 Units Fig. No. Max MHz Propagation Delay 3.3 1.0 14.5 CP to Qn or Qn 5.0 1.5 10.5 Propagation Delay 3.3 1.0 15.0 CP to Qn or Qn 5.0 1.5 11.5 Propagation Delay 3.3 1.0 15.0 MR to Qn 5.0 1.5 11.0 Propagation Delay 3.3 1.0 13.5 MR to Qn 5.0 1.5 10.5 ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol ts th tw tw trec (V) 54AC TA = −55˚C to +125˚C CL = 50 pF (Note 9) Guaranteed Minimum Setup Time, HIGH or LOW 3.3 5.0 Dn to CP 5.0 3.5 Parameter VCC Hold Time, HIGH or LOW 3.3 2.0 Dn to CP 5.0 2.5 CP Pulse Width 3.3 6.0 HIGH or LOW 5.0 5.0 MR Pulse Width, LOW 3.3 5.5 5.0 5.0 Recovery Time 3.3 1.5 MR to CP 5.0 1.5 Units Fig. No. ns ns ns ns ns Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V 5 www.national.com AC Electrical Characteristics Symbol fmax 54ACT TA = −55˚C to +125˚C CL = 50 pF VCC Parameter (V) Maximum Clock Units (Note 10) Min 5.0 95 5.0 1.5 11.5 ns 5.0 1.5 12.5 ns 5.0 1.5 11.5 ns 5.0 1.5 11.0 ns Fig. No. Max MHz Frequency tPLH Propagation Delay CP to Qn or Qn tPHL Propagation Delay CP to Qn or Qn tPLH Propagation Delay MR to Qn tPHL Propagation Delay MR to Qn Note 10: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol Parameter ts (H) Setup Time ts (L) Dn to CP th Hold Time, HIGH or LOW (V) 54ACT TA = −55˚C to +125˚C CL = 50 pF (Note 11) Guaranteed Minimum VCC 5.0 3.5 Units ns 3.5 5.0 1.5 ns 5.0 5.0 ns Dn to CP tw CP Pulse Width HIGH or LOW tw MR Pulse Width, LOW 5.0 5.0 ns trec Recovery Time, MR to CP 5.0 1.5 ns Note 11: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 45.0 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V Fig. No. Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 www.national.com 54AC175 • 54ACT175 Quad D Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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