54ACT818 8-Bit Diagnostic Register General Description The ’ACT818 is a high-speed, general-purpose pipeline register with an on-board diagnostic register for performing serial diagnostics and/or writable control store loading. The D-to-Y path provides an 8-bit parallel data path pipeline register for normal system operation. The diagnostic register can load parallel data to or from the pipeline register and can output data through the D input port (as in WCS loading). The 8-bit diagnostic register has multiplexer inputs that select parallel inputs from the Y-port or adjacent bits in the diagnostic register to operate as a right-shift-only register. This register can then participate in a serial loop throughout the system where normal data, address, status and control registers are replaced with ’ACT818 diagnostic pipeline registers. The loop can be used to scan in a complete test routine starting point (Data, Address, etc.). Then after a specified number of machine cycles it scans out the results to be inspected for the expected results. WCS loading can be accomplished using the same technique. An instruction word can be serially shifted into the shadow register and written into the WCS RAM by enabling the D output. n Swaps the contents of diagnostic register and output register n Diagnostic register and diagnostic testing n Cascadable for wide control words as used in microprogramming n Edge-triggered D registers n Outputs source/sink 24 mA n ’ACT818 has TTL-compatible inputs n ’ACT818 is functionally- and pin-compatible to AMD Am29818 and MMI 74S818 n Standard Microcircuit Drawing (SMD) 5962-9160901 Applications n n n n n n n n Register for microprogram control store Status register Data register Instruction register Interrupt mask register Pipeline register General purpose register Parallel-serial/serial-parallel converter Features n On-line and off-line system diagnostics Logic Symbol DS100251-3 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100251 www.national.com 54ACT818 8-Bit Diagnostic Register September 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100251-2 DS100251-1 Pin Names D0–D7 Description Data Inputs SDI Serial Data Input DCLK Diagnostics Clock MODE Control Input PCLK Pipeline Register Clock OEY Output Enable Input SDO Serial Data Output Y0–Y7 Data Outputs Diagnostic Register DS100251-4 www.national.com 2 Block Diagram DS100251-5 Functional Description nostic register output. Because of the independence of the clock inputs, data can be shifted in the diagnostic register via DCLK and loaded into the pipeline register from the data input via PCLK simultaneously, as long as no setup or hold times are violated. This simultaneous operation is legal. Data transfers into the diagnostic register occur on the LOW-to-HIGH transition of DCLK. Mode and SDI determine what data source will be loaded. The pipeline register is loaded on the LOW-to-HIGH transition of PCLK. Mode selects whether the data source is the data input or the diag- Function Table Inputs Outputs Operation SDI MODE DCLK PCLK SDO Diagnostic Reg. Pipeline Reg. X L N X S7 SI < SI − 1, NA Serial Shift; D7–D0 Disabled SO < SDI X L X N S7 NA PI < DI L H N X L SI < YI NA X H X N SDI NA PI < SI H H N X H Hold NA Normal Load Pipeline Register Load Diagnostic Register from Y; DI Disabled Load Pipeline Register from Diagnostic Register Hold Diagnostic Register; DI Enabled H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition 3 www.national.com Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC +0.5V −20 mA +20 mA −0.5V to VCC + 0.5V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns ± 50 mA Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. ± 50 mA −65˚C to +150˚C Note 2: All outputs loaded; thresholds on input associated with output under test. 175˚C DC Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL IIN Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Maximum Input 5.5 ± 1.0 µA 5.5 ± 1.0 µA 5.5 160 µA 5.5 1.6 mA or VCC − 0.1V VIN = VCC Leakage Current IOZ Maximum TRI-STATE Leakage Current ICC Maximum Quiescent OE = VIH VOUT = 0V, VCC VIN = VCC or GND Supply Current ICCT Maximum Additional ICC/Input VOH Minimum HIGH VIN = VCC − 2.1V VCC = 5.5V Level Output Voltage, 4.5 3.70 V (Note 2) VIN = VIL or VIH IOH = −24 mA Y0–Y7 Outputs 5.5 4.70 V IOH = −24 mA Level Output Voltage, 4.5 3.70 V D0–D7, SDO Outputs 5.5 4.70 V IOH = −8 mA IOH = −8 mA Minimum HIGH VOL Maximum LOW Level Output Voltage, 4.5 0.50 V (Note 2) VIN = VIL or VIH IOL = 24 mA Y0–Y7 Outputs 5.5 0.50 V IOL = 24 mA Level Output Voltage, 4.5 0.50 V D0–D7, SDO Outputs 5.5 0.50 V IOL = 8 mA IOL = 8 mA Maximum LOW www.national.com 4 DC Characteristics for ’ACT Family Devices Symbol Parameter (Continued) VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits IOLD VOLD = 1.65V Max Minimum Dynamic Output Current, 5.5 50 mA 5.5 −50 mA 5.5 32 mA 5.5 −32 mA Y0–Y7 Outputs IOHD VOHD = 3.85V Min Minimum Dynamic Output Current, Y0–Y7 Outputs IOLD VOLD = 1.65V Max Minimum Dynamic Output Current, D0–D7, SDO Outputs (Note 4) IOHD VOHD = 3.85V Min Minimum Dynamic Output Current, D0–D7, SDO Outputs (Note 4) Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Test load 50 pF, 500Ω to ground. Note 5: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) (Note 6) tPHL Propagation Delay Fig. to +125˚C CL = 50 pF Units Min Max 5.0 2.5 10.0 ns 5.0 2.5 10.0 ns 5.0 3.5 12.0 ns 5.0 3.5 13.5 ns 5.0 3.0 11.5 ns 5.0 3.0 12.0 ns 5.0 3.5 14.0 ns 5.0 3.5 15.5 ns 5.0 2.5 12.0 ns 5.0 1.5 10.0 ns 5.0 3.0 14.0 ns No. PCLK to Y tPLH Propagation Delay PCLK to Y tPHL Propagation Delay MODE to SDO tPLH Propagation Delay MODE to SDO tPHL Propagation Delay SDI to SDO tPLH Propagation Delay SDI to SDO tPHL Propagation Delay DCLK to SDO tPLH Propagation Delay DCLK to SDO tPZL Output Enable Time OEY to Yn tPLZ Output Disable Time OEY to Yn tPZL Output Enable Time DCLK to Dn 5 www.national.com AC Electrical Characteristics (Continued) 54ACT TA = −55˚C VCC Symbol Parameter (V) (Note 6) tPLZ Output Disable Time Fig. to +125˚C CL = 50 pF Units Min Max 5.0 1.5 12.0 ns 5.0 2.5 11.0 ns 5.0 2.0 12.0 ns 5.0 3.0 13.5 ns 5.0 2.0 13.5 ns No. DCLK to Dn tPZH Output Enable Time OEY to Yn tPHZ Output Disable Time OEY to Yn tPZH Output Enable Time DCLK to Dn tPHZ Output Disable Time DCLK to Dn Note 6: Voltage Range 5.0 is 5.0V ± 0.5V. AC Operating Requirements 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 8) Fig. Units Guaranteed Minimum ts Setup Time 5.0 6.0 ns 5.0 1.0 ns 5.0 6.0 ns 5.0 0.0 ns 5.0 2.5 ns 5.0 1.5 ns 5.0 4.5 ns 5.0 1.0 ns 5.0 4.5 ns 5.0 1.0 ns 5.0 11.5 ns 5.0 12.5 ns 5.0 3.5 ns D to PCLK th Hold Time D to PCLK ts Setup Time MODE to PCLK th Hold Time MODE to PCLK ts Setup Time Y to DCLK th Hold Time Y to DCLK ts Setup Time MODE to DCLK th Hold Time MODE to DCLK ts Setup Time SDI to DCLK th Hold Time SDI to DCLK ts Setup Time DCLK to PCLK ts Setup Time PCLK to DCLK tw www.national.com Pulse Width 6 No. AC Operating Requirements (Continued) 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 8) Fig. Units No. Guaranteed Minimum PCLK HIGH or LOW tw Pulse Width 5.0 3.0 ns DCLK HIGH or LOW Note 7: Test load 50 pF, 500Ω to ground. Note 8: Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol CIN CPD Parameter Typ Units Input Capacitance 4.5 pF Power Dissipation 20 pF Conditions VCC = OPEN VCC = 5.0V Capacitance 7 www.national.com 8 Physical Dimensions inches (millimeters) unless otherwise noted 28 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24 Lead Slim (0.300" wide) Ceramic Dual-in-Line Package (D) NS Package Number J24F 9 www.national.com 54ACT818 8-Bit Diagnostic Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24 Lead Ceramic Cerpack NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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