REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device type 02; editorial changes throughout. Redrawn. 93-06-23 M. A. Frye B Update boilerplate. Add device types 03 and 04. Add case outline M. Editorial changes throughout. 94-06-30 M. A. Frye C Add 05 device. Removed some parameters from table IIB. Updated boilerplate. ksr 98-04-06 Raymond Monnin D Added equation to footnote 2/, made corrections to table IB. Changed sample size in paragraph 4.4.1. Removed (Dose Rate Induced latchup testing) and (Dose Rate Upset testing) paragraphs. Updated boilerplate. ksr 98-07-10 Raymond Monnin E Change 1.3 Maximum junction temperature from 175(C to 150(C. Added footnote 2/ to Figure 2 for the T and M case outlines. Add die information per Appendix A. ksr 98-09-21 Raymond Monnin REV SHEET REV E E E E E E E E E SHEET 15 16 17 18 19 20 21 22 23 REV E E E E E E E E E E E E E E SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE PREPARED BY TIM H. NOH DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316 CHECKED BY KENNETH RICE APPROVED BY TIM H. NOH DRAWING APPROVAL DATE 92-06-23 REVISION LEVEL AMSC N/A MICROCIRCUIT, MEMORY, DIGITAL, , CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2000 GATES,MONOLITHIC SILICON SIZE A CAGE CODE 5962-90965 67268 E SHEET 1 DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. OF 23 5962-E526-98 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 | | | Federal stock class designator | | | RHA designator (See 1.2.1) 01 | | | Device type (See 1.2.2) 90965 \ / V | | | Device class designator (See 1.2.3) X | | | Case outline (See 1.2.4) X | | | Lead finish (See 1.2.5) \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type 01 02 03 04 05 Generic number 1020A 1020A-1 1020B 1020B-1 RH1020 Circuit function Bin speed 2000 gate, field programmable gate array 2000 gate, field programmable gate array 2000 gate, field programmable gate array 2000 gate, field programmable gate array 2000 gate, field programmable gate array 186 ns 158 ns 168.2 ns 142.9 ns 168.2 ns 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class M Q or V Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter X Y Z U T M Descriptive designator CQCC2 - J44 CQCC2 - J68 CQCC2 - J84 CMGA15 - P85 CQCC1 - F84 See figure 1 Terminals 44 68 84 84 84 84 Package style J-lead chip carrier J-lead chip carrier J-lead chip carrier Pin grid array 1/ Unformed lead chip carrier Unformed lead chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1/ Actual number of pins is 85 including one index or orientation pin (C3). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 2 1.3 Absolute maximum ratings. 2/ DC supply voltage range (VDD) - - - - - - - - - - - - - Input voltage range (VI) - - - - - - - - - - - - - - - - - - - Output voltage range (VO) - - - - - - - - - - - - - - - - - I/O source sink current IIO) - - - - - - - - - - - - - - - - Storage temperature range (TSTG) - - - - - - - - - - Lead temperature (soldering, 10 seconds) - - - - - Thermal resistance, junction-to-case (JC) Case outline X, Y, Z, U, T - - - - - - - - - - - - - - - - - Case outline M - - - - - - - - - - - - - - - - - - - - - - - - Maximum junction temperature (TJ) - - - - - - - - - - -0.5 V dc to +7.0 V dc -0.5 V dc to VDD + 0.5 V dc -0.5 V dc to VDD + 0.5 V dc ±20 mA -65(C to +150(C 300(C See MIL-STD-1835 10(C/W 3/ +150(C 1.4 Recommended operating conditions. Supply voltage (VDD) - - - - - - - - - - - - - - - - - - - - Case operating temperature range (TC) - - - - - - - +4.5 V dc to +5.5 V dc -55(C to +125(C 1.5 Radiation features. Total Dose - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 300K rads (maximum) 4/ 1.6 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012)- - - - - - - - 100 percent 5/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbook. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-973 - Configuration Management. MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines HANDBOOK DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's). MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2/ 3/ 4/ 5/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. When a thermal resistance for this case is specified in MIL-STD-1835 that value shall supersede the value indicated herein. Device electrical characteristics are verified for post irradiation levels at 25(C per MIL-STD-883, Test method 1019, condition A and post 168 hours, 100(C, biased anneal. 100 percent test coverage of blank programmable logic devices. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 3 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DODISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the documents cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard No. 17 - A Standard Test Procedure for the Characterization of Latch-up in CMOS Integrated Circuits. (Applications for copies should be addressed to the Electronics Industries Association, 2001 Pennsylvania Street, N.W., Washington, DC 20006.) AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-95 - Standard Guide for the Measurement of Single Event Procedures from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials, 1916 Race Street, Philadelphia, Pennsylvania 19103). (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with figure 1 and 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. 3.2.3.1 Unprogrammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered item drawing is not part of this drawing. When required in screening (see 4.2 herein) or quality conformance inspection group A, B, C, D, or E (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of logic modules shall be utilized or at least 25 percent of the total logic modules shall be utilized for any altered item drawing pattern. 3.2.3.2 Programmed devices. The truth table or test vectors for programmed devices shall be as specified by an attached altered item drawing. 3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IA. The electrical tests for each subgroup are defined in table IA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 4 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations, two processing options are provided for selection in the contract. 3.11.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1 and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.11.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical parameters of method 5004 of MIL-STD-883 and substitute lines 1 through 6 of table IIA herein. b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. For device class M, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (1) Dynamic burn-in for device class M (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein). c. Interim and final electrical parameters shall be as specified in table IIA herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 5 Table IA. Electrical performance characteristics. Symbol Output low voltage VOL Output high voltage VOH Input low voltage VIL Input high voltage VIH Standby supply current IDD Input leakage current IIL Output leakage current IOZ Output short circuit IOS current I/O terminal CI/O capacitance Functional tests FT 3/ Binning circuit delay tPBLH, tPBHL Test Conditions -55(C TC +125(C 4.5 V VDD 5.5 V 1/ unless otherwise specified test one output at a time, VDD = 4.5 V, IOL = 4.0 mA test one output at a time, VDD = 4.5 V, IOH = -3.2 mA outputs unloaded, VDD = 5.5 V, VIN = VDD or GND VDD = 5.5 V, VIN = VDD or GND VDD = 5.5 V, VOUT = VDD or GND VOUT = VDD 2/ VOUT = GND See 4.4.1c, f = 1.0 Mhz, VOUT = 0 V VDD = 4.5 V , See 4.4.1e and f See figure 3, VIL = 0 V, VIH = 3.0 V, VDD = 4.5 V, VOUT = 1.5 V 4/ Group A subgroups 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 4 7,8A,8B 9,10,11 Device type All All All 01-04 05 All All All 01,02 05 01,02 05 All All 01 02 03 04 05 Limits Min Max 0.4 3.7 0.8 2.0 VDD+ 2.2 0.3 25 -10 10 -10 10 20 140 0 160 -100 -10 -100 0 20 186 158 168.2 142.9 168.2 Unit V V V V mA µA µA mA pF ns 1/ All tests shall be performed under the worst case condition unless otherwise specified. Devices supplied to this drawing will meet levels M, D, L, R, and F, of irradiation. However, this device is only tested at the "F" level. Pre and post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25(C. 2/ VDD = 4.5 V for minimum limits and VDD = 5.5 V for maximum limits. Test one output at a time, duration of short circuit condition shall not exceed one second. This test for devices 01, 02, and 05 only. 3/ Devices are functionally tested using a serial scan test method. Data is shifted into the SDI pin and the DCLK pin is used as a clock. The data is used to drive the inputs of the internal logic and I/O modules, allowing a complete functional test to be performed. The outputs of the module can be read by shifting out the output response or by monitoring the PRA and PRB pins. These tests form a part of the manufacturer's test tape and shall be maintained by the approved source(s) of supply and shall be made available upon request by the preparing or acquiring activity. 4/ Binning circuit delay is defined as the input-to-output delay of a special path called the "binning circuit". The binning circuit shall be programmed into all device prior to screening. The binning circuit consists of one input buffer plus 28 logic modules plus one output buffer. The logic modules are distributed along two sides of the device. These modules are configured as inverting and non-inverting buffers and are connected through programmed antifuses with typical capacitive loading. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 6 TABLE IB. SEP test limits. Symbol Characteristics Upset Mode SEL Single event latchup all SEU Single event upset C-Latch Conditions Effective LET no upset (MeV-cm2/mg) Saturated X-section -55(CTC125(C 5.5 V >84 -55(CTC125(C 4.5 V >8 3/ N/A 1.5 x 10-6 cm2/bit TA = +25(C Single event dielectric (antifuse) rupture all Bias VDD = 5.0 V 18.8 -55(CTC125(C 5.5 V >40 1 Mhz Clock 2/ SEDR 4/ 1/ 3/ 2.5 x 10-7 cm2/device N/A Notes: 1/. Verification test per TRB approved test plan. 2/. Clock upset causes upset in the clocked flip-flops, its rate is proportional to the clock frequency and can be computed using the following; f x 3x10-8 upset/device-day ; 1 MHz Where f is the clock frequency of interest and 3 x 10-8 (upset/device-day) is the computed rate from the SEU testing data. 3/. Threshold LET at 1% saturated X-section is 13, and at 10%, saturated X-section is 25. 4/. Tested at worst case that ions have perpendicular incidence. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in appendix B of MIL-PRF-38535. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MILPRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MIL-STD-883 (see 3.1 herein) and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 5 and 6 of table IA of method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CI and CO measurements) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. A sample size of 5 devices with no failures, and all input and output terminals shall be required. d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may affect the performance of the device. For device class M, procedures and circuits shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive. Information contained in JEDEC standard number 17 may be used for reference. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 7 Case M Inches .002 .004 .006 .008 .012 .014 mm .050 .100 .150 .200 .300 .360 Inches .020 .025 .030 .035 .040 .105 mm 2.67 3.05 3.30 4.06 12.70 16.26 Inches .120 .130 .160 .500 .640 .660 mm 3.05 3.30 4.06 12.70 16.26 16.76 Inches .935 .975 1.590 1.620 mm 23.75 24.77 40.39 41.15 NOTES: 1. Dimensions are in inches. 2. The US government preferred system of measurement is the metric SI system. However, this item was originally designed using inch-pound units of measurement. In the event of conflict between the metric and inch-pound units, the inch-pound units shall take precedence. 3. For detail A: Includes lead attach dogleg height and lid height, whichever is greater. FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 8 Device type Case outlines Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 All 1/ X Y Terminal symbol I/O I/O VDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDD I/O VPP I/O I/O I/O I/O GND I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O GND CLK or I/O MODE I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VDD I/O I/O I/O VPP I/O I/O I/O I/O I/O I/O GND I/O I/O Case outlines Terminal number 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 1/ 1/ 1/ 1/ X Y Terminal symbol VDD SDI or I/O DCLK or I/O PRA or I/O PRB or I/O I/O I/O I/O GND I/O ------------------------------------------------- I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O CLK or I/O I/O MODE VDD SDI or I/O DCLK or I/O PRA or I/O PRB or I/O I/O I/O I/O I/O I/O I/O GND I/O I/O 1/ PRA and PRB are inverting signals for device types 01 and 02, and non-inverting signals for device types 03, 04, and 05. PRA and PRB are used only for device testing or debugging. In normal operation, all device types exhibit identical logic on these pins. FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 9 Device type All 1/ Device type All 1/ Case outlines Z Case outlines Z Terminal number Terminal symbol Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O VPP I/O I/O I/O I/O I/O I/O GND I/O I/O 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 1/ 75 1/ 76 77 78 79 80 81 82 83 84 I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O CLK or I/O I/O MODE VDD VDD I/O I/O I/O SDI or I/O DCLK or I/O PRA or I/O PRB or I/O I/O I/O I/O I/O I/O I/O GND I/O I/O 1/ PRA and PRB are inverting signals for device types 01 and 02, and non-inverting signals for device types 03, 04, and 05. PRA and PRB are used only for device testing or debugging. In normal operation, all device types exhibit identical logic on these pins. FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 10 Device type All 1/ Device type All 1/ Case outline U Case outline U Terminal number Terminal symbol Terminal number Terminal symbol I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA or I/O I/O NC I/O I/O VDD I/O GND I/O I/O PRB or I/O SDI or I/O I/O I/O Keying pin I/O I/O I/O DCLK or I/O I/O I/O I/O I/O I/O I/O GND GND VDD VDD MODE VDD I/O I/O F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 J2 J5 J6 J7 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 CLK or I/O GND I/O I/O VDD I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VPP I/O I/O GND I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 1/ B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 1/ B11 C1 C2 C3 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 F1 F2 F3 1/ PRA and PRB are inverting signals for device types 01 and 02, and non-inverting signals for device types 03, 04, and 05. PRA and PRB are used only for device testing or debugging. In normal operation, all device types exhibit identical logic on these pins. FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 11 Device type All 1/ Device type All 1/ Case outline T, M Case outline T, M Terminal number Terminal symbol Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NC I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O VPP I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 2/ 62 2/ 63 1/ 64 1/ 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 I/O I/O I/O I/O I/O I/O GND GND I/O I/O CLK/I/O I/O MODE VDD VDD I/O I/O I/O SDI/I/O DCLK/I/O PRA/I/O PRB/I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O NC = No connection 1/ PRA and PRB are inverting signals for device types 01 and 02, and non-inverting signals for device types 03, 04, and 05. PRA and PRB are used only for device testing or debugging. In normal operation, all device types exhibit identical logic on these pins. 2/ For device type 05 only. The special function pins 61(SDI_I/O) and 62 (DCLK_I/O) have shown anomalous operation when configured as outputs. Designers should ensure that these pins are unused as I/Os or, if necessary, they can be used as inputs only. Please contact vendor for complete details on product advisory. FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 12 FIGURE 3. Switching test circuit and waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 13 Note: Resistors are 1k6 resistors. FIGURE 4. Radiation exposure circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 14 4.4.1 Continued. e. Programmed device (see 3.2.3.2) - For device class M, subgroups 7, 8A, and 8B tests shall consist of verifying the functionality of the device. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. These tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.6 herein). f. Unprogrammed devices shall be tested for programmability and dc and ac performance compliance to the requirements of group A, subgroups 1 and 7. (1) A sample shall be selected from each wafer lot to satisfy programmability requirements. Eight devices shall be submitted to programming (see 3.2.3.1). If any device fails to program, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures allowable. (2) These eight devices shall also be submitted to the requirements of the specified tests of group A, subgroups 1 and 7. If any device fails, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures allowable. (3a) Eight devices from the programmability sample shall be submitted to the requirements of group A, subgroups 9 for binning circuit delay only. If any device fails, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures allowable. (3b) If the binning circuit is tested on 100 percent of the products, then the above requirement is met. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. b. TA = +125(C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MILPRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with MIL-PRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25(C ±5(C, after exposure, to the subgroups specified in table IIA herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019 and as specified herein. 4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-irradiation end-point electrical parameter limit at 25 (C ± 5(C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 15 4.4.4.2 Single event phenomena (SEP). SEP testing shall be required on class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup characteristics. Test four devices with zero failures. ASTM standard F1192 may be used as a guideline when performing SEP testing. The test conditions for SEP are as follows: a. The package lid of the DUT is removed so as to provide an unobstructed path to the die for the ion beam. b. The DUT is biased or exercised as appropriate to that IC being tested. c. The temperature that SEP tests are conducted at is 25(C +/- 10(C (ambient). d. Particle penetration range is > 20 microns (Si). e. The flux used is between 1E2 and 1E5 ions/cm2/s. f. The beam incidence angle(s) used are between 0( to 60( from normal. g. Supply current and voltage(s) as well as SEU, SEL and faults are monitored and recorded in-situ. h. For SEP test limits, see Table IB herein. 4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option, either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and 9. 4.6 Programming procedures. The programming procedures shall be as specified by the device manufacturer and shall be made available upon request. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-STD-883 (see 3.1 herein) for device class M and MIL-PRF-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished in accordance with MIL-STD-973 using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0525. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone (614) 692-0674. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 16 TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/ Line no. 1 2 3 4 5 6 7 8 9 10 Test requirements Interim electrical parameters (see 4.2) Static burn-in I and II (method 1015) Same as line 1 Dynamic burn-in (method 1015) Same as line 1 Final electrical parameters Group A test requirements Group C end-point electrical parameters Group D end-point electrical parameters Group E end-point electrical parameters Subgroups (in accordance with MIL-STD-883, method 5005, table IA) Device class M Not required Required 1*,2,3,7*, 8A,8B,9,10, 11 1,2,3,4**,7, 8A,8B,9,10, 11 2,3,7, 8A,8B 2,3, 8A,8B 1,7,9 Subgroups (in accordance with MIL-PRF-38535, table III) Device Device class Q class V 1,7,9 1,7,9 Not Required required 1*,7* Required Required 1*,7* 1*,2,3,7*, 1*,2,3,7*, 8A,8B,9,10, 8A,8B,9, 11 10,11 1,2,3,4**,7, 1,2,3,4**,7, 8A,8B,9,10, 8A,8B,9,10, 11 11 2,3,7, 1,2,3,7, 8A,8B 8A,8B,9, 10,11 2,3, 2,3, 8A,8B 8A,8B 1,7,9 1,7,9 1/ Blank spaces indicate tests are not applicable. 2/ Any or all subgroups may be combined when using high-speed testers. 3/ Subgroups 7 and 8 functional tests shall also verify functionality for unprogrammed devices or that the altered item drawing pattern exists for programmed devices. 4/ * indicates PDA applies to subgroup 1 and 7. 5 ** see 4.4.1c. 6/ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with reference to the previous interim electrical parameters (see line 1). 7/ See 4.4.1d. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 17 TABLE IIB. Delta limits at +25(C. Device types Test 1/ All IDD ±1.0 mA IOZ ±2.0 µA tPBLH, tPBHL 1/ ±10 ns The above parameters shall be recorded before and after the required burn-in and life test to determine the delta. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MILPRF-38535 and MIL-HDBK-1331. 6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. 6.5.2 Waveforms. Waveform symbol Input Output MUST BE VALID WILL BE VALID CHANGE FROM H TO L WILL CHANGE FROM H TO L CHANGE FROM L TO H WILL CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED CHANGING STATE UNKNOWN HIGH IMPEDANCE 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 18 Appendix A Appendix A forms a part of SMD 5962-90965 10. Scope 10.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers approved QML plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number (PIN). When available a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN. 10.2 PIN. The PIN is as shown in the following example: 5962 | | Federal stock class designator \___________ F 90965 01 | | | | RHA Device designator type (10.2.1) (see 10.2.2) __________/ V Drawing number Q | | Device class (see 10.2.3) 9 | | Die Code (see 10.2.4) X | | Die details (see 10.2.5) 10.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 10.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type 03 05 Generic number 1020B RH1020 Circuit function Bin speed 2000 gate, field programmable gate array 2000 gate, field programmable gate array 168.2 ns 168.2 ns 10.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Q or V Device requirements documentation Certification and qualification to MIL-PRF-38535 10.2.4 Die code. The die code designator shall be a number 9 for all devices supplied as die only with no case outline. 10.2.5 Die details. The die details designation shall be a unique letter which designates the die’s physical dimensions, bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product and variant supplied to this appendix. 10.2.5.1 Die physical dimensions. Device type 03 05 Die size Die thickness 254 mils X 267 mils 254 mils X 267 mils Die Detail 15±1 mils 25±1 mils A B Figure Number A-1 A-1 10.2.5.2 Die bonding pad locations and electrical functions. Device type Die Detail Figure Number 03 A A-1 05 B A-1 10.2.5.3 Interface materials. Device type Top metalization Backside metalization 03 Ti-cap+Al/Cu/Si,9-12kA None (backgrind) 05 TiW+Al/Cu,9-12kA None (backgrind) 10.2.5.4 Assembly related information. Device type Glassivation Die Detail 03 Ox/Nitride A 05 Ox/Nitride/Polyimide B STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 Die Detail A B Figure Number A-1 A-1 Figure Number A-1 A-1 SIZE 5962-90965 A REVISION LEVEL E SHEET 19 10.2.5.5 Wafer fabrication source. Device type Source 03 Matsushita Electronics Corp. Japan 05 Lockheed Martin Federal System, VA Die Detail A B 10.3 Absolute maximum ratings. See paragraph 1.3 within the body of this drawing for details. 10.4 Recommended operating conditions. See paragraph 1.4 within the body of this drawing for details. Figure Number A-1 A-1 20. APPLICABLE DOCUMENTS. 20.1 Government specification, standards, and handbooks. Unless otherwise specified, the following specification, standard, and handbook of the issue listed in that issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, form a part of this drawing to the extent specified herein. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's). (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 20.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 30. REQUIREMENTS. 30.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MILPRF-389535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The Modification in the QM plan shall not effect the form, fit or function as described herein. 30.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein. 30.2.1 Die physical dimensions. The die physical dimensions shall be specified in 10.2.5.1 and on figure A-1. 30.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as specified in 10.2.5.2 and figure A-1. 30.2.3 Interface materials. The interface materials for the die shall be as specified in 10.2.5.3 and on figure A-1. 30.2.4 Assembly related information. The assembly related information shall be as specified in 10.2.5.4 and figure A-1. 30.2.5 Truth table(s). Where technically applicable, (for die) the truth table(s) shall be as defined within paragraph 3.2.3 of the body of this document. 30.2.6 Radiation exposure circuit. The radiation exposure circuit will be as specified on figure 4 as shown within the body of this document. 30.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this document. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 20 30.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA. 30.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed in 10.2 herein. The certification mark shall be "QML” or "Q” as required by MIL-PRF-38535. 30.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML38535 listed manufacturer in order to supply to the requirements of this drawing (see 60.4 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein. 30.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuit die delivered to this drawing. 30.8 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing. 30.8.1 Unprogrammed die delivered to the user. All testing shall be verified through wafer probe test as defined in 40.2. 30.8.2 Manufacturer-programmed die delivered to the user. The programming integrity test shall be performed during programming. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 40. QUALITY ASSURANCE PROVISIONS 40.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 40.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the manufacturer’s QM plan. As a minimum it shall consist of: a) Wafer lot acceptance for Class V product using the criteria within MIL-STD-883 test method 5007. b) 100% wafer probe (see paragraph 30.4) c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 test method 2010 or the alternate procedures allowed within MIL-STD-883 test method 5004. 40.3 Conformance inspection. 40.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see 30.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified within paragraphs 4.4.4.1, 4.4.4.1.1, and 4.4.4.2 herein. 50. DIE CARRIER 50.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and electrostatic protection. 60. NOTES 60.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit application (original equipment), design applications and logistics purposes. 60.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone (614)-692-0536. 60.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined within MIL-PRF-38535 and MIL-HDBK-1331. 60.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see 30.6 herein) to DSCC-VA and have agreed to this drawing. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 21 Pad# Name X-Coord Y-Coord Pad# Name X-Coord Y-Coord 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O VPP, VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2922 -2788 -1912 -1685 -1459 -1233 -997 -830 -588 -345 -179 --13 154 320 578 820 987 1222 1449 1680 1907 2920 2920 2920 2964 2259 2003 1747 1491 1251 992 674 431 265 98 -68 -253 -495 -814 -1056 -1223 -1489 -1745 -2001 -2257 -2987 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -3085 -2962 -2257 -2001 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 GND I/O I/O I/O GND GND I/O I/O I/O, CLK I/O MODE VCC VCC I/O I/O I/O I/O, SDI I/O, DCLK I/O, PRA GND I/O, PRB I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2920 2921 2041 1830 1603 1372 1146 979 813 570 328 161 -5 -172 -338 -580 -823 -989 -1233 -1459 -1685 -1912 -1745 -1489 -1248 -1082 -839 -521 -278 -112 55 297 463 706 1024 1267 1433 1674 1930 2186 2442 2964 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 3087 NOTES: 1. The center of X-Y coordinate is at the center of the die. 2. All dimensions are in )m. Figure A-1. A1020B and RH1020 Bond Pad Locations and Functions STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 22 Figure A-1. A1020B and RH1020 Bond Pad Locations and Functions - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 42316-5000 DSCC FORM 2234 APR 97 SIZE 5962-90965 A REVISION LEVEL E SHEET 23 STANDARDIZED MILITARY DRAWING SOURCE APPROVAL BULLETIN DATE: 98-09-21 Approved sources of supply for SMD 5962-90965 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 3/ 5962-9096501MXA 2/ A1020A-JQ44B 5962-9096501MYA 2/ A1020A-JQ68B 5962-9096501MZA 2/ A1020A-JQ84B 5962-9096501MUC 2/ 2/ A1020A-PG84B TPC1020AMGB84B 5962-9096501MTC 2/ 2/ A1020A-CQ84B TPC1020AMHT84B 5962-9096501MMC 2/ TPC1020AMHFG84B 5962-9096502MXA 2/ A1020A-1-JQ44B 5962-9096502MYA 2/ A1020A-1-JQ68B 5962-9096502MZA 2/ A1020A-1-JQ84B 5962-9096502MUC 2/ 2/ A1020A-1-PG84B TPC1020AMGB84B-1 5962-9096502MTC 2/ 2/ A1020A-1-CQ84B TPC1020AMHT84B-1 5962-9096502MMC 2/ TPC1020AMHFG84B-1 5962-9096503MUC 0J4Z0 A1020B-PG84B 5962-9096503MTC 0J4Z0 A1020B-CQ84B 5962-9096503MMC 2/ A1020B-CQ84B 5962-9096504MUC 0J4Z0 A1020B-1PG84B 5962-9096504MTC 0J4Z0 A1020B-1CQ84B 5962-9096504MMC 2/ A1020B-1CQ84B See notes at end of table. Page 1 of 2 Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 3/ 5962F9096505QTC 0J4Z0 RH1020-CQ84V 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Not available from an approved source. 3/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number Vendor name and address 0J4Z0 Actel Corporation 955 East Arques Ave. Sunnyvale, CA 94086 The following table lists the SMD part numbers for die. 1/ Standard microcircuit drawing PIN Vendor CAGE number Vendor similar 1/ PIN 5962-9096503Q9A 0J4Z0 A1020B-DIE 5962F9096505Q9B 0J4Z0 RH1020-DIE Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number Vendor name and address 0J4Z0 Actel Corporation 955 East Arques Ave. Sunnyvale, CA 94086 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. Page 2 of 2