INTEGRATED CIRCUITS DATA SHEET 74AHC595; 74AHCT595 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product specification File under Integrated Circuits, IC06 2000 Mar 15 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 FEATURES DESCRIPTION • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. • Balanced propagation delays The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register has separate clocks. • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. • For AHCT only: operates with TTL input levels • Specified from −40 to +85 °C and from−40 to +125 °C. APPLICATIONS The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. • Serial-to-parallel data conversion • Remote control holding register. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC tPHL/tPLH propagation delay CL = 15 pF; VCC = 5 V SHCP to Q7’ 4.0 3.8 ns STCP to Qn 4.2 4.0 ns MR to Q7’ 4.4 4.6 ns 3.0 3.0 pF 170 170 MHz CL = 50 pF; f = 1 MHz; notes 1, 2 and 3 180 190 pF CI input capacitance fmax maximum clock frequency CPD power dissipation capacitance Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 3. All 9 outputs switching. 2000 Mar 15 AHCT 2 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 FUNCTION TABLE See note 1. INPUT OUTPUT FUNCTION SHCP STCP OE MR DS Q7’ Qn X X L L X L NC a LOW level on MR only affects the shift registers X ↑ L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear. Parallel outputs in high impedance OFF-state. ↑ X L H H Q6’ NC logic HIGH level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6’) appears on the serial output (Q7’). X ↑ L H X NC Qn’ contents of shift register stages (internal Qn’) are transferred to the storage register and parallel output stages ↑ ↑ L H X Q6’ Qn’ contents of shift register shifted through. Previous contents of the shift register is transferred to the storage register and the parallel output stages. Note 1. H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition; X = don’t care; NC = no change; Z = high impedance OFF-state. ORDERING INFORMATION PACKAGES TYPE NUMBER 74AHC595D TEMPERATURE RANGE PINS −40 to +125 °C PACKAGE MATERIAL CODE 16 SO plastic SOT109-1 74AHC595PW 16 TSSOP plastic SOT403-1 74AHCT595D 16 SO plastic SOT109-1 74AHCT595PW 16 TSSOP plastic SOT403-1 2000 Mar 15 3 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 PINNING PIN SYMBOL DESCRIPTION 1, 2, 3, 4, 5, 6, 7 and 15 Q1, Q2, Q3, Q4, Q5, Q6, Q7 and Q0 parallel data output 8 GND ground (0 V) 9 Q7’ serial data output 10 MR master reset (active LOW) 11 SHCP shift register clock input 12 STCP storage register clock input 13 OE output enable input (active LOW) 14 DS serial data input 16 VCC DC supply voltage handbook, halfpage 11 handbook, halfpage Q1 1 16 VCC Q2 2 15 Q0 Q3 3 14 DS Q4 4 13 OE Q7' Q0 Q1 14 595 Q2 Q3 DS Q5 5 12 STCP Q6 6 11 SHCP Q5 Q7 7 10 MR Q6 GND 8 9 Q7' Q4 Q7 MR MNA551 10 Fig.1 Pin configuration. 2000 Mar 15 12 SHCP STCP 9 15 1 2 3 4 5 6 7 OE 13 MNA552 Fig.2 Logic symbol. 4 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state handbook, halfpage13 EN3 12 10 11 14 74AHC595; 74AHCT595 C2 handbook, halfpage DS 11 SHCP 14 SRG8 R C1/ 1D 10 8-STAGE SHIFT REGISTER Q7' 15 3 2D MR 1 12 STCP 2 9 8-BIT STORAGE REGISTER 3 4 13 5 OE 3-STATE OUTPUTS 6 7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 15 1 2 3 4 5 6 7 MNA554 MNA553 Fig.3 IEC logic symbol. Fig.4 Functional diagram. handbook, full pagewidth STAGE 0 DS D Q STAGES 1 TO 6 D STAGE 7 Q D CP Q7' Q FF7 FF0 CP R R SHCP MR D Q D Q LATCH LATCH CP CP STCP OE MNA555 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Fig.5 Logic diagram. 2000 Mar 15 5 Q7 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 SHCP handbook, full pagewidth DS STCP MR OE Z-state Q0 Z-state Q1 Z-state Q6 Z-state Q7 Q7’ MNA556 Fig.6 Timing diagram. 2000 Mar 15 6 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 V VCC DC supply voltage 2.0 5.0 5.5 VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature −40 +25 +85 −40 +25 +85 °C −40 +25 +125 −40 +25 +125 °C tr, tf input rise and fall ratios (∆t/∆V) see DC and AC characteristics per device VCC = 3.3 ±0.3 V − − 100 − − − ns/V VCC = 5 ±0.5 V − − 20 − − 20 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK DC input diode current VI < −0.5 V; note 1 − −20 mA IOK DC output clamping diode current −0.5 > VO > VCC + 0.5 V; note 1 − ±20 mA IO DC output sink current −0.5 < VO < VCC + 0.5 V − ±25 mA ICC DC VCC or GND current − ±75 mA Tstg storage temperature PD power dissipation per package for temperature range: −40 to +125 °C; note 2 −65 +150 °C − 500 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. 2000 Mar 15 7 mW Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 DC CHARACTERISTICS 74AHC family Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH VIL VOH VOL −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. 2.0 1.5 − − 1.5 − 1.5 − V 3.0 2.1 − − 2.1 − 2.1 − V 5.5 3.85 − − 3.85 − 3.85 − V 2.0 − − 0.5 − 0.5 − 0.5 V 3.0 − − 0.9 − 0.9 − 0.9 V 5.5 − − 1.65 − 1.65 − 1.65 V 2.0 1.9 2.0 − 1.9 − 1.9 − V 3.0 2.9 3.0 − 2.9 − 2.9 − V 4.5 4.4 4.5 − 4.4 − 4.4 − V VI = VIH or VIL; IO = −4.0 mA 3.0 2.58 − − 2.48 − 2.40 − V VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V VI = VIH or VIL; IO = 50 µA 2.0 − 0 0.1 − 0.1 − 0.1 V 3.0 − 0 0.1 − 0.1 − 0.1 V 4.5 − 0 0.1 − 0.1 − 0.1 V VI = VIH or VIL; IO = 4.0 mA 3.0 − − 0.36 − 0.44 − 0.55 V VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V − 1.0 − 2.0 µA ±2.5 − ±10.0 µA LOW-level input voltage LOW-level output voltage VCC (V) MIN. HIGH-level input voltage HIGH-level output voltage −40 to +85 25 PARAMETER VI = VIH or VIL; IO = −50 µA II input leakage current VI = VCC or GND 5.5 − − 0.1 IOZ 3-state output OFF-state current VI = VIH or VIL; 5.5 VO = VCC or GND − − ±0.25 − ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 4.0 − 40 − 80 µA CI input capacitance − − 3 10 − 10 − 10 pF 2000 Mar 15 8 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 74AHCT family Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V VI = VIH or VIL; IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V − 1.0 − 2.0 µA ±2.5 − ±10.0 µA VOL LOW-level output voltage II input leakage current VI = VIH or VIL 5.5 − − 0.1 IOZ 3-state output OFF-state current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±0.25 − ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 − − 4.0 − 40 − 80 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 − 1.5 − 1.5 mA CI input capacitance − 3 10 − 10 − 10 pF 2000 Mar 15 − 9 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 AC CHARACTERISTICS Type 74AHC595 GND = 0 V; tr = tf ≤ 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL MIN. −40 to +125 TYP. MAX. MIN. MAX. MIN. MAX. UNIT VCC = 3.0 to 3.6 V; note 1 propagation delay SHCP to Q7’ see Figs 7 and 12 15 pF − 5.7 13.0 1.0 15.0 1.0 16.5 ns propagation delay STCP to Qn see Figs 8 and 12 − 5.9 11.9 1.0 13.5 1.0 15.0 ns tPHL propagation delay MR to Q7’ see Figs 10 and 12 − 5.9 12.8 1.0 13.7 1.0 15.0 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 11 and 12 − 5.6 11.5 1.0 13.5 1.0 15.0 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 5.4 11.0 1.0 13.0 1.0 14.5 ns tPHL/tPLH propagation delay SHCP to Q7’ see Figs 7 and 12 50 pF − 7.7 16.5 1.0 18.5 1.0 20.1 ns propagation delay STCP to Qn see Figs 8 and 12 − 7.7 15.4 1.0 17.0 1.0 18.5 ns tPHL propagation delay MR to Q7’ see Figs 10 and 12 − 7.4 16.3 1.0 17.2 1.0 18.7 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 11 and 12 − 7.4 15.0 1.0 17.0 1.0 18.5 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 8.7 15.7 1.0 16.2 1.0 17.5 ns tW shift clock pulse width see Figs 7 HIGH or LOW and 12 5.0 − − 5.0 − 5.0 − ns storage clock pulse width HIGH or LOW see Figs 8 and 12 5.0 − − 5.0 − 5.0 − ns master reset pulse width LOW see Figs 10 and 12 5.0 − − 5.0 − 5.0 − ns set-up time DS to SHCP see Figs 8 and 12 3.5 − − 3.5 − 3.5 − ns set-up time SHCP to STCP see Figs 9 and 12 8.5 − − 8.5 − 8.5 − ns 1.5 − − 1.5 − 1.5 − ns 3.0 − − 3.0 − 3.0 − ns 80 125 − 60 − 40 − MHz tPHL/tPLH tsu th hold time DS to SHCP trem removal time MR to SHCP fmax maximum clock pulse see Figs 7, 8 frequency and 12 SHCP or STCP 2000 Mar 15 see Figs 10 and 12 10 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL MIN. −40 to +125 TYP. MAX. MIN. MAX. MIN. MAX. UNIT VCC = 4.5 to 5.5 V; note 2 propagation delay SHCP to Q7’ see Figs 7 and 12 15 pF − 4.0 8.2 1.0 9.4 1.0 10.5 ns propagation delay STCP to Qn see Figs 8 and 12 − 4.2 7.4 1.0 8.5 1.0 9.5 ns tPHL propagation delay MR to Q7’ see Figs 10 and 12 − 4.4 8.0 1.0 9.1 1.0 10.0 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 11 and 12 − 4.0 8.6 1.0 10.0 1.0 11.0 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 3.8 8.0 1.0 9.5 1.0 10.5 ns tPHL/tPLH propagation delay SHCP to Q7’ see Figs 7 and 12 50 pF − 5.4 10.0 1.0 11.4 1.0 12.5 ns propagation delay STCP to Qn see Figs 8 and 12 − 5.5 9.0 1.0 10.5 1.0 11.5 ns tPHL propagation delay MR to Q7’ see Figs 10 and 12 − 5.6 10.0 1.0 11.1 1.0 12.0 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 11 and 12 − 5.3 10.6 1.0 12.0 1.0 13.0 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 5.8 10.3 1.0 11.0 1.0 12.0 ns tW shift clock pulse width see Figs 7 HIGH or LOW and 12 5.0 − − 5.0 − 5.0 − ns storage clock pulse width HIGH or LOW see Figs 8 and 12 5.0 − − 5.0 − 5.0 − ns master reset pulse width LOW see Figs 10 and 12 5.0 − − 5.0 − 5.0 − ns set-up time DS to SHCP see Figs 8 and 12 3.0 − − 3.0 − 3.0 − ns set-up time SHCP to STCP see Figs 9 and 12 5.0 − − 5.0 − 5.0 − ns 2.0 − − 2.0 − 2.0 − ns 2.5 − − 2.5 − 2.5 − ns 130 170 − 110 − 90 − MHz tPHL/tPLH tsu th hold time DS to SHCP trem removal time MR to SHCP fmax maximum clock pulse see Figs 7, 8 frequency and 12 SHCP or STCP see Figs 10 and 12 Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. 2000 Mar 15 11 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 Type 74AHCT595 GND = 0 V; tr = tf ≤ 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL MIN. −40 to +125 TYP. MAX. MIN. MAX. MIN. MAX. UNIT VCC = 4.5 to 5.5 V; note 1 propagation delay SHCP to Q7’ see Figs 7 and 12 15 pF − 3.8 8.2 1.0 9.0 1.0 10.0 ns propagation delay STCP to Qn see Figs 8 and 12 − 4.0 7.4 1.0 8.5 1.0 9.5 ns tPHL propagation delay MR to Q7’ see Figs 10 and 12 − 4.6 8.2 1.0 9.5 1.0 10.5 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 11 and 12 − 4.8 9.0 1.0 11.0 1.0 12.0 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 3.6 6.9 1.0 8.0 1.0 9.0 ns tPHL/tPLH propagation delay SHCP to Q7’ see Figs 7 and 12 50 pF − 5.2 10.0 1.0 11.0 1.0 12.0 ns propagation delay STCP to Qn see Figs 8 and 12 − 5.3 9.0 1.0 10.5 1.0 11.5 ns tPHL propagation delay MR to Q7’ see Figs 10 and 12 − 5.8 10.5 1.0 11.5 1.0 12.5 ns tPZH/tPZL 3-state output enable time OE to Qn see Figs 11 and 12 − 6.2 11.6 1.0 13.0 1.0 14.5 ns tPHZ/tPLZ 3-state output disable time OE to Qn − 5.8 10.3 1.0 11.0 1.0 12.0 ns tW shift clock pulse width see Figs 7 HIGH or LOW and 12 5.0 − − 5.0 − 5.0 − ns storage clock pulse width HIGH or LOW see Figs 8 and 12 5.0 − − 5.0 − 5.0 − ns master reset pulse width LOW see Figs 10 and 12 5.0 − − 5.0 − 5.0 − ns set-up time SHCP to STCP see Figs 8 and 12 5.0 − − 5.0 − 5.0 − ns set-up time DS to SHCP see Figs 9 and 12 3.0 − − 3.0 − 3.0 − ns 2.0 − − 2.0 − 2.0 − ns tPHL/tPLH tsu th hold time DS to SHCP trem removal time MR to SHCP see Figs 10 and 12 3.0 − − 3.0 − 3.0 − ns fmax maximum clock pulse frequency SHCP or STCP see Figs 7, 8 and 12 130 170 − 110 − 90 − MHz Note 1. Typical values at VCC = 5.0 V. 2000 Mar 15 12 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 AC WAVEFORMS 1/fmax handbook, full pagewidth VI VM(1) SHCP input GND tW t PHL t PLH VOH VM(2) Q 7' output VOL FAMILY VM(1) INPUT VI INPUT REQUIREMENTS MNA557 VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V Fig.7 50% VCC The clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width (tW) and maximum shift clock frequency (fmax). VI handbook, full pagewidth VM(1) SHCP input GND 1/fmax t su VI VM(1) STCP input GND tW t PHL t PLH VOH VM(2) Q n output VOL FAMILY VI INPUT REQUIREMENTS VM(1) INPUT MNA558 VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V Fig.8 50% VCC The storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width (tW) and the shift clock to storage clock set-up time (tsu). 2000 Mar 15 13 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 VI handbook, full pagewidth VM(1) SHCP input GND t su t su th th VI VM(1) DS input GND VOH VM(2) Q 7' output VOL FAMILY VI INPUT REQUIREMENTS MNA560 VM(1) INPUT VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. 50% VCC Fig.9 The data set-up (tsu) and hold (th) times for the DS input. VI handbook, full pagewidth VM(1) MR input GND tW t rem VI VM(1) SHCP input GND t PHL VOH VM(2) Q 7' output VOL FAMILY VI INPUT REQUIREMENTS VM(1) INPUT MNA561 VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.10 The master reset (MR) pulse width, the master reset to output (Q7’) propagation delays and the master reset to shift clock (SHCP) removal time (trem). 2000 Mar 15 14 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 VI handbook, full pagewidth VM(1) OE input GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM(2) VOL + 0.3 V VOL tPHZ tPZH VOH VOH − 0.3 V output HIGH-to-OFF OFF-to-HIGH VM(2) GND outputs enabled outputs enabled outputs disabled MNA450 FAMILY VI INPUT REQUIREMENTS VM(1) INPUT VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.11 3-state enable and disable times. S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO VCC open GND D.U.T. CL RT MNA219 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”). RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.12 Load circuitry for switching times. 2000 Mar 15 15 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.050 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.041 0.228 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 2000 Mar 15 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 16 o 8 0o Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 2000 Mar 15 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-04-04 99-12-27 MO-153 17 o Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state SOLDERING 74AHC595; 74AHCT595 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2000 Mar 15 18 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74AHC595; 74AHCT595 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613507/01/pp20 Date of release: 2000 Mar 15 Document order number: 9397 750 06822