INTEGRATED CIRCUITS 74ALS161B/74ALS163B 4-bit binary counter Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B 74ALS161B/74ALS163B 4-bit binary counter, asynchronous reset 4-bit binary counter, synchronous reset FEATURES DESCRIPTION • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive edge-triggered clock • Asynchronous reset (74ALS161B) • Synchronous reset (74ALS163B) • High speed synchronous expansion • Typical count rate of 140MHz Synchronous presettable 4-bit binary counters (74ALS161B, 74ALS163B) feature an internal carry look-ahead and can be used for high speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the parallel enable (PE) input disables the counting action and causes the data at the D0 – D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at count enable (CEP, CET) inputs. TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74ALS161B 140MHz 10mA 74ALS163B 140MHz 10mA TYPE A Low level at the master reset (MR) input sets all the four outputs of the flip-flops (Q0 – Q3) in 74ALS161B to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 74ALS163B the clear function is synchronous. A Low level at the synchronous reset (SR) input sets all four outputs of the flip-flops (Q0 – Q3) to Low levels after the next positive-going transition on the clock (CP) input ( provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at CP, PE, CET and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate (see Figure 1). ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 16-pin plastic DIP 74ALS161BN, 74ALS163BN SOT38-4 16-pin plastic SO 74ALS161BD, 74ALS163BD SOT109-1 16-pin plastic SSOP Type II 74ALS161BDB, 74ALS163BDB SOT338-1 The carry look-ahead simplifies serial cascading of the counters. Both count enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2). The TC output is subjected to decoding spikes due to internal race conditions, Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 1.0/1.0 20µA/0.1mA CEP Count enable parallel input (active-Low) 1.0/1.0 20µA/0.1mA CET Count enable trickle input (active-Low) 1.0/1.0 20µA/0.1mA CP Clock input (active rising edge) 1.0/1.0 20µA/0.1mA PE Parallel enable input (active-Low) 1.0/1.0 20µA/0.1mA MR Asynchronous master reset input (active-Low) for 74ALS161B 1.0/1.0 20µA/0.1mA SR Asynchronous reset input (active-Low) for 74ALS163B 1.0/1.0 20µA/0.1mA Flip-flop outputs 20/80 0.4mA/8mA Terminal count output (active-Low) 20/80 0.4mA/8mA PINS D0 – D3 Q0 – Q3 TC DESCRIPTION NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. 1991 Feb 08 2 853–1350 01670 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B STATE DIAGRAM 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 SF00664 APPLICATIONS VCC PE D0 D1 D2 D3 CEP CET CLOCK 74ALS163B TC CP SR Q0 Q1 Q2 Q3 SC00086 Figure 1. Maximum Count Modifying Scheme Terminal Count = 6 H H = Enable count or L L = Disable count D0 D1 D2 D3 PE CEP 74ALS163B CET TC D0 D1 D2 D3 PE CEP 74ALS163B CET TC D0 D1 D2 D3 PE CEP 74ALS163B CET TC D0 D1 D2 D3 PE CEP 74ALS163B CET TC D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP CP CP CP CP SR Q0 Q1 Q2 Q3 SR Q0 Q1 Q2 Q3 SR Q0 Q1 Q2 Q3 SR Q0 Q1 Q2 Q3 SR Q0 Q1 Q2 Q3 CP SC00087 Figure 2. Synchronous Multistage Counting Scheme 1991 Feb 08 3 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B PIN CONFIGURATION – 74ALS161B PIN CONFIGURATION – 74ALS163B MR 1 16 VCC SR 1 16 VCC CP 2 15 TC CP 2 15 TC D0 3 14 Q0 D0 3 14 Q0 D1 4 13 Q1 D1 4 13 Q1 D2 5 12 Q2 D2 5 12 Q2 D3 6 11 Q3 D3 6 11 Q3 CEP 7 10 CET CEP 7 10 CET GND 8 9 PE GND 8 9 PE SF00656 SF00657 LOGIC SYMBOL – 74ALS161B 9 PE 7 CEP 10 CET 3 4 5 D0 D1 D2 LOGIC SYMBOL – 74ALS163B D3 TC 15 9 PE 7 CEP 10 CET 2 CP 2 CP 1 MR 1 SR Q0 Q1 Q2 Q3 14 13 12 11 VCC = Pin 16 GND = Pin 8 3 4 5 D0 D1 D2 6 6 D3 TC Q0 Q1 Q2 Q3 14 13 12 11 VCC = Pin 16 GND = Pin 8 15 SF00658 SF00659 IEC/IEEE SYMBOL – 74ALS161B 1 9 7 10 2 3 IEC/IEEE SYMBOL – 74ALS163B CTR DIV 16 R 1 9 M1 7 G3 10 G4 2 C2 /1,3,4+ CTR DIV 16 M1 G3 G4 C2 /1,3,4+ 14 3 4 13 4 13 5 12 5 12 6 11 6 11 1,2 D 4 CT=15 15 14 1,2 D 4 CT=15 SF00660 1991 Feb 08 2R 15 SF00661 4 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B LOGIC DIAGRAM – 74ALS161B CP MR PE CET CEP D0 2 1 9 10 7 3 D R Q CP D1 14 Q Q0 4 D R Q CP D2 13 Q Q1 5 D R Q CP D3 12 Q Q2 6 D R Q CP 11 Q 15 VCC = Pin 16 GND = Pin 8 INPUTS OUTPUTS MR CP CEP CET PE Dn Qn TC L X X X X X L L H ↑ X X l l L L H ↑ X X l h H (a) H ↑ h h h X count (a) h X l X h X qn (a) h X X l h X qn L OPERATING MODE Reset (clear) Parallel load Count Hold (do nothing) High-voltage level High state must be present one setup time before the Low-to-High clock transition Low-voltage level Low state must be present one setup time before the Low-to-High clock transition Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Don’t care The output is High when CET is High and the counter is at terminal count (HHHH) Low-to-High clock transition 1991 Feb 08 TC SF00662 MODE SELECTION FUNCTION TABLE – 74ALS161B H = h = L = l = qn = X = (a) = ↑ = Q3 5 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B LOGIC DIAGRAM – 74ALS163B CP SR PE CET CEP D0 D1 D2 D3 2 1 9 10 7 3 D Q CP Q D Q CP Q D Q CP Q D Q CP Q 14 4 13 12 Q2 6 11 VCC = Pin 16 GND = Pin 8 Q3 TC SF00663 MODE SELECTION FUNCTION TABLE – 74ALS163B INPUTS OUTPUTS SR CP CEP CET PE Dn Qn TC l ↑ X X X X L L h ↑ X X l l L L h ↑ X X l h H (a) h ↑ h h h X count (a) h X l X h X qn (a) h X X l h X qn L OPERATING MODE Reset (clear) Parallel load Count Hold (do nothing) High-voltage level High state must be present one setup time before the Low-to-High clock transition Low-voltage level Low state must be present one setup time before the Low-to-High clock transition Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Don’t care The output is High when CET is High and the counter is at terminal count (HHHH) Low-to-High clock transition 1991 Feb 08 Q1 5 15 H = h = L = l = qn = X = (a) = ↑ = Q0 6 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) PARAMETER SYMBOL RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 16 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –0.4 mA IOL Low-level output current 8 mA +70 °C Tamb Operating free-air temperature range V V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 LIMITS MIN TYP2 MAX UNIT VOH O High level output voltage High-level VCC = ±10%,, VIL = MAX,, VIH = MIN VOL O Low level output voltage Low-level VCC = MIN,, VIL = MAX,, VIH = MIN VIK Input clamp voltage VCC = MIN, II = IIK II Input current at minimum input voltage VCC = MAX, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.4V –0.1 mA IO Output current3 VCC = MAX, VO = 2.25V –112 mA ICC Supply current (total) VCC = MAX 21 mA IOH 0 4mA O = –0.4mA VCC – 2 IOL = 4mA IOL = 8mA V 0.25 0.40 V 0.35 0.50 V –0.73 –1.5 V 0.1 mA –30 10 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 1991 Feb 08 7 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 100 tPLH tPHL Propagation delay CP to Qn Waveform 1 4.0 6.0 13.0 16.0 MHz ns tPLH tPHL Propagation delay CP to TC Waveform 1 6.0 8.0 16.0 16.0 ns tPLH tPHL Propagation delay CET to TC Waveform 2 3.0 3.0 10.0 10.0 ns tPHL Propagation delay MR to Qn 74ALS161B Waveform 3 8.0 15.0 ns tPHL Propagation delay MR to TC 74ALS163B Waveform 3 11.0 19.0 ns AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN tsu(H) tsu(L) Setup time, High or Low Dn to CP th(H) th(L) UNIT MAX Waveform 6 8.0 8.0 ns Hold time, High or Low Dn to CP Waveform 6 0.0 0.0 ns tsu(H) tsu(L) Setup time, High or Low PE or SR to CP Waveform 5 or 6 10.0 10.0 ns th(H) th(L) Hold time, High or Low PE or SR to CP Waveform 6 0.0 0.0 ns tsu(H) tsu(L) Setup time, High or Low CET or CEP to CP Waveform 4 10.0 10.0 ns th(H) th(L) Hold time, High or Low CET or CEP to CP Waveform 4 0.0 0.0 ns tw(H) tw(L) CP Pulse width (load), High or Low Waveform 1 5.0 5.0 ns tw(H) tw(L) CP Pulse width (count), High or Low Waveform 1 5.0 5.0 ns tw(L) MR or SR Pulse width, Low Waveform 3 5.0 ns tREC Recovery time, CR or SR to CP Waveform 3 10.0 ns 1991 Feb 08 8 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B AC WAVEFORMS For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP VM VM tw(H) VM tw(L) tPLH CET tPHL VM tPLH VM Qn, TC VM VM tPHL VM TC VM SC00088 SF00668 Waveform 2. Propagation Delay for CET to TC Output Waveform 1. Propagation Delay for Clock Input to Output, Clock PUlse Width, and Maximum Clock Frequency tw(L) MR VM VM CEP tREC CET VM VM tsu(H) VM CP VM tPHL th(H) VM tsu(L) th(L) VM CP VM VM Qn, TC SF00669 SC00089 Waveform 3. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time Waveform 4. CEP and CET Setup and Hold Times Dn SR VM VM VM tsu(L) CP th(L) VM VM tsu tsu(H) th(H) PE VM th VM VM tsu(L) VM CP SC00090 th(L) VM VM VM tsu(H) th(H) VM SC00091 Waveform 6. Data and Parallel Enable Setup and Hold Times Waveform 5. Synchronous Reset Setup and Hold Times 1991 Feb 08 VM 9 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B/74ALS163B TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN CL RL AMP (V) VM 10% D.U.T. RT 90% VM VOUT PULSE GENERATOR tw 90% 10% tTHL (tff) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0.3V AMP (V) 90% Test Circuit for Totem-pole Outputs POSITIVE PULSE 90% VM VM 10% 10% tw 0.3V Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate tw tTLH tTHL 1MHz 500ns 2.0ns 2.0ns SC00005 1991 Feb 08 10 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B DIP16: plastic dual in-line package; 16 leads (300 mil) 1991 Feb 08 11 SOT38-4 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B SO16: plastic small outline package; 16 leads; body width 3.9 mm 1991 Feb 08 12 SOT109-1 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1991 Feb 08 13 SOT338-1 Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1991 Feb 08 14