74LVX174 LOW VOLTAGE CMOS HEX D-TYPE FLIP-FLOP WITH CLEAR WITH 5V TOLERANT INPUTS ■ HIGH SPEED: fMAX = 180MHz (TYP.) at VCC = 3.3V ■ 5V TOLERANT INPUTS ■ INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V at VCC=3V ■ LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C ■ LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V ■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) ■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL ■ OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) ■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 ■ IMPROVED LATCH-UP IMMUNITY ■ POWER DOWN PROTECTION ON INPUTS DESCRIPTION The 74LVX174 is a low voltage CMOS HEX D-TYPE FLIP FLOP WITH CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. SOP TSSOP Table 1: Order Codes PACKAGE T&R SOP TSSOP 74LVX174MTR 74LVX174TTR Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols August 2004 Rev. 3 1/12 74LVX174 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL NAME AND FUNCTION 1 CLEAR 2, 5, 7, 10, 12, 15 3, 4, 6, 11, 13, 14 9 Q0 to Q5 Asynchronous Master Reset (Active LOW) Flip-Flop Outputs D0 to D5 Data Inputs CLOCK 8 16 GND VCC Clock Input (LOW-to-HIGH, Edge Triggered) Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS OUTPUTS FUNCTION CLEAR D CLOCK Q L X X L H L L H H H H X Qn X : Don’t Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/12 CLEAR NO CHANGE 74LVX174 Table 4: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 - 20 V mA ± 20 mA ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Value ± 25 mA ± 50 mA -65 to +150 °C 300 °C Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 5: Recommended Operating Conditions Symbol VCC Parameter Supply Voltage (note 1) Value Unit 2 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage 0 to VCC V Top Operating Temperature dt/dv Input Rise and Fall Time (note 2) (VCC = 3.3V) -55 to 125 °C 0 to 100 ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2.0V Table 6: DC Specifications Test Condition Symbol VIH VIL VOH VOL II ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 3.0 3.6 2.0 3.0 3.6 Typ. Max. 1.5 2.0 2.4 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 2.0 2.4 0.5 0.8 0.8 Max. 1.5 2.0 2.4 0.5 0.8 0.8 Unit V 0.5 0.8 0.8 V 2.0 IO=-50 µA 3.0 3.0 2.0 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=4 mA 0.36 0.44 0.55 3.6 VI = 5V or GND ± 0.1 ±1 ±1 µA 3.6 VI = VCC or GND 4 40 40 µA 1.9 2.0 IO=-50 µA 2.9 3.0 IO=-4 mA 2.58 1.9 1.9 2.9 2.9 2.48 2.4 V V 3/12 74LVX174 Table 7: Dynamic Switching Characteristics Test Condition Symbol VOLP VOLV VIHD VILD Parameter TA = 25°C VCC (V) Dynamic Low Voltage Quiet Output (note 1, 2) Min. 3.3 Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) Value -0.8 3.3 CL = 50 pF Typ. Max. 0.3 0.8 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. -0.3 2 V 3.3 0.8 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. Table 8: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time CLOCK to Q tPLH tPHL Propagation Delay Time CLEAR to Q tWL tW tS th tREM fMAX tOSLH tOSHL CLEAR pulse Width, HIGH CLOCK pulse Width Setup Time Q to CLOCK HIGH or LOW Hold Time Q to CLOCK HIGH or LOW Recovery Time CLEAR to Q Maximum Clock Frequency Output To Output Skew Time (note1, 2) VCC (V) CL (pF) 2.7 2.7 Value TA = 25°C Min. -40 to 85°C -55 to 125°C Typ. Max. Min. Max. Min. Max. 15 50 7.6 10.1 14.5 18.0 1.0 1.0 17.5 21.0 1.0 1.0 18.5 22.0 3.3(*) 15 5.9 9.3 1.0 11.0 1.0 12.0 3.3(*) 2.7 2.7 50 8.4 12.8 1.0 14.5 1.0 15.5 15 50 7.9 10.4 15.0 18.5 1.0 1.0 18.5 22.0 1.0 1.0 19.5 23.0 3.3(*) 15 6.2 9.7 1.0 11.5 1.0 12.5 3.3(*) 2.7 50 8.7 13.2 1.0 15.0 1.0 16.0 Unit ns ns (*) 6.5 5.0 7.5 5.0 7.5 5.0 ns (*) 6.5 5.0 7.5 5.0 7.5 5.0 ns 3.3(*) 7.5 5.0 8.5 6.0 8.5 6.0 ns 0.0 0.0 0.0 0.0 0.0 0.0 ns 4.5 3.0 4.5 3.0 3.3 2.7 3.3 2.7 2.7 (*) 3.3 2.7 3.3(*) 2.7 2.7 15 50 65 45 130 60 55 40 3.3(*) 15 115 180 95 3.3(*) 2.7 50 65 50 3.3(*) 50 95 0.5 0.5 ns MHz 55 1.0 1.0 1.5 1.5 1.5 1.5 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V 4/12 74LVX174 Table 9: Capacitive Characteristics Test Condition Symbol Parameter TA = 25°C VCC (V) CIN Input Capacitance 3.3 CPD Power Dissipation Capacitance (note 1) 3.3 Value Min. Typ. Max. 5 fIN = 10MHz 23 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) Figure 4: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) Figure 5: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) 5/12 74LVX174 Figure 6: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 7: Waveform - Recovery Time, Minimum Pulse Width (f=1MHz; 50% duty cycle) 6/12 74LVX174 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.25 a2 MAX. 0.004 0.010 1.64 0.063 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8° (max.) 0016020D 7/12 74LVX174 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.60 0.0256 BSC 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 8/12 74LVX174 Tape & Reel SO-16 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.45 6.65 0.254 0.262 Bo 10.3 10.5 0.406 0.414 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 9/12 74LVX174 Tape & Reel TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 10/12 TYP 0.504 22.4 0.519 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 74LVX174 Table 10: Revision History Date Revision 27-Aug-2004 3 Description of Changes Ordering Codes Revision - pag. 1. 11/12 74LVX174 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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