ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER GENERAL DESCRIPTION FEATURES The ICS813252I-02 is a member of the ICS HiperClockS™ family of high performance clock HiPerClockS™ solutions from IDT. The ICS813252I-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock™ frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range. • Two LVPECL outputs Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz • Attenuates the phase jitter of the input clock by using a lowcost pullable fundamental mode VCXO crystal • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection • FemtoClock frequency multiplier provides low jitter, high frequency output • Absolute pull range: 50ppm • FemtoClock VCO frequency: 625MHz • RMS phase jitter @ 125MHz, using a 25MHz crystal (10kHz – 20MHz): 1.3ps (maximum) • 3.3V supply voltage • -40°C to 85°C ambient operating temperature PIN ASSIGNMENT • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages nCLK1 VCC CLK1 CLK0 nCLK0 XTAL_OUT VCCX XTAL_IN 32 31 30 29 28 27 26 25 LF1 1 24 VEE LF0 2 23 nQB ISET 3 22 QB VEE 4 21 VCCO CLK_SEL 5 20 nQA VCC 6 19 QA RESERVED 7 18 VEE VEE 8 17 ODASEL_0 ICS813252I-02 ODASEL_1 ODBSEL_0 ODBSEL_1 VCC VCCA PDSEL_0 PDSEL_1 PDSEL_2 9 10 11 12 13 14 15 16 32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 1 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER XTAL_IN LF1 LF0 ISET Loop Filter XTAL_OUT BLOCK DIAGRAM 25MHz Output Divider PDSEL_[2:0] Pullup CLK0 0 nCLK0 CLK1 1 nCLK1 CLK_SEL Pulldown VCXO Input Pre-Divider 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 111 = 19440 (default) 00 = 25 (default) 01 = 5 10 = 4 11 = 2 Phase Detector 2 VCXO Charge Pump VCXO Feedback Divider ÷3125 VCXO Jitter Attenuation PLL FemtoClock PLL 625MHz Output Divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2 2 IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 2 QA nQA ODASEL_[1:0] QB nQB ODBSEL_[1:0] CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 1. PIN DESCRIPTIONS Number Name Type Analog Input/Output Analog Input/Output Power 1, 2 LF1, LF0 3 ISET 4 , 8, 1 8 , 2 4 VEE 5 CLK_SEL Input 6, 12, 27 VCC Power 7 9, 10, 11 13 14, 15 16, 17 19, 20 RESERVED PDSEL_2, PDSEL_1, PDSEL_0 VCCA ODBSEL_1, ODBSEL_0 ODASEL_1, ODASEL_0 QA, nQA Reserved 21 VCCO Power 22, 23 QB, nQB Output Input Power Input Input Output 25 nCLK1 Input 26 CLK1 Input 28 nCLK0 Input 29 30, 31 CLK0 XTAL_OUT, XTAL_IN Input 32 VCCX Power Description Loop filter connection node pins. LF0 is the output. LF1 is the input. Charge pump current setting pin. Negative supply pins. Input clock select. When HIGH selects CLK1/nCLK1. Pulldown When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels. Core power supply pins. Reserved pin. Do not connect. Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. Analog supply pin. Frequency select pins for Bank B output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Frequency select pins for Bank A output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Differential Bank A clock outputs. LVPECL interface levels. Output power supply pin. Differential Bank B clock outputs. LVPECL interface levels. Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Input Inver ting differential clock input. VCC/2 bias voltage when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 bias voltage when left floating. Non-inver ting differential clock input. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Power supply pin for VCXO charge pump. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER Test Conditions 3 Minimum Typical Maximum Units CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 3A. PRE-DIVIDER FUNCTION TABLE Inputs PDSEL_2 PDSEL_1 PDSEL_0 0 0 0 0 0 1 TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE Inputs Pre-Divider Value Output Divider Value ODxSEL_1 ODxSEL_0 1 0 0 25 (default) 193 0 1 5 0 1 0 256 1 0 4 0 1 1 2430 1 1 2 1 0 0 3125 1 0 1 9720 1 1 0 15625 1 1 1 19440 (default) IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 4 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 3C. FREQUENCY FUNCTION TABLE Input Frequency (MHz) Pre-Divider Value VCXO Frequency (MHz) FemtoClock Feedback Divider Value Femtoclock VCO Frequency (MHz) Output Divider Value Output Frequency (MHz) 0.008 1 25 25 625 25 25 0.008 1 25 25 625 5 125 0.008 1 25 25 625 4 156.25 0.008 1 25 25 625 2 312.5 1.544 193 25 25 625 25 25 1.544 193 25 25 625 5 125 1.544 193 25 25 625 4 156.25 1.544 193 25 25 625 2 312.5 2.048 256 25 25 625 25 25 2.048 256 25 25 625 5 125 2.048 256 25 25 625 4 156.25 2.048 256 25 25 625 2 312.5 19.44 2430 25 25 625 25 25 19.44 2430 25 25 625 5 125 19.44 2430 25 25 625 4 156.25 19.44 2430 25 25 625 2 312.5 25 3125 25 25 625 25 25 25 3125 25 25 625 5 125 25 3125 25 25 625 4 156.25 25 3125 25 25 625 2 312.5 77.76 9720 25 25 625 25 25 77.76 9720 25 25 625 5 125 77.76 9720 25 25 625 4 156.25 77.76 9720 25 25 625 2 312.5 125 15625 25 25 625 25 25 125 15625 25 25 625 5 125 125 15625 25 25 625 4 156.25 125 15625 25 25 625 2 312.5 155.52 19440 25 25 625 25 25 155.52 19440 25 25 625 5 125 155.52 19440 25 25 625 4 156.25 155.52 19440 25 25 625 2 312.5 IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 5 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Test Conditions VCC Core Supply Voltage VCCA Analog Supply Voltage VCCO Output Supply Voltage Minimum Typical Maximum Units 3.135 3. 3 3.465 V VCC – 0.15 3.3 VCC V 3.135 3. 3 3.465 V 3.135 3. 3 VCCX Charge Pump Supply Voltage 3.465 V IEE Power Supply Current 235 mA ICCA Analog Supply Current 15 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage CLK_SEL, ODASEL_[0:1], Input High Current ODBSEL_[0:1] PDSEL[0:2] CLK_SEL, ODASEL_[0:1], Input Low Current ODBSEL_[0:1] IIH IIL PDSEL[0:2] IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER Minimum Typical TO 85°C Maximum Units 2 VCC + 0.3 V -0.3 0.8 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA VCC = 3.465V, VIN = 0V -5 µA VCC = 3.465V, VIN = 0V -150 µA 6 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 150 µA CLK0/nCLK0, CLK1/nCLK1 CLK0, CLK1 VIN = 0V, VCC = 3.465V -5 µA nCLK0, nCLK1 VIN = 0V, VCC = 3.465V -150 µA IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 VIN = VCC = 3.465V VCMR Common Mode Input Voltage; NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. 0.15 1.3 V VEE + 0.5 VCC - 0.85 V TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1. 0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. AC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter fIN Input Frequency fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tjit(acc) Accumulated Jitter, RMS; NOTE 2 tjit(pk-pk) Peak-to-Peak Jitter tsk(o) Output Skew; NOTE 2, 3 odc Output Duty Cycle t R / tF Output Rise/Fall Time Test Conditions Minimum Maximum Units 0.008 155.52 MHz 25 312.5 MHz 1.3 ps 10 ps 35 ps 75 ps 125MHz fOUT, 25MHz cr ystal Integration Range: 10kHz – 20MHz 125MHz fOUT, 25MHz cr ystal, 20K Cycles 100K Random Cycles Typical 45 55 % 200 700 ps PLL Lock Time 175 tLOCK Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth. Refer to VCXO-PLL Loop Bandwidth Selection Table. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load condtions. Measured at the output differential cross points. ms IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 20% to 80% 7 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TYPICAL PHASE NOISE @ 125MHZ 125MHz Z (dBc H ) PHASE NOISE RMS Phase Jitter (Random) 10kHz to 20MHz = 0.98ps (typical) OFFSET FREQUENCY (HZ) IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 8 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PARAMETER MEASUREMENT INFORMATION 2V 2V VCC VCC, VCCO, VCCX VCCA Qx SCOPE nCLK0, nCLK1 V V Cross Points PP CMR CLK0, CLK1 LVPECL nQx VEE VEE -1.3V ± 0.165V DIFFERENTIAL INPUT LEVEL 3.3V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power nFOUTx FOUTx Phase Noise Mask nFOUTy FOUTy f1 Offset Frequency tsk(o) f2 RMS Jitter = Area Under the Masked Phase Noise Plot OUTPUT SKEW PHASE JITTER nQA, nQB nQA, nQB 80% 80% QA, QB VSW I N G QA, QB t PW t 20% 20% tR tF odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD OUTPUT RISE/FALL TIME IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 9 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES 3.3V As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813252I-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCX, VCCA, and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. VDD .01µF 10Ω VDDX 10Ω .01µF 10µF VDDA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VCC R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 10 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 2.5V FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK HCSL *R4 33 R1 50 R2 50 nCLK HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 11 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER VFQFN EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical performance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 12 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 5A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 84Ω FIGURE 5B. LVPECL OUTPUT TERMINATION 13 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER SCHEMATIC EXAMPLE Figure 6 shows an example of the ICS813252I-02 application schematic. In this example, the device is operated at VCC = VCCX = VCCO = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. An optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used. FIGURE 6. ICS813252I-02 S CHEMATIC EXAMPLE IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 14 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (C L ). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a cr ystal also var ies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependent on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows RS, C S and C P values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not r un under neath the device, loop filter or crystal components. The crystal’s load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal’s CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal’s CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than LF0 LF1 ISET RS CP RSET CS XTAL_IN CTUNE 25MHz XTAL_OUT CTUNE VCXO CHARACTERISTICS TABLE Symbol Parameter Typical Unit kVCXO VCXO Gain 15,700 Hz/V CV_LOW Low Varactor Capacitance 9.9 pF CV_HIGH High Varactor Capacitance 22.2 pF VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE Bandwidth Crystal Frequency (MHz) RS (kΩ ) CS (µF) CP (µF) RSET (kΩ ) 10Hz (Low) 25MHz 121 1.0 0.01 9.09 90Hz (Mid) 25MHz 22 1 0.1 0.001 2.21 300Hz (High) 25MHz 680 0.1 0.0001 2.21 CRYSTAL CHARACTERISTICS Symbol Parameter fN Frequency fT Frequency Tolerance fS Frequency Stability Minimum Mode of Operation Operating Temperature Range Typical Maximum Units Fundamental 25 MHz -40 ±20 ppm ±20 ppm 85 °C CL Load Capacitance 10 pF CO Shunt Capacitance 4 pF CO /C1 Pullability Ratio ESR Equivalent Series Resistance 22 0 24 0 20 Drive Level Aging @ 25°C IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 1 mW ±3 per year ppm 15 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS813252I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS813252I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 235mA = 814.275mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 814.275mW + 60mW = 874.275mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.874W * 37°C/W = 117.3°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 32 LEAD VFQFN, FORCED CONVECTION θ JA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 16 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V – 2V. CCO • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (V CCO_MAX • –V OH_MAX ) = 0.9V For logic low, VOUT = V OL_MAX =V CC_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX – 2V))/R ] * (V CCO_MAX L –V OH_MAX ) = [(2V – (V CCO_MAX –V OH_MAX ))/R ] * (V CCO_MAX L –V OH_MAX )= [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX –V OL_MAX ) = [(2V – (V CCO_MAX –V OL_MAX ))/R ] * (V L CCO_MAX –V OL_MAX )= [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 17 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN θ JA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W TRANSISTOR COUNT The transistor count for ICS813252I-02 is: 6579 IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 18 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN NOTE: The above mechanical package drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4) SYMBOL Minimum Maximum 32 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 8 NE 8 D, E 5.0 BASIC D2, E2 3.0 3.3 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 19 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 813252CKI-02 ICS3252CI02 32 Lead VFQFN tray -40°C to 85°C 813252CKI-02T ICS3252CI02 32 Lead VFQFN 2500 tape & reel -40°C to 85°C 813252CKI-02LF ICS352CI02L 32 Lead "Lead-Free" VFQFN tray -40°C to 85°C 813252CKI-02LFT ICS352CI02L 32 Lead "Lead-Free" VFQFN 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 20 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER REVISION HISTORY SHEET Rev Table Page A T9 20 Description of Change Date Ordering Information Table - added ICS prefix in the Par t/Order Number. IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 21 5/6/08 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA