Differential-to-0.7V HCSL Differential PCI EXPRESS™ Jitter Attenuator ICS871002I-02 DATA SHEET General Description Features The ICS871002I-02 is a high performance Jitter Attenuator designed for use in PCI Express™systems. HiPerClockS™ In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS871002I-02 has two PLL bandwidth modes: 350kHz and 2200kHz. The 350kHz mode provides the maximum jitter attenuation, but it also results in higher PLL tracking time. In this mode, the spread spectrum modulation may also be attenuated. The 2200kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. The ICS871002I-02 can be set for different modes using the F_SELx pins as shown in Table 3C. • • • Two 0.7V HCSL differential output pairs • • • • • Input frequency range: 98MHz to 128MHz • • • Full 3.3V supply mode ICS One differential clock input CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL Output frequency range: 98MHz to 640MHz VCO range: 490MHz - 640MHz Cycle-to-cycle jitter: 45ps (maximum) Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages The ICS871002I-02 uses IDT 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a small 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. PLL Bandwidth (typical) Table BW_SEL 0 = PLL Bandwidth: ~350kHz (default) 1 = PLL Bandwidth: ~2200kHz Block Diagram IREF OE Pullup F_SEL[1:0] Pullup:Pulldown 2 Pin Assignment nQ0 IREF FB_OUT nFB_OUT MR BW_SEL F_SEL1 VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 VDD Q1 nQ1 nFB_IN FB_IN GND nCLK CLK OE ICS871002I-02 BW_SEL Pulldown 0 = 350kHz 1 = 2200kHz CLK Pulldown Phase Detector nCLK Pullup VCO Output Divider 00 ÷5 01 ÷4 10 ÷2 (default) 11 ÷1 nQ0 490 - 640 MHz Q1 nQ1 FB_IN Pulldown nFB_IN Pullup 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ÷5 (fixed) FB_OUT nFB_OU MR Pulldown ICS871002AGI-02 REVISION A APRIL 14, 2010 Q0 1 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 1. Pin Descriptions Number Name 1, 20 nQ0, nQ0 Output Type 2 IREF Input 3, 4 FB_OUT, nFB_OUT Output Description Differential output pair. HCSL interface levels. A fixed precision resistor (475Ω) from this pin to ground provides a reference current used for differential current-mode Qx/nQx clock outputs. Differential feedback output pair. HCSL interface levels. 5 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx, FB_OUT) to go low and the inverted outputs (nQx, nFB_OUT) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6 BW_SEL Input Pulldown PLL Bandwidth select input. 0 = 350kHz, 1 = 2200kHz. See Table 3B. 7, 9 F_SEL1, F_SEL0 Input Pullup Pulldown Frequency select pins. See Table 3C. LVCMOS/LVTTL interface levels 8 VDDA Power Analog supply pin. 10, 19 VDD Power Core supply pins. 11 OE Input Pullup 12 CLK Input Pulldown 13 nCLK Input Pullup 14 GND Power 15 FB_IN Input Pulldown 16 nFB_IN Input Pullup 17, 18 nQ1, Q1 Output Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Non-inverting differential feedback clock input. Inverting differential feedback clock input. Differential output pair. HCSL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS871002AGI-02 REVISION A APRIL 14, 2010 Test Conditions 2 Minimum Typical Maximum Units ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Function Tables Table 3A. Output Enable Function Table Input Outputs OE Q[1:0], nQ[1:0] FB_OUT, nFB_OUT 0 High-Impedance Enabled 1 (default) Enabled Enabled Table 3B. PLL Bandwidth Control Table Input BW_SEL PLL Bandwidth 0 350kHz (default) 1 2200kHz Table 3C. F_SELx Function Table Inputs Input Frequency (MHz) F_SEL1 F_SEL0 Divider Output Frequency (MHz) 100 0 0 ÷5 100 100 0 1 ÷4 125 100 1 0 ÷2 250 (default) 100 1 1 ÷1 500 ICS871002AGI-02 REVISION A APRIL 14, 2010 3 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 86.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Analog Supply Voltage IDD IDDA Test Conditions Minimum Typical Maximum Units 2.97 3.3 3.63 V VDD – 0.12 3.3 VDD V Power Supply Current 75 mA Analog Supply Current 12 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current OE, F_SEL1 VDD = VIN = 3.63V 5 µA BW_SEL, F_SEL0, MR VDD = VIN = 3.63V 150 µA OE, F_SEL1 VDD = 3.63V, VIN = 0V -150 µA BW_SEL, F_SEL0, MR VDD = 3.63V, VIN = 0V -5 µA Table 4C. Differential DC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units CLK, FB_IN VDD = VIN = 3.465V 150 µA nCLK, nFB_IN VDD = VIN = 3.465V 5 µA CLK, FB_IN VDD = 3.465V, VIN = 0V -5 µA nCLK, nFB_IN VDD = 3.465V, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. ICS871002AGI-02 REVISION A APRIL 14, 2010 4 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 5. 0.7V HCSL Differential AC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum 98 Typical Maximum Units 640 MHz 45 ps 1150 mV fMAX Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 VMAX Absolute Max. Output Voltage; NOTE 2, 3 VMIN Absolute Min. Output Voltage; NOTE 2, 4 -300 VRB Ringback Voltage; NOTE 5, 6 -100 100 mV VCROSS Absolute Crossing Voltage; NOTE 2, 7, 8 200 550 mV ∆VCROSS Total Variation of VCROSS over all edges; NOTE 2, 7, 9 140 mV tR / tF Output Rise/Fall Time 0.6 4.75 V/ns odc Output Duty Cycle; NOTE 10 48 52 % PLL Mode measured between -150mV to +150mV mV NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at f ≤ 250MHz unless noted otherwise. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Measurement taken from single ended waveform. NOTE 3: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 4: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 5: Measurement taken from differential waveform. NOTE 6:TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. NOTE 7: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ. NOTE 8: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. NOTE 9: Defined as the total variation of all crossing voltages of rising Q and falling nQ, This is the maximum allowed variance in Vcross for any particular system. NOTE 10: Input duty cycle must be 50%. ICS871002AGI-02 REVISION A APRIL 14, 2010 5 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information 3.3V±10% 3.3V±10% 3.3V±10% 3.3V±10% SCOPE VDD 50Ω 33Ω VDD Measurement Point VDDA VDDA 49.9Ω IREF HCSL 2pF HCSL 50Ω 33Ω 50Ω 50Ω Measurement Point IREF GND 475Ω GND 49.9Ω 2pF 475Ω 0V 0V This load condition is used for IDD and tjit(cc) measurements. 3.3V HCSL Output Load AC Test Circuit 3.3V HCSL Output Load AC Test Circuit VDD nQ[0:1], nFB_OUT nCLK, nFB_IN Q[0:1], ➤ V Cross Points PP CMR CLK, FB_IN tcycle n ➤ V FB_OUT ➤ tcycle n+1 ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles GND Differential Input Level Cycle-to-Cycle Jitter TSTABLE Clock Period (Differential) Positive Duty Cycle (Differential) VRB Negative Duty Cycle (Differential) +150mV VRB = +100mV 0.0V VRB = -100mV -150mV 0.0V Q - nQ VRB Q - nQ TSTABLE Differential Measurement Points for Duty Cycle/Period ICS871002AGI-02 REVISION A APRIL 14, 2010 Differential Measurement Points for Ringback 6 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information, continued VMAX = 1.15V nQ nQ VCROSS_MAX = 550mV VCROSS_DELTA = 140mV VCROSS_MIN = 250mV Q VMIN = -0.30V Q Single-ended Measurement Points for Absolute Cross Point and Swing Rise Edge Rate Single-ended Measurement Points for Delta Cross Point Fall Edge Rate +150mV 0.0V -150mV Q - nQ Output Rise/Fall Time ICS871002AGI-02 REVISION A APRIL 14, 2010 7 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS871002I-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS871002AGI-02 REVISION A APRIL 14, 2010 8 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. The differential signal must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK Differential Input HSTL R1 50Ω IDT HSTL Driver Differential Input LVPECL R2 50Ω R2 50Ω R1 50Ω R2 50Ω 3A. CLK/nCLK Input Driven by an IDT Open Emitter HSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125Ω 3.3V R4 125Ω 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100 Zo = 50Ω nCLK R1 84Ω R2 84Ω nCLK Zo = 50Ω Differential Input LVPECL Receiver LVDS Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 2.5V 3.3V 3.3V 2.5V *R3 33Ω R3 120Ω Zo = 50Ω R4 120Ω Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input SSTL R1 120Ω R2 120Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS871002AGI-02 REVISION A APRIL 14, 2010 9 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins Differential Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Recommended Termination Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. Figure 4A. Recommended Termination Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. Figure 4B. Recommended Termination ICS871002AGI-02 REVISION A APRIL 14, 2010 10 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Schematic Layout Figure 5 shows an example of ICS871002I-02 application schematic. In this example, the device is operated at VDD= 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. Two examples of HCSL termination are shown in this schematic. Logic Control Input Examples Set Logic Input to '1' VDD Set Logic Input to '0' VDD RU1 1K RU2 Not Install To Logic Input pins RD1 Not Install RD2 1K To Logic Input pins VDD=3.3V R1 Q0 33 Zo = 50 R2 nQ0 33 Zo = 50 + - FB_IN R3 475 nFB_IN R7 50 VDD R6 R8 50 VDDA 10 VDD FB_IN nFB_IN MR BW_SEL F_SEL1 F_SEL0 C2 10u C3 0.1u R4 50 U1 VDD 1 2 3 4 5 6 7 8 9 10 nQ0 IREF FB_OUT nFB_OUT MR BW_SEL F_SEL1 VDDA F_SEL0 VDD Q0 VDD Q1 nQ1 nFB_IN FB_IN GND nCLK CLK OE 20 19 18 17 16 15 14 13 12 11 R5 50 C1 .1uf Recommended for PCI Express Add-In Card FB_IN nFB_IN OE HCSL Termination C4 .1uf Zo = 50 Ohm CLK Zo = 50 Ohm LVPECL Driv er Zo = 50 nQ1 Zo = 50 + - R9 50 nCLK R11 50 Q1 R10 50 Recommended for PCI Express Point-to-Point Connection R12 50 R13 50 Figure 5. ICS871002I-02 Schematic Layout ICS871002AGI-02 REVISION A APRIL 14, 2010 11 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS871002I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS71002I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.63V * (75mA + 12mA) = 315.81mW • Power (outputs)MAX = 46.8mW/Loaded Output Pair If all outputs are loaded, the total power is 3 * 46.8mW = 140.4mW Total Power_MAX (3.63V, with all outputs switching) = 315.81mW + 140.4mW = 456.21mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.456W * 86.7°C/W = 124.6°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS871002AGI-02 REVISION A APRIL 14, 2010 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W 12 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6. VDD IOUT = 17mA ➤ VOUT RREF = 475Ω ± 1% RL 50Ω IC Figure 6. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX – VOUT) * IOUT, since VOUT – IOUT * RL = (VDD_MAX – IOUT * RL) * IOUT = (3.6V – 17mA * 50Ω) * 17mA Total Power Dissipation per output pair = 46.8mW ICS871002AGI-02 REVISION A APRIL 14, 2010 13 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W Transistor Count The transistor count for ICS871002I-02 is: 1,704 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8 Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS871002AGI-02 REVISION A APRIL 14, 2010 14 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Ordering Information Table 9. Ordering Information Part/Order Number 871002AGI-02 871002AGI-02T 871002AGI-02LF 871002AGI-02LFT Marking ICS71002AI02 ICS71002AI02 ICS1002AI02L ICS1002AI02L Package 20 Lead TSSOP 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS871002AGI-02 REVISION A APRIL 14, 2010 15 ©2010 Integrated Device Technology, Inc. ICS871002I-02 Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 PCI EXPRESS™ JITTER ATTENUATOR Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.