a FEATURES +5 V Single-Supply Operation 7 ns Propagation Delay Low Power Separate Input and Output Sections TTL and CMOS Logic Compatible Outputs Wide Output Swing TSSOP, SOIC and PDIP Packages APPLICATIONS High Speed Timing Line Receivers Data Communications High Speed V-to-F Converters Battery Operated Instrumentation High Speed Sampling Systems Window Comparators Read Channel Detection PCMCIA Cards Upgrade for MAX901 Designs GENERAL DESCRIPTION The AD8564 is quad 7 ns comparator with separate input and output supplies, thus enabling the input stage to be operated from ± 5 V dual supplies or a +5 V single supply while maintaining a CMOS/TTL-compatible output. Quad 7 ns Single Supply Comparator AD8564 PIN CONFIGURATIONS 16-Lead Epoxy DIP (P Suffix) N-16 16-Lead Narrow Body SO (S Suffix) R-16A –IN D +IN D V+ANA OUT D OUT C V+DIG +IN C –IN C –IN A +IN A GND OUT A OUT B V–ANA +IN B –IN B –IN A 1 16 –IN D +IN A 2 15 +IN D + – – + 14 V+ANA GND 3 OUT A 4 OUT B 5 AD8564 V–ANA 6 AD8564 + – – + 13 OUT D 12 OUT C 11 V+DIG +IN B 7 10 +IN C –IN B 8 9 –IN C 16-Lead TSSOP (RU-Suffix) RU-16 –IN A +IN A GND OUT A OUT B V–ANA +IN B –IN B 1 16 AD8564 8 9 –IN D +IN D V+ANA OUT D OUT C V+DIG +IN C –IN C Fast 7 ns propagation delay makes the AD8564 a good choice for timing circuits and line receivers. Independent analog and digital supplies provide excellent protection from supply pin interaction. The AD8564 is pin compatible with the MAX901, and has lower supply currents. All four comparators have similar propagation delays. The propagation delay for rising and falling signals is similar, and tracks over temperature and voltage. These characteristics make the AD8564 a good choice for high speed timing and data communications circuits. For a similar dual comparator with a latch function, please see the AD8598 data sheet. For a similar single comparator with latch function, please see the AD8561 data sheet. The AD8564 is specified over the industrial (–40°C to +85°C) temperature range. The quad AD8564 is available in the 16lead plastic DIP, narrow SO-16 surface mount, and 16-lead TSSOP packages. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD8564–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V +ANA Parameter Symbol INPUT CHARACTERISTICS Offset Voltage VOS Offset Voltage Drift Input Bias Current Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance ∆VOS/∆T IB IB IOS VCM CMRR AVO CIN = V+DIG = +5.0 V, V–ANA = 0 V, TA = +25ⴗC unless otherwise noted) Conditions Min Typ Max Units 2.3 7 8 mV mV µV/°C µA µA µA V dB V/V pF –40°C ≤ TA ≤ +85°C 4 ±4 ±9 ±3 +2.75 VCM = 0 V –40°C ≤ TA ≤ +85°C VCM = 0 V 0 V ≤ VCM ≤ +3.0 V RL = 10 kΩ 0 65 85 3000 3.0 DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage VOH VOL IOH = –3.2 mA, ∆VIN > 250 mV IOL = 3.2 mA, ∆VIN > 250 mV DYNAMIC PERFORMANCE Propagation Delay tP 200 mV Step with 100 mV Overdrive –40°C ≤ TA ≤ +85°C1 100 mV Step with 5 mV Overdrive1 8 ∆tP 100 mV Step with 20 mV Overdrive1 20% to 80% 20% to 80% 0.5 3.8 1.5 PSRR I+ANA +4.5 V ≤ V+ANA and V+DIG ≤ +5.5 V 80 10.5 Propagation Delay Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Rise Time Fall Time POWER SUPPLY Power Supply Rejection Ratio Analog Supply Current tP Digital Supply Current IDIG Analog Supply Current I–ANA 2.4 3.5 0.3 6.75 –40°C ≤ TA ≤ +85°C VO = 0 V, RL = ∞ –40°C ≤ TA ≤ +85°C 6.0 –7.0 –40°C ≤ TA ≤ +85°C 0.4 V V 9.8 13 ns ns ns 2.0 ns ns ns 14.0 15.6 7.0 8.0 14.0 15.6 dB mA mA mA mA mA mA NOTES 1 Guaranteed by design. Specifications subject to change without notice. ELECTRICAL SPECIFICATIONS (@ V +ANA Parameter Symbol INPUT CHARACTERISTICS Offset Voltage VOS Offset Voltage Drift Input Bias Current Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage ∆VOS/∆T IB IB IOS VCM CMRR AVO CIN VOH VOL = V+DIG = +5.0 V, V–ANA = –5 V, TA = +25ⴗC unless otherwise noted) Conditions Min Typ Max Units 2.3 7 8 mV mV µV/°C µA µA µA V dB V/V pF –40°C ≤ TA ≤ +85°C 4 ±4 ±9 ±3 +3.5 VCM = 0 V –40°C ≤ TA ≤ +85°C VCM = 0 V 0 V ≤ VCM ≤ +3.0 V RL = 10 kΩ IOH = –3.2 mA, ∆VIN > 250 mV IOL = 3.2 mA, ∆VIN > 250 mV –2– –4.9 65 2.6 85 3000 3.0 3.6 0.2 0.3 V V REV. A AD8564 Parameter Symbol Conditions DYNAMIC PERFORMANCE Propagation Delay tP Propagation Delay Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Rise Time Fall Time POWER SUPPLY Power Supply Rejection Ratio Analog Supply Current Typ Max Units 200 mV Step with 100 mV Overdrive –40°C ≤ TA ≤ +85°C1 100 mV Step with 5 mV Overdrive1 6.75 8 8 9.8 13 ns ns ns ∆tP 100 mV Step with 20 mV Overdrive1 20% to 80% 20% to 80% 0.5 3 3 2.0 ns ns ns PSRR I+ANA +4.5 V ≤ V+ANA and V+DIG ≤ +5.5 V tP Digital Supply Current IDIG Analog Supply Current I–ANA Min 50 70 10.8 –40°C ≤ TA ≤ +85°C VO = 0 V, RL = ∞ –40°C ≤ TA ≤ +85°C 3.6 –8.2 –40°C ≤ TA ≤ +85°C 14.0 15.6 4.4 5.6 14.0 15.6 dB mA mA mA mA mA mA NOTES 1 Guaranteed by design. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Total Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . +14 V Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V Analog Positive Supply–Digital Positive Supply . . . . . –600 mV Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ± 8 V Output Short-Circuit Duration to GND . . . . . . . . . Indefinite Storage Temperature Range N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Junction Temperature Range N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300°C Package Type JA2 JC Units 16-Lead Plastic DIP (N) 16-Lead Narrow Body SO (R) 16-Lead TSSOP (RU) 90 113 180 47 37 37 °C/W °C/W °C/W NOTES 1 The analog input voltage is equal to ± 7 V or the analog supply voltage, whichever is less. 2 θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket for, P-DIP, and θJA is specified for device soldered in circuit board for SOIC and TSSOP packages. ORDERING GUIDE Model Temperature Range Package Description Package Options AD8564AN AD8564AR AD8564ARU –40°C to +85°C –40°C to +85°C –40°C to +85°C 16-Lead Plastic DIP 16-Lead Narrow Body SOIC 16-Lead Thin Shrink Small Outline (TSSOP) N-16 R-16A RU-16 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8564 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE AD8564 –Typical Performance Characteristics 0 0.000 0.800 0.600 0.400 0.200 INPUT BIAS CURRENT – A V+ANA = V+DIG = +5V V–ANA = –5V INPUT BIAS CURRENT – A INPUT OFFSET VOLTAGE – mV 1.000 (V+ ANA = V+DIG = +5 V, V– ANA = 0 V, TA = +25ⴗC unless otherwise noted) –1.000 –2.000 –3.000 –4.000 Figure 1. Input Offset Voltage vs. Temperature Figure 2. Input Bias Current vs. Temperature 500 –2 –3 –4 –5 –7.5 –5.000 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – ⴗC 0.000 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – ⴗC –1 –2.5 0 2.5 –5 INPUT COMMON-MODE VOLTAGE – V 5 Figure 3. Input Bias Current vs. Input Common-Mode Voltage 10 5.000 400 300 200 100 0 –5 –4 –3 –2 –1 0 1 2 3 4 INPUT OFFSET VOLTAGE – mV Figure 4. Input Offset Voltage 6 tPDLH 4 2 –25 0 25 50 75 TEMPERATURE – ⴗC 100 TA = –40ⴗC TA = +25ⴗC 0.300 TA = +85ⴗC 0.200 0.100 0 3 6 9 12 SINK CURRENT – mA 15 Figure 7. Output Low Voltage, VOL vs. Sink Current 3.800 TA = +25ⴗC 3.200 TA = –40ⴗC 2.600 0 3 6 9 12 SOURCE CURRENT – mA 15 0.000 4.000 TA = +85ⴗC 3.000 TA = +25ⴗC 2.000 TA = –40ⴗC 1.000 0.000 TA = +85ⴗC Figure 6. Output High Voltage, VOH vs. Source Current I–ANA, SUPPLY CURRENT – mA 0.400 4.400 2.000 125 5.000 I+ANA, SUPPLY CURRENT – mA OUTPUT LOW VOLTAGE – V tPDHL Figure 5. Propagation Delay, tPDHL/ tPDLH vs. Temperature 0.500 0.00 8 0 –50 5 OUTPUT HIGH VOLTAGE – V PROPAGATION DELAY – ns NUMBER OF AMPLIFIERS STEPSIZE = 100mV OVERDRIVE = 5mV 2 6 8 10 4 V+ANA SUPPLY VOLTAGE – V 12 Figure 8. I+ANA: Analog Supply Current/Comparator vs. Supply Voltage –4– TA = –40ⴗC –1.000 TA = +25ⴗC –2.000 TA = +85ⴗC –3.000 –4.000 –5.000 2 4 6 8 10 V–ANA SUPPLY VOLTAGE – V 12 Figure 9. I–ANA: Analog Supply Current/Comparator vs. Supply Voltage REV. A AD8564 2.000 TA = +85ⴗC TA = +25ⴗC 1.500 1.000 TA = –40ⴗC 0.500 2 4 6 8 10 V+DIG SUPPLY VOLTAGE – V 4.000 V+ANA = ⴞ5V 3.000 V+ANA = +5V 2.000 1.000 0 –75 –50 –25 12 Figure 10. I+DIG: Digital Supply Current/Comparator vs. Supply Voltage 0 25 50 75 100 125 150 TEMPERATURE – ⴗC Figure 11. I+ANA : Analog Supply Current/Comparator vs. Temperature I–ANA, SUPPLY CURRENT – mA 2.500 0.000 0.000 5.000 I+ANA, SUPPLY CURRENT – mA I+DIG, SUPPLY CURRENT – mA 3.000 –1.000 V+ANA = +5V –2.000 –3.000 V+ANA = ⴞ5V –4.000 –5.000 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – ⴗC Figure 12. I–ANA: Analog Supply Current/Comparator vs. Temperature I+DIG, SUPPLY CURRENT – mA 2.000 1.500 1.000 0.500 0.000 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – ⴗC Figure 13. I+DIG: Digital Supply Current/ Comparator vs. Temperature APPLICATIONS power supply pins to ground. These capacitors act as a charge reservoir for the device during high frequency switching. OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator or amplifier, proper design and layout techniques should be used to ensure optimal performance from the AD8564. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance or other layout issues. A ground plane is recommended for proper high speed performance. This can be created by using a continuous conductive plane over the surface of the circuit board, only allowing breaks in the plane for necessary current paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused from “ground bounce.” A proper ground plane also minimizes the effects of stray capacitance on the circuit board. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the AD8564. Source resistance in combination with equivalent input capacitance could cause a lagged response at the input, thus delaying the output. The input capacitance of the AD8564 in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF of input capacitance yields a time constant of 15 ns, which is slower than the 5 ns capability of the AD8564. Source impedances should be less than 1 kΩ for the best performance. OUTPUT LOADING CONSIDERATIONS It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 µF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors will reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible from the To ensure the best performance from the AD8564 it is important to minimize capacitive loading of the output of the device. Capacitive loads greater than 50 pF will cause ringing on the output waveform and will reduce the operating bandwidth of the comparator. Propagation delay will also increase with capacitive loads above 100 pF. REV. A The AD8564 output can deliver up to 40 mA of output current without any significant increase in propagation delay. The output of the device should not be connected to more than twenty (20) TTL input logic gates, or drive a load resistance less than 100 Ω. –5– AD8564 INPUT STAGE AND BIAS CURRENTS The input signal is connected directly to the inverting input of the comparator. The output is fed back to the noninverting input through R2 and R1. The ratio of R1 to R1 + R2 establishes the width of the hysteresis window with VREF setting the center of the window, or the average switching voltage. The output will switch high when the input voltage is greater than VHI and will not switch low again until the input voltage is less than VLO as given in Equation 1: The AD8564 uses a PNP differential input stage which enables the input common-mode range to extend all the way from the negative supply rail to within 2.2 V of the positive supply rail. The input common-mode voltage can be found as the average of the voltage at the two inputs of the device. To ensure the fastest response time, care should be taken to not allow the input common-mode voltage to exceed this voltage. The input bias current for the AD8564 is 4 µA. As with any PNP differential input stage, this bias current will go to zero on an input that is high and will double on an input that is low. Care should be taken in choosing resistor values to be connected to the inputs as large resistors could cause significant voltage drops due to the input bias current. ( V HI = V + –1–V REF ) R1+R1R2 +V REF R1 V LO =V REF 1– R1+ R2 The input capacitance for the AD8564 is typically 3 pF. This is measured by inserting a kΩ source resistance to the input and measuring the change in propagation delay. (1) Where V+ is the positive supply voltage. The capacitor CF can also be added to introduce a pole into the feedback network. This has the effect of increasing the amount of hysteresis at high frequencies. This can be useful when comparing a relatively slow signal in a high frequency noise environ- USING HYSTERESIS Hysteresis can easily be added to a comparator through the addition of positive feedback. Adding hysteresis to a comparator offers an advantage in noisy environments where it is not desirable for the output to toggle between states when the input signal is near the switching threshold. Figure 14 shows a method for configuring the AD8564 with hysteresis. 1 , the hysteresis 2π CF R2 window approaches VHI = V+ – 1 V and VLO = 0 V. At frequencies less than fP the threshold voltages remain as in Equation 1. ment. At frequencies greater than fP = COMPARATOR SIGNAL R1 R2 VREF CF Figure 14. Configuring the AD8564 with Hysteresis –6– REV. A AD8564 Spice Model * AD8564 SPICE Macro-Model Typical Values * 8/98, Ver. 1.0 * TAM / ADSC * * Node assignments * noninverting input * | inverting input * | | positive supply * | | | * | | | * | | | * | | | * | | | * | | | .SUBCKT AD8564 1 2 99 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1k RC2 6 50 1k CL1 4 6 2.5E-12 CIN 1 2 3E-12 EOS 3 1 (4,6) 1E-3 * * Reference Voltage * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RDUM 98 0 100E3 GSY 99 50 POLY(1) (99,50) 8E-3 –2.6E-3 * * Gain Stage Av=250 fp=100MHz * G1 98 20 (4.6) 0.25 R1 20 98 1E3 C1 20 98 16E-13 D1 20 21 DX D2 22 20 DX V1 99 21 DC 0.71 V2 22 50 DC 0.71 * * Output Stage * Q3 99 41 46 NOX Q4 47 42 50 NOX RB1 43 41 200 RB2 40 42 200 CB1 99 41 10p CB2 42 50 5p RO1 46 45 2E3 RO2 47 45 500 EO1 98 43 POLY(1) (20,98) 0 1 EO2 40 98 POLY(1) (20,98) 0 1 * * MODELS * .MODEL PIX PNP(BF=100,VAF=130,IS=1E-14) .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14) .MODEL DX D(IS=1E-14,CJO=1E-15) negative supply | | | | | 50 .ENDS AD8564 REV. A –7– Output | | | | 45 AD8564 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Epoxy DIP (N-16) C3219a–2–6/99 16-Lead Narrow Body SOIC (R-16A) 0.3937 (10.00) 0.3859 (9.80) 0.1574 (4.00) 0.1497 (3.80) 16 9 1 8 PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0500 SEATING (1.27) PLANE BSC 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 0.0196 (0.50) ⴛ 45ⴗ 0.0099 (0.25) 8ⴗ 0ⴗ 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. 16-Lead Thin Shrink Small Outline (TSSOP) (RU-16) –8– REV. A