a GSM Power Management System ADP3401 FEATURES Handles all GSM Baseband Power Management Functions Four LDOs Optimized for Specific GSM Subsystems Charges Li-Mn Coin Cell for Real-Time Clock Charge Pump and Logic Level Translators for 3 V and 5 V GSM SIM Modules Thermally Enhanced 6.1 mm 28-Lead TSSOP Package APPLICATIONS GSM/DCS/PCS Handsets TeleMatic Systems ICO/Iridium Terminals FUNCTIONAL BLOCK DIAGRAM VBAT ADP3401 DIGITAL LDO VCC RESET PWRONKEY ROWX PWRONIN RTC LDO POWER-UP SEQUENCING AND PROTECTION LOGIC XTAL OSC LDO VRTC VTCXO ANALOGON RESCAP GENERAL DESCRIPTION The ADP3401 is a multifunction power management system IC optimized for GSM cell phones. The wide input voltage range of 3.0 V to 7.0 V makes the ADP3401 ideal for both single cell Li-Ion and three cell NiMH designs. The current consumption of the ADP3401 has been optimized for maximum battery life, featuring a ground current of only 150 µA when the phone is in standby (digital LDO, and SIM card supply active). An undervoltage lockout (UVLO) prevents the startup when there is not enough energy in the battery. All four integrated LDOs are optimized to power one of the critical sub-blocks of the phone. Their novel anyCAP™ architecture requires only very small output capacitors for stability, and the LDOs are insensitive to the capacitors’ equivalent series resistance (ESR). This makes them stable with any capacitor, including ceramic (MLCC) types for space-restricted applications. ANALOG LDO CHRON VCCA SIMBAT CAP+ CAP2 SIMPROG CHARGE PUMP VSIM SIMON BUFFER REF SIMGND REFOUT + RESETIN CLKIN DGND LOGIC LEVEL TRANSLATION AGND DATAIO I/O CLK RST A step-up converter is implemented to supply both the SIM module and the level translation circuitry to adapt logic signals for 3 V and 5 V SIM modules. Sophisticated controls are available for power-up during battery charging, keypad interface, and charging of an auxiliary backup battery for the real-time clock. These allow an easy interface between ADP3401, GSM processor, charger, and keypad. The 28-lead TSSOP package has been thermally enhanced to maximize power dissipation capability. Furthermore, a reset circuit and a thermal shutdown function have been implemented to support reliable system design. anyCAP is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 ADP3401–SPECIFICATIONS (–20 °C ≤ TA ≤ +85°C, VBAT = 3 V to 7 V, CVBAT = CSIMBAT = CVSIM = 10 F, CVCC = C VCCA = 2.2 F, C VRTC = 0.1 F, CVTCXO = 0.22 F, C VCAP = 0.1 F, min. loads applied on all outputs, unless otherwise noted) ELECTRICAL CHARACTERISTICS1 Parameter Symbol SHUTDOWN SUPPLY CURRENT VBAT = Low (UVLO Low) VBAT = High (UVLO High) IBAT OPERATING GROUND CURRENT VCC and VRTC On VCC, VRTC and VSIM On All LDOs and VSIM On All LDOs and VSIM On IGND UVLO CHARACTERISTICS UVLO On Threshold UVLO Hysteresis INPUT CHARACTERISTICS Input High Voltage PWRONIN and ANALOGON PWRONKEY Input Low Voltage PWRONIN and ANALOGON PWRONKEY Conditions Typ Max Unit VBAT = 2.7 V VBAT = 3.6 V, VRTC On 3 12 20 30 µA µA Minimum Loads, VBAT = 3.6 V Minimum Loads, VBAT = 3.6 V Minimum Loads, VBAT = 3.6 V Maximum Loads, VBAT = 3.6 V 100 150 260 15 140 240 400 µA µA µA mA 3.0 100 3.3 V mV VBATUVLO VIH 2 0.7 ⫻ VBAT 0.4 V 0.3 ⫻ VBAT V CHRON CHARACTERISTICS CHRON Threshold CHRON Hysteresis Resistance CHRON Input Bias Current VT RIN IB ROWX CHARACTERISTICS ROWX Output Low Voltage VOL IIH SHUTDOWN Thermal Shutdown Threshold2 Thermal Shutdown Hysteresis DIGITAL LDO (VCC) Output Voltage Line Regulation Load Regulation Output Capacitor3 Dropout Voltage ANALOG LDO (VCCA) Output Voltage Line Regulation Load Regulation 2.38 < CHRON < VT CHRON > VT 15 20 25 kΩ 2.38 108 2.48 125 2.58 138 0.5 V kΩ µA 0.4 V 1 µA PWRONKEY = Low IOL = 200 µA PWRONKEY = High V(ROWX) = 5 V Junction Temperature Junction Temperature VCC DVCC DVCC CO VDO VCCA DVCCA DVCCA Output Capacitor3 Dropout Voltage CO VDO Ripple Rejection DVBAT/ DVCCA VNOISE Output Noise Voltage V V VIL PWRONKEY INPUT PULL-UP RESISTANCE TO VBAT ROWX Output High Leakage Current Min Line, Load, Temp 3 V < VBAT < 7 V, Min Load 50 µA < ILOAD < 100 mA, VBAT = 3.6 V 2.710 160 35 ºC ºC 2.765 2.820 2 15 V mV mV 2.2 VO = VINITIAL – 100 mV ILOAD = 100 mA Line, Load, Temp 3 V < VBAT < 7 V, Min Load 200 µA < ILOAD < 130 mA, VBAT = 3.6 V 215 2.710 2.765 2.820 2 15 2.2 VO = VINITIAL – 100 mV ILOAD = 130 mA f = 217 Hz (t = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 130 mA, VBAT = 3.6 V –2– 215 65 µF mV V mV mV µF mV 70 dB 75 µV rms REV. 0 ADP3401 Parameter Symbol Conditions Min Typ Max Unit CRYSTAL OSCILLATOR LDO (VTCXO) Output Voltage Line Regulation Load Regulation VTCXO ∆VTCXO ∆VTCXO Line, Load, Temp 3 V < VBAT < 7 V, Min Load 100 µA < ILOAD < 5 mA, VBAT = 3.6V 2.710 2.765 2 1 2.820 V mV mV Output Capacitor3 Dropout Voltage CO VDO Ripple Rejection ∆VBAT/ ∆VTCXO VNOISE VO = VINITIAL – 100 mV ILOAD = 5 mA f = 217 Hz (t = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 5 mA, VBAT = 3.6 V VREFOUT ∆VREFOUT Line, Load, Temp 3 V < VBAT < 7 V, Min Load Load Regulation ∆VREFOUT Ripple Rejection ∆VBAT/ ∆VREFOUT CO VNOISE 0 µA < ILOAD < 50 µA, VBAT = 3.6 V f = 217 Hz (t = 4.6 ms), VBAT = 3.6 V Output Noise Voltage VOLTAGE REFERENCE (REFOUT) Output Voltage Line Regulation Maximum Capacitive Load Output Noise Voltage 0.22 150 65 1.192 65 REAL-TIME CLOCK LDO/ BATTERY CHARGER (VRTC) Maximum Output Voltage Current Limit Off Reverse Leakage Current Dropout Voltage VRTC IMAX IL VDO ILOAD ≤ 10 µA 3.050 V < VBAT < 7 V 2.0 V < VBAT < UVLO VO = VINITIAL – 10 mV ILOAD = 10 µA 2.810 SIM CHARGE PUMP (VSIM) Output Voltage for 5 V SIM Modules VSIM 4.70 Output Voltage for 3 V SIM Modules VSIM 0 mA ≤ ILOAD ≤ 10 mA SIMPROG = High 0 mA ≤ ILOAD ≤ 6 mA SIMPROG = Low 2.82 GSM/SIM LOGIC TRANSLATION (GSM INTERFACE) Input High Voltage (SIMPROG, SIMON, RESETIN, CLKIN) Input Low Voltage (SIMPROG, SIMON, RESETIN, CLKIN) DATAIO DATAIO Pull-Up Resistance to VCC REV. 0 72 dB 80 µV rms 1.210 2 VIH mV 75 dB 40 pF µV rms 2.850 175 VIH, V OH IIL VOL RIN 2.890 1 170 V µA µA mV 5.00 5.30 V 3.00 3.18 V VCC – 0.6 VOL (I/O) = 0.4 V, IOL (I/O) = 1 mA VOL (I/O) = 0.4 V, IOL (I/O ) = 0 mA IIH, IOH = ± 10 µA VIL = 0 V VIL (I/O) = 0.4 V V –3– 0.6 V 0.230 V 0.335 V –0.9 0.420 24 V mA V kΩ VCC – 0.4 16 V mV 0.5 VIL VIL 1.228 100 f = 10 Hz to 100 kHz VBAT = 3.6 V µF mV 20 ADP3401 Parameter Symbol Conditions Min SIM INTERFACE VSIM = 5 V RST RST CLK CLK I/O I/O I/O I/O VOL VOH VOL VOH VIL VIH, V OH IIL VOL I = +200 µA I = –20 µA I = +200 µA I = –20 µA VSIM – 0.7 VSIM = 3 V RST RST CLK CLK I/O I/O I/O I/O VOL VOH VOL VOH VIL VIH, V OH IIL VOL I = +200 µA I = –20 µA I = +20 µA I = –20 µA I/O Pull-Up Resistance to VSIM Max Frequency (CLK) Prop Delay (CLK) Output Rise/Fall Times (CLK) Output Rise/Fall Times (I/O, RST) Duty Cycle (CLK) RIN fMAX tD tR, tF tR, tF D RESET GENERATOR (RESET) Output High Voltage Output Low Voltage Delay Time Per Unit Capacitance Applied to RESCAP Pin VOH VOL tD IIH, I OH = ± 20 µA VIL = 0 V IOL = +1 mA DATAIO ≤ 0.23 V IIH, I OH = ± 20 µA VIL= 0 V IOL = 1 mA DATAIO ≤ 0.23 V CL = 30 pF CL = 30 pF CL = 30 pF D CLKIN = 50% f = 5 MHz IOH = –15 µA IOL = –15 µA Typ Max Unit 0.6 V V V V V V mA V 0.5 0.7 ⫻ VSIM 0.4 VSIM – 0.4 –0.9 0.4 0.2 ⫻ VSIM 0.8 ⫻ VSIM 0.2 ⫻ VSIM 0.7 ⫻ VSIM 0.4 VSIM – 0.4 –0.9 0.4 8 5 47 10 12 30 9 50 18 1 53 VCC – 0.3 0.3 1.0 V V V V V V mA V kΩ MHz ns ns µs % V V ms/nF NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods . 2This feature is intended to protect against catastophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC could cause permenant damage to the device. 3Required for stability. Specifications subject to change without notice. –4– REV. 0 ADP3401 PIN FUNCTION DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Respect to Any GND Pin . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +10 V Voltage on Any Pin May Not Exceed VBAT, with the Following Exceptions: VRTC, VSIM, CAP+, PWRONIN, I/O, CLK, RST Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . –20°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C θJA, Thermal Impedance (TSSOP-28) . . 2-Layer Board 90°C/W θJA, Thermal Impedance (TSSOP-28) . . 4-Layer Board 60°C/W Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C *This is a stress rating only, operation beyond these limits can cause the device to be permanently damaged. PIN CONFIGURATION VBAT 1 28 AGND VCC 2 27 VCCA 3 26 REFOUT ANALOGON 4 25 RESET PWRONIN 5 24 VTCXO ROWX 6 23 DGND CHRON 7 22 RESCAP PWRONKEY VRTC 8 ADP3401 21 CAP+ CAP2 9 20 VSIM SIMBAT 10 19 CLK DATAIO 11 18 SIMON RESETIN 12 17 SIMPROG CLKIN 13 16 RST SIMGND 14 15 I/O ORDERING GUIDE Model Temperature Range Package Description ADP3401ARU –20°C to +85°C 28-Lead TSSOP Package Option Pin Mnemonic Function 1 2 3 4 5 VBAT VCC PWRONKEY ANALOGON PWRONIN 6 7 8 ROWX CHRON VRTC 9 10 CAP– SIMBAT 11 DATAIO 12 13 14 15 RESETIN CLKIN SIMGND I/O 16 17 RST SIMPROG 18 19 20 21 22 23 24 SIMON CLK VSIM CAP+ RESCAP DGND VTCXO 25 26 27 28 RESET REFOUT VCCA AGND Battery Input Voltage Digital Low Dropout Regulator Power On/Off Key VTCXO Enable Power On/Off Signal from Microprocessor Microprocessor Keyboard Output Charger On/Off Input Real-Time Clock Supply/Coin Cell Battery Charger Negative Side of Boost Capacitor Battery Input for the SIM Charge Pump Non-Level-Shifted Bidirectional Data I/O Non-Level-Shifted SIM Reset Non-Level-Shifted Clock Charge Pump Ground Level-Shifted Bidirectional SIM Data Input/Output Level-Shifted SIM Reset VSIM Programming: Low = 3 V, High = 5 V VSIM Enable Level-Shifted SIM Clock SIM Supply Positive Side of Boost Capacitor Reset Delay Timing Cap Digital Ground Crystal Oscillator Low Dropout Regulator Main Reset Reference Output Analog Low Dropout Regulator Analog Ground RU-28A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3401 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– WARNING! ESD SENSITIVE DEVICE ADP3401 Table I. LDO Control Logic INPUTS OUTPUTS UVLO CHRON PWRONKEY PWRONIN ANALOGON VRTC VCC VCCA REFOUT VTCXO L X X X X Off Off Off Off Off H H X X X On On On On On H X L X X On On On On On H L H L X On Off Off Off Off H L H H L On On Off Off Off H L H H H On On On On On X = Don't care Bold denotes the active control signal. Table II. VSIM Control Logic INPUTS OUTPUTS VCC RESET SIMON SIMPROG VSIM Off On On On On L L H H H X X L H H X X X L H Off Off Off 3V 5V X = Don't care VBAT ADP3401 DIGITAL LDO VBAT OUT VREF 20kV ADJ UVLO EN GND VCC 2.765V PG UVLO OVER TEMP ROWX RTC LDO OUT VBAT EN PWRONIN RESCAP CHRON DGND POWER GOOD PWRONKEY RESET GENERATOR VRTC 2.85V GND RESET XTAL OSC LDO VBAT CHARGER ON THRESHOLD VREF EN OUT VTCXO 2.765V GND ANALOGON SIMBAT ANALOG LDO CAP+ EN CHARGE PUMP CAP2 SIMPROG SIMON VBAT VREF 3V/5V EN OUT VCCA 2.765V GND EN SIMGND RESETIN CLKIN EN REF BUFFER LOGIC LEVEL TRANSLATION DATAIO REFOUT + 1.210V I/O CLK RST AGND VSIM Figure 1. Functional Block Diagram –6– REV. 0 ADP3401 300 350 250 250 200 IRTC – mA IGND – mA PWRONIN, SIMON, AND ANALOGON 300 PWRONIN AND SIMON 200 150 +858C 150 100 +258C PWRONIN 50 2208C 50 100 3 4 5 VBAT – V 0 7 6 0 Figure 2. Ground Current vs. Battery Voltage 0.5 1.0 1.5 VRTC – V 2.0 2.5 3 Figure 5. RTC I/V Characteristic 140 MLCC CAPS 3.2 100 VCC 3.0 VCCA 80 VOLTAGE DROPOUT VOLTAGE – mV 120 VBAT 100 mV/DIV 60 VCC 10 mV/DIV VCCA 10 mV/DIV 40 VTCXO 10 mV/DIV 20 0 0 20 40 60 80 100 LOAD CURRENT – mA 120 140 TIME – 100ms/DIV Figure 3. VCC, VCCA Dropout Voltage vs. Load Current Figure 6. Line Transient Response, Maximum Loads 70 MLCC CAPS 60 VBAT (100 mV/DIV) 50 VOLTAGE DROPOUT VOLTAGE – mV 3.2 40 30 3.0 VCC (10 mV/DIV) VCCA (10 mV/DIV) 20 VTCXO (10 mV/DIV) 10 0 0 1 2 3 LOAD CURRENT – mA 4 5 TIME – 100ms/DIV Figure 4. VTCXO Dropout Voltage vs. Load Current REV. 0 Figure 7. Line Transient Response, Minimum Loads –7– ADP3401 MLCC CAPS ILOAD I = 100mA PWRONIN AND ANALOGON (2V/DIV) VCC VCCA (100mV/DIV) VOLTAGE VOLTAGE – 20mV/DIV I = 200mA REFOUT (100mV/DIV) VCC (100mV/DIV) VTCXO (100mV/DIV) TIME – 200ms/DIV TIME – 50ms/DIV Figure 8. VCC Load Step Figure 11. Turn-On Transients, Maximum Loads 80 MLCC CAPS 70 I = 130mA ILOAD RIPPLE REJECTION – dB VOLTAGE – 20mV/DIV I = 50mA VCCA VTCXO VCCA 60 MLCC OUTPUT CAPS VBAT = 3.2V, FULL LOADS 50 REFOUT VCC 40 30 20 10 0 4 10 100 TIME – 100ms/DIV 1k FREQUENCY – Hz 100k 10k Figure 12. Ripple Rejection vs. Frequency Figure 9. VCCA Load Step 80 REFOUT 70 RIPPLE REJECTION – dB PWRONIN AND ANALOGON (2V/DIV) VOLTAGE VCCA (100mV/DIV) VTCXO (100mV/DIV) VCC (100mV/DIV) 60 50 40 VCCA VTCXO 20 FREQUENCY = 217Hz MAX LOADS 10 0 2.5 TIME – 50ms/DIV VCC 30 2.6 2.7 2.8 2.9 3.0 VBAT – V 3.1 3.2 3.3 Figure 13. Ripple Rejection vs. Battery Voltage Figure 10. Turn-On Transients, Minimum Loads –8– REV. 0 ADP3401 These functions have traditionally been done as either a discrete implementation or a custom ASIC design. ADP3401 combines the benefits of both worlds by providing an integrated standard product solution where every block is optimized to operate in a GSM environment while maintaining a cost-competitive solution. Hz 600 VOLTAGE SPECTRAL NOISE DENSITY – nV/ FULL LOAD MLCC CAPS 500 VCCA TCXO 400 Figure 15 shows the external circuitry associated with the ADP3401. Only a few support components, mainly decoupling capacitors, are required. 300 Input Voltage 200 REF The input voltage range for ADP3401 is 3 V to 7 V and optimized for a single Li-Ion cell or three NiMH/NiCd cells. The ADP3401 uses Analog Devices’ patented package thermal enhancement technology, which allows 15% improvement in power handling capability over standard plastic packages. The thermal impedance (θJA) of the ADP3401 is 60°C/W. The charging voltage for a high capacity NiMH cell can be as high as 5.5 V. Power dissipation should be calculated at maximum ambient temperatures and battery voltage in order not to exceed the 125°C maximum allowable junction temperature. Figure 16 shows the maximum total LDO output current as a function of ambient temperature and battery voltage. 100 0 10 1k FREQUENCY – Hz 100 10k 100k Figure 14. Output Noise Density THEORY OF OPERATION The ADP3401 is a power management chip optimized for use with the AD20msp425 GSM baseband chipsets in handset applications. Figure 1 shows a functional block diagram of the ADP3401. The ADP3401 contains several blocks: However, high battery voltages normally occur only when the battery is being charged and the handset is not in conversation mode. In this mode there is a relatively light load on the LDOs. A fully charged Li-Ion battery is 4.25 V, where the LDOs deliver the maximum 240 mA up to the max 85°C ambient temperature. • Four Low Dropout Regulators (Digital, Analog, Crystal Oscillator, Real-Time Clock) • Reset Generator • Buffered Precision Reference • SIM Interface Logic Level Translation (3 V/5 V) • SIM Voltage Supply • Power-On/-Off Logic • Undervoltage Lockout CHARGER INPUT R1 1 VBAT AGND 28 2 VCC VCCA 27 3 PWRONKEY REFOUT 26 4 ANALOGON RESET 25 5 PWRONIN VTCXO 24 6 ROWX 7 CHRON 10mF 1 Li-ION OR 3 NiMH CELLS 2.2mF 100V 2.2mF 10mF GSM PROCESSOR 0.22mF DIGITAL AND SIM GND R2 RESCAP 22 100nF ADP3401 BACKUP COIN CELL ANALOG GND DGND 23 8 VRTC CAP+ 21 9 CAP– VSIM 20 100nF 10mF 100nF SIM PIN OF GSM PROCESSOR 10 SIMBAT CLK 19 11 DATAIO SIMON 18 12 RESETIN GSM PROCESSOR SIMPROG 17 13 CLKIN RST 16 14 SIMGND I/O 15 Figure 15. Typical Application Circuit REV. 0 CLK TO SIMCARD 10mF –9– RST TO SIMCARD I/O TO SIM CARD ADP3401 RTC LDO (VRTC) 300 4-LAYER BOARD uJA = 608C/W The RTC LDO charges a rechargable coin cell to run the realtime clock module. It has been targeted to charge Manganese Lithium batteries such as the ML series (ML621/ML1220) from Sanyo. The ML621 has a small physical size (6.8 mm diameter) and a nominal capacity of 2.5 mAh, which yields about 250 hours of backup time. VBAT = 5V TOTAL LDO CURRENT – mA 250 VBAT = 5.5V 200 VBAT = 6V VBAT = 7V 150 Figure 18 shows the use of VRTC with the Enhanced GSM Processor which is a part of the AD20msp425 chipset. 100 ENHANCED GSM PROCESSOR (AD20msp425) ADP3401 50 0 220 0 20 40 60 AMBIENT TEMPERATURE – 8C 80 85 VRTC VRTC COIN CELL Figure 16. Total LDO Load Current vs. Temperature and VBAT RTC MODULE Low Dropout Regulators (LDOs) PWRONIN The ADP3401 high-performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise. 2.2 µF tantalum or MLCC ceramic capacitors are recommended for use with the digital and analog LDOs, and 0.22 µF for the TCXO LDO. Figure 18. Connecting VRTC and POWERONIN to the AD20msp425 Chipset Digital LDO (VCC) The ADP3401 supplies current both for charging the coin cell and for the RTC module when the digital supply is off. The nominal charging voltage of 2.85 V ensures charging down to a main battery voltage of 3.0 V. The inherent current limit of VRTC ensures long cell life while the precise output voltage regulation charges the cell to more than 90% of its capacity. In addition, it features a very low quiescent current (10 µA) since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage which is needed when the main battery is removed and the coin cell supplies the RTC module. POWER The digital LDO (VCC) supplies all the digital circuitry in the handset (baseband processor, baseband converter, external memory, display, etc). The LDO has been optimized for very low quiescent current (30 µA maximum) at light loads as this LDO is on at all times. This is due to both the structure of GSM and a new clocking scheme used in the AD20msp425. Figure 17 shows how the digital current varies as a function of time. ~2ms 0.5s TO 2s The RTC module has a built-in alarm which, when it expires, will pull POWERONIN high, allowing an alarm function even if the handset is switched off. ~50mA Reference Output (REFOUT) ~200mA The reference output is a low-noise, high-precision reference with a guaranteed accuracy of 1.5% over temperature. The reference can be fed to the baseband converter, such as the AD6425, improving the absolute accuracy of the converters from 5% to 1.5%. This significantly reduces calibration time needed for the baseband converter during production. TIME MICROPROCESSOR START PWRON MICROPROCESSOR STOP Figure 17. Digital Power as a Function of Time Analog LDO (VCCA) This LDO has the same features as the digital LDO. It has furthermore been optimized for good low frequency ripple rejection for use with analog sections in order to reject the ripple coming from the RF power amplifier. VCCA is rated to 130 mA load which is sufficient to supply the complete analog section of a baseband converter such as the AD6421/AD6425, including a 32 Ω earpiece. The analog LDO and the TCXO LDO can be controlled by ANALOGON. SIM Interface The SIM interface generates the needed SIM voltage—either 3 V or 5 V, dependent on SIM type, and also performs the needed logic level translation. Quiescent current is low, as the SIM card will be powered all the time. Note that DATAIO and I/O have integrated pull-up resistors as shown in Figure 19. See Table II for the control logic of the charge pump output, VSIM. TCXO LDO (VTCXO) The TCXO LDO is intended as a supply for the temperaturecompensated crystal oscillator, which needs its own ultralow noise supply. The output current is rated to 5 mA for the TCXO LDO. –10– REV. 0 ADP3401 RESET ADP3401 VCC LEVEL SHIFT RESETIN VCC RST VSIM LEVEL SHIFT CLKIN ADP3401 contains reset circuitry that is active both at power-up and at power-down. RESET is held low at power-up. An internal power-good signal starts the reset delay. The delay is set by an external capacitor on RESCAP: VSIM tRESET = 1.0 CLK VCC A 100 nF capacitor will produce a 100 ms reset time. At power-off, RESET will be kept low to prevent any spurious microprocessor starts. The current capability of RESET is low (a few hundred nA) when VCC is off, to minimize power consumption. Therefore, RESET should only be used to drive a single CMOS input. When VCC is on, RESET will drive about 15 µA. VSIM DATAIO I/O Figure 19. Schematic for Level Translators Overtemperature Protection Power-On/-Off ADP3401 handles all issues regarding power-on/-off of the handset. It is possible to turn on the ADP3401 in three different ways: • Pulling PWRONKEY low • Pulling PWRONIN high • CHRON exceeds threshold Pulling PWRONKEY key low is the normal way of turning on the handset. This will turn on all the LDOs as long as PWRONKEY is held low. The microprocessor then starts and pulls PWRONIN high after which PWRONKEY can be released. PWRONIN going high will also turn on the handset. This is the case when the alarm in the RTC module expires. An external charger can also turn on the phone. The turn-on threshold and hysteresis can be programmed via external resistors to allow full flexibility with any external charger and battery chemistry. These resistors are referred to as R1 and R2 in Figure 15. Undervoltage Lockout (ULVO) The UVLO function in the ADP3401 prevents startup when the initial voltage of the main battery is below the 3.0 V threshold. If the battery is this low with no load, there will be little or no capacity left. When the battery is greater than 3.0 V, as with the insertion of a fresh battery, the UVLO comparator trips, the RTC LDO is enabled, and the threshold is reduced to 2.9 V. This allows the handset to start normally until the battery voltage decays to 2.9 V open circuit. Once the 3.0 V threshold is exceeded, the RTC LDO is enabled. If, however, the backup coin cell is not connected, or is damaged or discharged below 1.5 V, the RTC LDO will not start on its own. In this situation, the RTC LDO will be started by enabling the VCC LDO. Once the system is started, i.e., the phone is turned on and the VCC LDO is up and running, the UVLO function is entirely disabled. The ADP3401 is then allowed to run down to very low battery voltages, typically around 2 V. The battery voltage is normally monitored by the microprocessor and usually shuts the phone off at around 3.0 V. If the phone is off, i.e., the VCC LDO is off, and the battery voltage drops below 2.9 V, the UVLO circuit disables startup and the RTC LDO. This is implemented with very low quiescent current, typically 3 µA, to protect the main battery against any damage. NiMH batteries can reverse polarity if the 3-cell battery voltage drops below 3.0 V and a current of more than about 40 µA continues to flow. Lithium ion batteries will lose their capacity, although the built-in safety circuits normally present in these cells will most likely prevent any damage. REV. 0 ms × CRESCAP nF The maximum die temperature for ADP3401 is 125°C. If the die temperature exceeds 160°C, the ADP3401 will disable all the LDOs except the RTC LDO, which has very limited current capabilities. The LDOs will not be re-enabled before the die temperature is below 125°C, regardless of the state of PWRONKEY, PWRONIN, and CHRON. This ensures that the handset will always power-off before the ADP3401 exceeds its absolute maximum thermal ratings. APPLICATIONS INFORMATION Input Capacitor Selection For the input voltage, VBAT, of the ADP3401, a local bypass capacitor is recommended. Use a 5 µF to 10 µF, low ESR capacitor. Multilayer ceramic chip capacitors provide the best combination of low ESR and small size, but may not be cost-effective. A lower cost alternative may be to use a 5 µF to 10 µF tantalum capacitor with a small (1 µF to 2 µF) ceramic in parallel. LDO Capacitor Selection The performance of any LDO is a function of the output capacitor. The digital and analog LDOs require a 2.2 µF capacitor and the TCXO LDO requires a 0.22 µF capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. All the LDOs are stable with a wide range of capacitor types and ESR due to Analog Devices’ anyCAP technology. The ADP3401 is stable with extremely low ESR capacitors (ESR ~ 0), such as multilayer ceramic capacitors, but care should be taken in their selection. Note that the capacitance of some capacitor types shows wide variations over temperature or with dc voltage. A good quality dielectric, X7R or better, is recommended. The RTC LDO has a rechargeable coin cell or an electric doublelayer capacitor as a load, but an additional 0.1 µF ceramic capacitor is recommended for stability and best performance. Charge Pump Capacitor Selection For the input (SIMBAT) and output (VSIM) of the SIM charge pump, use 10 µF low ESR capacitors. The use of low ESR capacitors improves the noise and efficiency of the SIM charge pump. Multilayer ceramic chip capacitors provide the best combination of low ESR and small size but may not be cost-effective. A lower cost alternative may be to use a 10 µF tantalum capacitor with a small (1 µF to 2 µF) ceramic capacitor in parallel. –11– For the lowest ripple and best efficiency, use a 0.1 µF, ceramic capacitor for the charge pump flying capacitor (CAP+ and CAP–). A good quality dielectric, such as X7R is recommended. Example: R1 = 10 kΩ and R2 = 30.2 kΩ gives a charger threshold (not counting the drop in the power Schottky diode) of 3.5 V ± 160 mV with a 200 mV ± 30 mV hysteresis. Setting the Charger Turn-On Threshold Charger Diode Selection The ADP3401 can be turned on when the charger input exceeds a programmable threshold voltage. The charger’s threshold and hysteresis are set by selecting the values for R1 and R2 shown in Figure 15. The diode shown in Figure 15 is used to prevent the battery from discharging into the charger turn-on setting resistors, R1 and R2. A Schottky diode is recommended to minimize the voltage difference from the charger to the battery and the power dissipation. Choose a diode with a current rating high enough to handle both the battery charging current and the current the ADP3401 will draw if powered up during charging. The battery charging current is dependent on the battery chemistry and the charger circuit. The ADP3401 current will be dependent on the loading. The turn-on threshold for the charger is calculated using: R2 + RHYS VCHR = × R1 + 1 × VT R2 × RHYS Where VT is the CHRON threshold voltage and RHYS is the CHRON hysteresis resistance. Printed Circuit Board Layout Considerations Use the following general guidelines when designing printed circuit boards: The hysteresis is determined using: 1. Split the battery connection to the VBAT and SIMBAT pins of the ADP3401. Use separate traces for each connection and locate the input capacitors as close to the pins as possible. VT × R1 RHYS Combining the above equations and solving for R1 and R2 gives the following formulas: R1 = R2 = RHYS × VHYS VT 2. SIM input and output capacitors should be returned to the SIMGND and kept as close as possible to the ADP3401 to minimize noise. Traces to the SIM charge pump capacitor should be kept as short as possible to minimize noise. 3. VCCA and VTCXO capacitors should be returned to AGND. R1 × RHYS VCHR − 1 × RHYS − R1 V T 4. VCC and VRTC capacitors should be returned to DGND. 5. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds, and tie them together at a single point, preferably close to the battery return. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Thin Shrink Small Outline (TSSOP) (RU-28A) 0.386 (9.80) 0.378 (9.60) 28 15 0.244 (6.20) 0.236 (6.00) 0.325 (8.25) 0.313 (7.95) 1 PRINTED IN U.S.A. VHYS = C3768–8–1/00 (rev. 0) ADP3401 14 PIN 1 0.0374 (0.95) 0.0335 (0.85) 0.0433 (1.10) MAX 0.006 (0.15) 0.0256 0.0118 (0.30) SEATING 0.002 (0.05) (0.65) 0.0075 (0.19) PLANE BSC 0.0078 (0.200) 0.0035 (0.090) –12– 88 08 0.030 (0.75) 0.020 (0.50) REV. 0