Order this document by MTW35N15E/D SEMICONDUCTOR TECHNICAL DATA "'# % #!$$%"# '% $" % "&!%! " N–Channel Enhancement–Mode Silicon Gate This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Isolated Mounting Hole Reduces Mounting Hardware Motorola Preferred Device TMOS POWER FET 35 AMPERES 150 VOLTS RDS(on) = 0.05 OHM D G CASE 340K–01, Style 1 TO–247AE S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit Drain–Source Voltage VDSS 150 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 150 Vdc Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 35 26.9 105 Adc Total Power Dissipation Derate above 25°C PD 180 1.45 Watts W/°C TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 80 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 Ω) EAS 600 mJ Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient RθJC RθJA 0.70 62.5 °C/W TL 260 °C Rating Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Apk Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 3 TMOS Motorola Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1 MTW35N15E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 150 — — 210 — — Vdc mV/°C — — — — 10 100 — — 100 nAdc 2.0 — — 7.0 4.0 — Vdc mV/°C — — 0.05 Ohm — — 1.45 — 1.8 1.7 gFS 11 18 — mhos Ciss — 3600 5040 pF Coss — 855 1170 Crss — 165 330 td(on) — 28 56 tr — 170 346 td(off) — 90 180 tf — 103 210 QT — 98 137 Q1 — 19 — Q2 — 49 — Q3 — 40 — — — 0.95 0.9 1.5 — trr — 200 — ta — 167 — tb — 32 — QRR — 1.63 — µC Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD — 4.5 — nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS — 13 — nH OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS µAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Temperature Coefficient (Negative) VGS(th) Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 17.5 Adc) RDS(on) Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 35 Adc) (ID = 17.5 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 17.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, Vdc VGS = 0 Vdc, Vdc f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time Rise Time Turn–Off Delay Time (VDD = 75 Vdc, Vd ID = 35 Adc, Ad VGS = 10 Vdc Vdc, RG = 9.1 Ω)) Fall Time Gate Charge (See Figure 8) ((VDS = 120 Vdc, Vd , ID = 35 Adc, Ad , VGS = 10 Vdc) ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (1) (IS = 35 Adc, VGS = 0 Vdc) (IS = 35 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (See Figure 14) Ad , VGS = 0 Vdc, Vd , ((IS = 35 Adc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data MTW35N15E TYPICAL ELECTRICAL CHARACTERISTICS I D , DRAIN CURRENT (AMPS) 60 70 VGS = 10 V 9.0 V TJ = 25°C 8.0 V 7.0 V 50 40 30 6.0 V 20 5.0 V 10 0 1.0 0.5 1.5 2.0 2.5 3.0 40 30 20 100°C 4.0 6.0 5.0 7.0 Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics TJ = 100°C 0.06 0.05 25°C 0.04 0.03 – 55°C 0.02 0.01 10 50 30 40 20 ID, DRAIN CURRENT (AMPS) 70 60 2.5 TJ = 25°C 0.045 0.043 VGS = 10 V 0.041 0.039 15 V 0.037 0.035 0 10 1000 VGS = 0 V 2.0 I DSS , LEAKAGE (nA) 100 1.0 50 20 30 40 ID, DRAIN CURRENT (AMPS) 70 60 Figure 4. On–Resistance versus Drain Current and Gate Voltage VGS = 10 V ID = 17.5 A 1.5 8.0 0.047 Figure 3. On–Resistance versus Drain Current and Temperature RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) TJ = – 55°C 3.0 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 0.07 TJ = 125°C 100°C 10 1.0 0.5 0 – 50 25°C VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS = 10 V 0 50 0 2.0 4.0 3.5 0.09 0.08 VDS ≥ 10 V 60 10 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) I D , DRAIN CURRENT (AMPS) 70 25°C – 25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 150 Figure 5. On–Resistance Variation with Temperature Motorola TMOS Power MOSFET Transistor Device Data 0.1 0 100 50 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 150 Figure 6. Drain–To–Source Leakage Current versus Voltage 3 MTW35N15E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) space 10000 VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 8000 6000 Crss Ciss 4000 2000 Coss Crss 0 10 5 5 0 VGS 10 15 20 25 VDS GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data 120 QT 10 100 VGS Q2 Q1 8.0 80 60 6.0 4.0 40 TJ = 25°C ID = 35 A 20 2.0 VDS Q3 0 0 20 40 60 80 0 100 1000 VDD = 75 V ID = 35 A VGS = 10 V TJ = 25°C t, TIME (ns) 12 VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) MTW35N15E tr 100 tf td(off) td(on) 10 0 10 QT, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS) Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 DRAIN–TO–SOURCE DIODE CHARACTERISTICS I S , SOURCE CURRENT (AMPS) 35 VGS = 0 V TJ = 25°C 30 25 20 15 10 5 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reli- Motorola TMOS Power MOSFET Transistor Device Data able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain– to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 5 MTW35N15E SAFE OPERATING AREA 600 VGS = 20 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT EAS, SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 1000 100 10 µs 10 100 µs 1.0 10 ms DC 1 ms 0.1 1.0 10 100 ID = 35 A 500 400 300 200 100 0 1000 25 50 75 100 125 150 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.05 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 t1 SINGLE PULSE 0.01 1.0E–05 1.0E–04 t2 DUTY CYCLE, D = t1/t2 1.0E–02 t, TIME (s) 1.0E–03 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 1.0E–01 1.0E+00 1.0E+01 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTW35N15E PACKAGE DIMENSIONS 0.25 (0.010) M –T– –Q– T B M E –B– C 4 L U A R 1 K 2 3 –Y– P V H F D 0.25 (0.010) M Y Q J G S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. DIM A B C D E F G H J K L P Q R U V STYLE 1: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 19.7 20.3 15.3 15.9 4.7 5.3 1.0 1.4 1.27 REF 2.0 2.4 5.5 BSC 2.2 2.6 0.4 0.8 14.2 14.8 5.5 NOM 3.7 4.3 3.55 3.65 5.0 NOM 5.5 BSC 3.0 3.4 INCHES MIN MAX 0.776 0.799 0.602 0.626 0.185 0.209 0.039 0.055 0.050 REF 0.079 0.094 0.216 BSC 0.087 0.102 0.016 0.031 0.559 0.583 0.217 NOM 0.146 0.169 0.140 0.144 0.197 NOM 0.217 BSC 0.118 0.134 GATE DRAIN SOURCE DRAIN CASE 340K–01 ISSUE O Motorola TMOS Power MOSFET Transistor Device Data 7 MTW35N15E Motorola reserves the right to make changes without further notice to any products herein. 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