BF 1012S Silicon N-Channel MOSFET Tetrode • For low noise, high gain controlled input stages up to 1GHz • Operating voltage 5V • Integrated stabilized bias network ESD: Electrostatic discharge sensitive device, observe handling precaution! Type Marking Ordering Code BF 1012S NYs Q62702-F1627 Pin Configuration 1=S 2=D Package 3 = G2 4 = G1 SOT-143 Maximum Ratings Parameter Symbol Value Unit Drain-source voltage VDS 16 V Continuos drain current ID 25 mA Gate 1/gate 2 peak source current ±I G1/2SM 10 Gate 1 (external biasing) +VG1SE 3 Total power dissipation, T S ≤ 76 °C Ptot 200 Storage temperature T stg -55 ...+150 Channel temperature T ch 150 V mW °C Thermal Resistance Channel - soldering point Rthchs ≤370 K/W Note: It is not recommended to apply external DC-voltage on Gate 1 in active mode. Semiconductor Group Semiconductor Group 11 Au 1998-11-01 -25-1998 BF 1012S Electrical Characteristics at TA = 25°C, unless otherwise specified. Symbol Values Parameter Unit min. typ. max. DC characteristics Drain-source breakdown voltage V(BR)DS 16 - - V I D = 300 µA, -V G1S = 4 V, - V G2S = 4 V Gate 1 source breakdown voltage ±V (BR)G1SS 8 - 12 ±V (BR)G2SS 10 - 16 +I G1SS - - 60 µA ±I G2SS - - 50 nA I DSS - - 500 µA I DSO 8 12 - mA VG2S(p) - 0.9 - V 26 30 - mS Cg1ss - 2.1 2.7 pF Cdss - 0.9 - G ps 18 22 - F 800 - 1.4 - ∆Gps 40 50 - ±I G1S = 10 mA, VG2S = V DS = 0 Gate 2 source breakdown voltage ±I G2S = 10 mA, VG1S = 0 V, V DS = 0 V Gate 1 source current VG1S = 6 V, V G2S = 0 V Gate 2 source leakage current ±VG2S = 8 V, V G1S = 0 V, V DS = 0 V Drain current VDS = 12 V, V G1S = 0 , V G2S = 6 V Operating current (selfbiased) VDS = 12 V, V G2S = 6 V Gate 2-source pinch-off voltage VDS = 12 V, I D = 100 µA AC characteristics Forward transconductance (self biased) g fs VDS = 12 V, V G2S = 6 V, f = 1 kHz Gate 1-input capacitance (self biased) VDS = 12 V, V G2S = 6 , f = 1 MHz Output capacitance (self biased) VDS = 12 V, V G2S = 6 , f = 1 MHz Power gain (self biased) dB VDS = 12 V, V G2S = 6 , f = 800 MHz Noise figure (self biased) VDS = 12 V, V G2S = 6 , f = 800 MHz Gain control range (self biased) VDS = 12 V, V G2S = 6 V, f = 800 MHz Semiconductor Group Semiconductor Group 22 Au 1998-11-01 -25-1998 BF 1012S Total power dissipation P tot = f (T S) Drain current ID = f (VG2S) 300 15 mA mW 12 10 ID P tot 11 200 9 8 150 7 6 100 5 4 3 50 2 1 0 0 20 40 60 80 100 120 °C 0 0.0 150 1.0 2.0 3.0 4.0 V TS 6.0 VG2S Insertion power gain Forward transfer admittance | S 21 | 2 = f (V G2S) | Y 21 | = f (V G2S) 28 10 dB mS -5 22 -10 20 |Y21| | S21 |2 24 -15 -20 18 16 -25 14 -30 12 -35 10 -40 8 -45 -50 6 -55 4 -60 2 -65 0.0 1.0 2.0 3.0 4.0 V 0 0.0 6.0 VG2S Semiconductor Group Semiconductor Group 1.0 2.0 3.0 4.0 V 6.0 VG2S 33 Au 1998-11-01 -25-1998 BF 1012S Output capacitance C dss = f (V G2) f = 200MHz 3.0 pF 3.0 pF 2.4 2.4 2.2 2.2 Cdss Cg1ss Gate 1 input capacitance Cg1ss = f (V g2s) f = 200MHz 2.0 1.8 2.0 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 1.0 2.0 3.0 4.0 V 0.0 0.0 6.0 VG2S Semiconductor Group Semiconductor Group 1.0 2.0 3.0 4.0 V 6.0 VG2S 44 Au 1998-11-01 -25-1998