データシート

[AK4385]
AK4385
108dB 192kHz 24-Bit 2ch ΔΣ DAC
AK4385
24
DAC
ΔΣ
(SCF)
192kHz
DVD, AC-3
AK4385
16pin TSSOP
†
† 128
† 64
† 32
† 24
† SCF
†
†
†
†
†
: 8kHz ∼ 192kHz
2
4
8
FIR
(32kHz, 44.1kHz, 48kHz
)
ATT (
256
)
I/F
: 24
, 24/20/16
: 256fs, 384fs, 512fs, 768fs or 1152fs
128fs, 192fs, 256fs or 384fs 2
128fs or 192fs 4
† THD+N: -94dB
† Dynamic Range: 108dB
†
†
: 4.75 ∼ 5.25V
†
: 16pin TSSOP (6.4mm x 5.0mm)
† AK4381
, I2S
MCLK
VDD
CSN
CCLK
µP
Interface
De-emphasis
Control
VSS
Clock
Divider
DZFL
CDTI
DZFR
LRCK
BICK
SDTI
Audio
Data
Interface
8X
Interpolator
ΔΣ
Modulator
SCF
8X
Interpolator
ΔΣ
Modulator
SCF
AOUTL+
AOUTLAOUTR+
AOUTR-
PDN
MS0246-J-02
2010/09
-1-
[AK4385]
■
-20 ∼ +85°C
-40 ∼ +85°C
AK4385
AK4385ET
AK4385VT
AKD4385
16pin TSSOP (0.65mm pitch)
16pin TSSOP (0.65mm pitch)
■
No.
1
Pin Name
MCLK
MCLK
1
16
DZFL
BICK
2
15
DZFR
SDTI
3
14
VDD
LRCK
4
13
VSS
PDN
5
12
AOUTL+
CSN
6
11
AOUTL-
CCLK
7
10
AOUTR+
CDTI
8
9
AOUTR-
Top
View
I/O
I
Function
Master Clock Input Pin
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock Pin
3
SDTI
I
Audio Serial Data Input Pin
4
LRCK
I
L/R Clock Pin
5
PDN
I
Power-Down Mode Pin
When at “L”, the AK4385 is in the power-down mode and is held in reset.
The AK4385 must be reset once upon power-up.
6
CSN
I
Chip Select Pin
7
CCLK
I
Control Data Input Pin
8
CDTI
I
Control Data Input Pin
9
AOUTRO
Rch Negative Analog Output Pin
10
AOUTR+
O
Rch Positive Analog Output Pin
11
AOUTLO
Lch Negative Analog Output Pin
12
AOUTL+
O
Lch Positive Analog Output Pin
13
VSS
Ground Pin
14
VDD
Power Supply Pin
15
DZFR
O
Rch Data Zero Input Detect Pin
16
DZFL
O
Lch Data Zero Input Detect Pin
Note: All input pins should not be left floating.
MS0246-J-02
2010/09
-2-
[AK4385]
(VSS=0V; Note 1)
Parameter
Power Supply
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
AK4385ET
(Powered applied)
AK4385VT
Storage Temperature
Note: 1.
Symbol
VDD
IIN
VIND
Ta
Ta
Tstg
min
-0.3
-0.3
-20
-40
-65
max
6.0
±10
VDD+0.3
85
85
150
Units
V
mA
V
°C
°C
°C
:
(VSS=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
min
4.75
typ
5.0
max
5.25
Units
V
:
MS0246-J-02
2010/09
-3-
[AK4385]
(
Ta = 25°C; VDD = 5.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥4kΩ)
Parameter
min
typ
max
Resolution
24
Dynamic Characteristics
(Note 3)
THD+N
fs=44.1kHz
0dBFS
-94
-84
BW=20kHz
-60dBFS
-44
fs=96kHz
0dBFS
-92
BW=40kHz
-60dBFS
-41
fs=192kHz
0dBFS
-92
BW=40kHz
-60dBFS
-41
Dynamic Range (-60dBFS with A-weighted)
(Note 4)
100
108
S/N
(A-weighted)
(Note 5)
100
108
Interchannel Isolation (1kHz)
90
110
Interchannel Gain Mismatch
0.2
0.5
DC Accuracy
Gain Drift
100
Output Voltage
(Note 6)
±2.55
±2.75
±2.95
Load Resistance
(Note 7)
4
Power Supplies
Power Supply Current (VDD)
17
27
Normal Operation (PDN = “H”, fs≤96kHz)
20
32
Normal Operation (PDN = “H”, fs=192kHz)
10
100
Power-Down Mode (PDN = “L”)
(Note 8)
Notes: 3. Audio Precision (System Two)
4. 100dB at 16bit data.
5. S/N
6.
(0dB)
VDD
AOUT ([email protected]) = (AOUT+) - (AOUT-) = ±2.75Vpp×VDD/5
7. AC
DC
4kΩ
8.
(MCLK, BICK, LRCK)
VDD
VSS
MS0246-J-02
Units
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
Vpp
kΩ
mA
mA
µA
2010/09
-4-
[AK4385]
(Ta = 25°C; VDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “0”)
Parameter
Symbol
min
Digital filter
PB
0
Passband
±0.05dB (Note 9)
-6.0dB
Stopband
(Note 9)
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay
(Note 10)
GD
Digital Filter + SCF
Frequency Response 20.0kHz fs=44.1kHz
FR
40.0kHz fs=96kHz
FR
80.0kHz fs=192kHz
FR
Notes: 9.
fs (
PB=0.4535*fs(@±0.05dB) SB=0.546*fs
10.
16/24
typ
max
Units
22.05
20.0
-
19.3
-
kHz
kHz
kHz
dB
dB
1/fs
± 0.2
± 0.3
+0.1/-0.6
-
dB
dB
dB
± 0.02
)
(Ta = 25°C; VDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)
Parameter
Symbol
min
typ
max
Units
PB
0
39.2
18.2
8.1
-
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 11)
(Note 11)
(Note 10)
SB
PR
SA
GD
72
-
19.3
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0/-5
+0/-4
+0.1/-5
-
dB
dB
dB
typ
-
max
0.8
0.4
± 10
Units
V
V
V
V
µA
± 0.005
Digital Filter + SCF
FR
20.0kHz fs=44.kHz
40.0kHz fs=96kHz
FR
80.0kHz fs=192kHz
FR
Note: 11. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
Frequency Response
DC
(Ta = 25°C; VDD = 4.75 ∼ 5.25V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout = -80µA)
Low-Level Output Voltage
(Iout = 80µA)
Input Leakage Current
Symbol
VIH
VIL
VOH
VOL
Iin
MS0246-J-02
min
2.2
VDD-0.4
-
-
2010/09
-5-
[AK4385]
(Ta = 25°C; VDD = 4.75 ∼ 5.25V)
Parameter
Master Clock Frequency
Duty Cycle
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
Audio Interface Timing
BICK Period
Normal Speed Mode
Double/Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge
(Note 12)
LRCK Edge to BICK “↑”
(Note 12)
SDTI Hold Time
SDTI Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
(Note 13)
Notes: 12.
LRCK
BICK
13.
PDN “L”
“H”
Symbol
fCLK
dCLK
min
2.048
40
typ
11.2896
max
36.864
60
Units
MHz
%
fsn
fsd
fsq
Duty
8
60
120
45
48
96
192
55
kHz
kHz
kHz
%
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
tPD
150
ns
“↑”
MS0246-J-02
2010/09
-6-
[AK4385]
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Serial Interface Timing
MS0246-J-02
2010/09
-7-
[AK4385]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power-down Timing
MS0246-J-02
2010/09
-8-
[AK4385]
■
MCLK, LRCK, BICK
(MCLK)
(LRCK)
ΔΣ
MCLK
(Manual Setting Mode)
(Auto Setting Mode)
Manual Setting Mode (ACKS = “0”: Register 00H)
DFS0/1
(Table 1)
MCLK
(Table 2~4)
(PDN = “↑”) Auto Setting Mode
Auto Setting Mode (ACKS = “1”: Default)
MCLK
(Table 5)
(Table 6)
DFS0/1
MCLK
(PDN= “H”)
(MCLK, BICK, LRCK)
(PDN= “L”)
ON
(PDN = “↑”)
MCLK, LRCK
DFS1
DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
8kHz~48kHz
0
1
Double Speed Mode
60kHz~96kHz
1
0
Quad Speed Mode
Table 1.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896MHz
12.2880MHz
Table 3.
LRCK
fs
176.4kHz
192.0kHz
Table 4.
120kHz~192kHz
(Manual Setting Mode)
384fs
12.2880MHz
16.9344MHz
18.4320MHz
Table 2.
Default
MCLK
512fs
16.3840MHz
22.5792MHz
24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
(Normal Speed Mode
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
(Double Speed Mode
MCLK
128fs
192fs
22.5792MHz 33.8688MHz
24.5760MHz 36.8640MHz
(Quad Speed Mode
MS0246-J-02
1152fs
36.8640MHz
N/A
N/A
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Manual Setting Mode)
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Manual Setting Mode)
BICK
64fs
11.2896MHz
12.2880MHz
Manual Setting Mode)
2010/09
-9-
[AK4385]
MCLK
512fs
768fs
256fs
384fs
128fs
192fs
Table 5.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
Sampling Speed
Normal
Double
Quad
(Auto Setting Mode: Default)
192fs
33.8688
36.8640
MCLK (MHz)
256fs
384fs
22.5792
33.8688
24.5760
36.8640
-
Table 6.
512fs
16.3840
22.5792
24.5760
-
768fs
24.5760
33.8688
36.8640
-
Sampling Speed
Normal
Double
Quad
(Auto Setting Mode)
■
BICK LRCK
MSB
Mode 2
SDTI
2’s complement
LSB
16/20
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
16bit
20bit
24bit
24bit I2S
24bit
5
(Table 7)
DIF0-2
BICK
“0”
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Default
Table 7.
MS0246-J-02
2010/09
- 10 -
[AK4385]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
14
6
1
0
5
14
4
15
3
2
16
1
17
0
31
15
0
14
6
5
14
1
4
15
3
16
2
1
17
0
31
15
14
0
1
0
1
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1,4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
MS0246-J-02
2010/09
- 11 -
[AK4385]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
0
1
23 22
Don’t care
23 22
0
1
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
■
IIR
3
(32kHz, 44.1kHz, 48kHz)
Double Speed Mode, Quad Speed Mode
(50/15μs
)
OFF
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Table 8.
Default
(Normal Speed Mode)
■
AK4385 MUTE
DAC
256
ATT
0dB
-48dB
1
256
Table 9
Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
1 Level
4LRCK
8LRCK
16LRCK
255 to 0
1020LRCK
2040LRCK
4080LRCK
Table 9. ATT
MS0246-J-02
2010/09
- 12 -
[AK4385]
■
AK4385
DZF
DZF
“L”
8192
“H”
RSTN
“0”
DZF
“0”
DZFM
“1”
8192
“H”
DZFE
“0”
“0”
“H”
RSTN
“1”
DZF
4~5LRCK
“L”
“0”
DZF
DZF
“L”
DZF
DZFB
■
×ATT
(Table 9)
-∞
ATT
SMUTE
-∞ (“0”)
ATT
×ATT
“1”
ATT
SMUTE
ATT
”0”
-∞
-∞
ATT
SMUTE bit
(1)
ATT Level
(1)
(3)
Attenuation
-∞
GD
GD
(2)
AOUT
(4)
8192/fs
DZF pin
:
(1) ATT
×ATT
1020LRCK
(2)
(3)
0dB
(4)
(Table 9)
Normal Speed Mode
ATT
“255”
(GD)
-∞
8192
”0”
”0”
DZF
DZF
”L”
”H”
Figure 5.
MS0246-J-02
2010/09
- 13 -
[AK4385]
■
ON
PDN
LRCK
“↑”
“L”
MCLK
LRCK
■
PDN
L”
(Hi-Z)
Figure5
PDN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
(1)
D/A Out
(Analog)
GD
(2)
(3)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, LRCK, BICK
DZF
(6)
External
MUTE
(5)
(1)
(2)
(3) PDN
(4)
(5)
(6)
Mute ON
(GD)
Hi-Z
(“↑ ↓”)
“0”
(PDN = “L”)
(MCLK, BICK, LRCK)
(3)
(PDN
= “L”)
Figure 6.
DZF
“L”
/
MS0246-J-02
2010/09
- 14 -
[AK4385]
■
RSTN
VCOM
0”
DAC
DZFL/DZFR
"H"
Figure 7 RSTN
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
Normal Operation
Digital Block Power-down
D/A In
(Digital)
“0” data
(1)
GD
GD
(2)
(3)
D/A Out
(Analog)
(3)
(1)
(4)
Clock In
Don’t care
MCLK,LRCK,BICK
2/fs(5)
DZF
(1)
(2) RSTN = “0”
(3)
RSTN
(4)
(5) DZF
“L”
(6) RSTN
VCOM
(“↓ ↑”)
(RSTN = “0”)
RSTN
(GD)
(VDD/2)
“0”
(MCLK, BICK, LRCK)
“H”
LSI
RSTN
LSI
RSTN
2/fs
3 ~4/fs
2 ~ 3/fs
Figure 7.
MS0246-J-02
2010/09
- 15 -
[AK4385]
■
AK4385
3
I/F
address (MSB first, 5bit)
“↑”
5MHz (max)
PDN
I/F
: CSN, CCLK, CDTI
Chip address (2bit, C1/0, “01”
), Read/Write (1bit, “1”
, Write only), Register
Control data (MSB first, 8bit)
CCLK “↓”
CSN “↑”
CCLK
“L”
RSTN
“L”
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 8. Control I/F Timing
*AK4385
*PDN = “L”
C1/0, R/W
(“011”)
■ Register Map
Addr
00H
01H
02H
03H
04H
Notes:
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
D7
D6
D5
D4
D3
D2
D1
D0
ACKS
DZFE
0
ATT7
ATT7
0
DZFM
0
ATT6
ATT6
0
SLOW
0
ATT5
ATT5
DIF2
DFS1
0
ATT4
ATT4
DIF1
DFS0
0
ATT3
ATT3
DIF0
DEM1
DZFB
ATT2
ATT2
PW
DEM0
0
ATT1
ATT1
RSTN
SMUTE
0
ATT0
ATT0
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values.
All data can be written to the register even if PW or RSTN bit is “0”.
MS0246-J-02
2010/09
- 16 -
[AK4385]
■ Register Definitions
Addr
00H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 1
ACKS
0
0
DIF2
DIF1
DIF0
PW
RSTN
default
1
0
0
0
1
0
1
1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (see Table 7)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr
01H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
DZFE
DZFM
SLOW
DFS1
DFS0
DEM1
DEM0
SMUTE
default
0
0
0
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Table 8)
Initial: “01”, OFF
DFS1-0: Sampling speed control
00: Normal Speed Mode
01: Double Speed Mode
10: Quad Speed Mode
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise
occurs.
SLOW: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
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[AK4385]
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
Addr
02H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 3
0
0
0
0
0
DZFB
0
0
default
0
0
0
0
0
0
0
0
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
Addr
03H
04H
Register Name
Lch ATT
Rch ATT
default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
Figure 9
(AKD4385)
Master Clock
1
MCLK
DZFL
64fs
2
BICK
DZFR
15
24bit Audio Data
3
SDTI
VDD
14
0.1u
fs
Reset & Power down
Microcontroller
Digital Ground
16
4
LRCK
VSS
13
5
PDN
AOUTL+
12
6
CSN
AOUTL-
11
7
CCLK
AOUTR+
10
8
CDTI
AOUTR-
9
AK4385
+
Analog
Supply 5V
10u
Lch
LPF
Lch
MUTE
Lch Out
Rch
LPF
Rch
MUTE
Rch Out
Analog Ground
Figure 9. Typical Connection Diagram
Notes:
- LRCK = fs, BICK=64fs.
- AOUT
-
MS0246-J-02
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- 18 -
[AK4385]
1.
VDD
VSS
VDD
VDD
VSS
2.
2.5V
0.55 x VDD Vpp (typ)
VAOUT = (AOUT+)-(AOUT-)
AOUT+ AOUT5.5Vpp ([email protected]=5V)
2’s complement (2
) 7FFFFFH(@24bit)
000000H(@24bit)
VAOUT
ΔΣ
AK4385
Figure 10 11
800000H(@24bit)
0V
SCF
DC
AOUT+/- DC
LPF
4.7k
4.7k
AOUTR1
470p
Vop
3300p
4.7k
AOUT+
Vop
Analog
Out
R1
4.7k
470p
1k
BIAS
47u
0.1u
When R1=200Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180Ω
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
1k
Figure 10. External 2nd order LPF Circuit Example (using op-amp with single power supply)
4.7k
4.7k
AOUTR1
470p
+Vop
3300p
AOUT+
4.7k
Analog
Out
R1
4.7k
470p
-Vop
When R1=200Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180Ω
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
MS0246-J-02
2010/09
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[AK4385]
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
8
1
0.13
6.4±0.2
*4.4±0.1
A
0.65
0.22±0.1
M
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■
:
:
:
(
)
MS0246-J-02
2010/09
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[AK4385]
(AK4385VT)
AKM
4385VT
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4385VT
Asahi Kasei Logo
MS0246-J-02
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[AK4385]
(AK4385ET)
AKM
4385ET
XXYYY
5)
6)
7)
8)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4385ET
Asahi Kasei Logo
MS0246-J-02
2010/09
- 22 -
[AK4385]
Date (YY/MM/DD)
03/07/02
06/01/10
Revision
00
01
Reason
Page
Contents
2
AK4385ET
22
AK4385ET
10/09/28
02
20
z
z
z
z
z
z
MS0246-J-02
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- 23 -