Data Sheet

Freescale Semiconductor
Technical Data
Document Number: A2T18H410--24S
Rev. 0, 5/2015
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 71 W asymmetrical Doherty RF power LDMOS transistor is designed for
cellular base station applications covering the frequency range of 1805 to
1880 MHz.
A2T18H410--24SR6
1800 MHz
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 800 mA, VGSB = 0.8 Vdc, Pout = 71 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
1805 MHz
17.4
51.2
7.9
–34.5
1840 MHz
17.5
50.1
8.3
–36.9
1880 MHz
17.6
49.3
8.0
–36.8
1805–1880 MHz, 71 W AVG., 28 V
AIRFAST RF POWER LDMOS
TRANSISTOR
ACPR
(dBc)
Features
 Advanced High Performance In--Package Doherty
 Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
 Designed for Digital Predistortion Error Correction Systems
NI--1230S--4L2L
6 VBWA(1)
Carrier
RFinA/VGSA 1
5 RFoutA/VDSA
RFinB/VGSB 2
4 RFoutB/VDSB
Peaking
3 VBWB(1)
(Top View)
Figure 1. Pin Connections
1. Device cannot operate with the VDD current
supplied through pin 3 and pin 6.
 Freescale Semiconductor, Inc., 2015. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
A2T18H410--24SR6
1
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain--Source Voltage
Rating
VDSS
–0.5, +65
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
Case Operating Temperature Range
TC
–40 to +150
C
TJ
–40 to +225
C
CW
282
1.5
W
W/C
Operating Junction Temperature Range
(1,2)
CW Operation @ TC = 25C
Derate above 25C
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 72C, 71 W Avg., W--CDMA, 28 Vdc, IDQA = 800 mA, VGSB = 0.8 Vdc,
1840 MHz
Symbol
Value (2,3)
Unit
RJC
0.24
C/W
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
2
Machine Model (per EIA/JESD22--A115)
B
Charge Device Model (per JESD22--C101)
IV
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 160 Adc)
VGS(th)
1.4
1.5
2.3
Vdc
Gate Quiescent Voltage
(VDD = 28 Vdc, IDA = 800 mAdc, Measured in Functional Test)
VGS(Q)
2.2
2.6
3.0
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 1.6 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 270 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 2.7 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Characteristic
Off Characteristics (4)
On Characteristics -- Side A (Carrier)
On Characteristics -- Side B (Peaking)
1.
2.
3.
4.
Continuous use at maximum temperature will affect MTTF.
MTTF calculator available at http://www.freescale.com/rf/calculators.
Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf and search for AN1955.
Each side of device measured separately.
(continued)
A2T18H410--24SR6
2
RF Device Data
Freescale Semiconductor, Inc.
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests (1,2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 800 mA, VGSB = 0.8 Vdc, Pout = 71 W Avg.,
f = 1805 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in
3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
16.5
17.4
19.5
dB
Drain Efficiency
D
47.0
51.2
—
%
PAR
7.4
7.9
—
dB
ACPR
—
–34.5
–28.0
dBc
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Load Mismatch (2) (In Freescale Doherty Test Fixture, 50 ohm system) IDQA = 800 mA, VGSB = 0.8 Vdc, f = 1840 MHz
VSWR 10:1 at 32 Vdc, 440 W CW (3) Output Power
(3 dB Input Overdrive from 376 W CW (3) Rated Power)
No Device Degradation
Typical Performance (2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 800 mA, VGSB = 0.8 Vdc,
1805–1880 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
355 (3)
—
W
Pout @ 3 dB Compression Point (4)
P3dB
—
457
—
W

—
–12.4
—

VBWres
—
90
—
MHz
Gain Flatness in 75 MHz Bandwidth @ Pout = 71 W Avg.
GF
—
0.1
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.0056
—
dB/C
P1dB
—
0.0077
—
dB/C
AM/PM
(Maximum value measured at the P3dB compression point across
the 1805–1880 MHz frequency range)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30C to +85C) (3)
Table 5. Ordering Information
Device
A2T18H410--24SR6
1.
2.
3.
4.
Tape and Reel Information
R6 Suffix = 150 Units, 56 mm Tape Width, 13--inch Reel
Package
NI--1230S--4L2L
Part internally matched both on input and output.
Measurements made with device in an asymmetrical Doherty configuration.
Exceeds recommended operating conditions. See CW operation data in Maximum Ratings table.
P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
A2T18H410--24SR6
RF Device Data
Freescale Semiconductor, Inc.
3
VDDA
VDDA
C17
C9
R2
C1
C10
C19
C2
D68602
C11
C4
C12
Z1
R1
C6
C5
C8
A2T18H410
Rev. 4
C7
R3
CUT OUT AREA
C3
C13
C15
C16
C14
C18
VDDB
VGGB
Figure 2. A2T18H410--24SR6 Test Circuit Component Layout
Table 6. A2T18H410--24SR6 Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1, C7, C9, C14, C16, C19
10 uF Chip Capacitors
C5750X7S2A106M230KB
TDK
C2, C8, C10, C15
12 pF Chip Capacitors
ATC100B120JT500XT
ATC
C3
1.2 pF Chip Capacitor
ATC100B1R2BT500XT
ATC
C4, C6
6.2 pF Chip Capacitors
ATC100B6R2BT500XT
ATC
C5, C11
1.0 pF Chip Capacitors
ATC100B1R0CT500XT
ATC
C12
5.1 pF Chip Capacitor
ATC100B5R1CT500XT
ATC
C13
4.7 pF Chip Capacitor
ATC100B4R7CT500XT
ATC
C17, C18
470 uF, 63 V Electrolytic Capacitors
MCGPR63V477M13X26
Multicomp
R1
50  Termination
CW12010T0050GBK
ATC
R2, R3
2.7 , 1/4 W Chip Resistors
CRCW12062R7FKEA
Vishay
Z1
1700–2000 MHz Band, 5 dB Directional Coupler
X3C19P1-05S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D68602
MTL
A2T18H410--24SR6
4
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS
D
17.5
17.4
48
Gps
17.3
PARC
17.2
17.1
–27
–1.4
–30
–1.6
–33
17
–36
ACPR
16.9
16.8
1760
1780
1800
1820 1840 1860
f, FREQUENCY (MHz)
–39
1880
1900
–1.8
–2
–2.2
PARC (dB)
Gps, POWER GAIN (dB)
17.6
ACPR (dBc)
17.7
D, DRAIN
EFFICIENCY (%)
56
VDD = 28 Vdc, Pout = 71 W (Avg.), IDQA = 800 mA
VGSB = 0.8 Vdc, Single--Carrier W--CDMA, 3.84 MHz 54
Channel Bandwidth, Input Signal PAR = 9.9 dB @
52
0.01% Probability on CCDF
50
17.8
–2.4
–42
1920
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 71 Watts Avg.
–10
VDD = 28 Vdc, Pout = 8 W (PEP), IDQA = 800 mA
VGSB = 0.8 Vdc, Two--Tone Measurements
–20
(f1 + f2)/2 = Center Frequency of 1840 MHz
–30
IM3--L
IM3--U
IM5--U
–40
IM5--L
–50
IM7--L
–60
–70
1
IM7--U
10
500
100
TWO--TONE SPACING (MHz)
17.6
0
17.4
17.2
17
16.8
16.6
–1
VDD = 28 Vdc, IDQA = 800 mA, VGSB = 0.8 Vdc
f = 1840 MHz, Single--Carrier W--CDMA
3.84 MHz Channel Bandwidth
–3
Gps
D
ACPR
–5
25
PARC
Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF
50
55
–32
75
100
Pout, OUTPUT POWER (WATTS)
45
40
–2 dB = 78.1 W
–3 dB = 100 W
–4
–30
50
–1 dB = 55 W
–2
60
125
–34
–36
ACPR (dBc)
1
D DRAIN EFFICIENCY (%)
17.8
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
–38
35
–40
30
150
–42
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T18H410--24SR6
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
Gps, POWER GAIN (dB)
20
18 1805 MHz
Gps
1805 MHz
1840 MHz
1880 MHz
1840 MHz
16
1840 MHz
10
1880 MHz
ACPR
1880 MHz
50
–10
30
20
10
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
1
0
40
1805 MHz
14
12
D
60
0
500
10
100
Pout, OUTPUT POWER (WATTS) AVG.
–20
–30
–40
ACPR (dBc)
VDD = 28 Vdc, IDQA = 800 mA, VGSB = 0.8 Vdc
Single--Carrier W--CDMA
D, DRAIN EFFICIENCY (%)
22
–50
–60
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
22
20
Gain
GAIN (dB)
18
16
14
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 800 mA
VGSB = 0.8 Vdc
12
10
1600
1680
1760
1840 1920 2000
f, FREQUENCY (MHz)
2080
2160
2240
Figure 7. Broadband Frequency Response
A2T18H410--24SR6
6
RF Device Data
Freescale Semiconductor, Inc.
Table 7. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 785 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1805
1.32 – j3.98
1.36 + j3.59
1840
1.57 – j4.28
1.50 + j3.86
1880
2.23 – j4.77
1.99 + j4.16
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1.01 – j3.41
18.7
52.6
181
58.4
–12
0.98 – j3.56
18.7
52.6
183
58.3
–12
0.98 – j3.75
18.6
52.6
181
57.2
–12
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
1.32 – j3.98
1.22 + j3.74
1.02 – j3.56
16.5
53.3
215
59.4
–15
1840
1.57 – j4.28
1.37 + j4.04
0.99 – j3.72
16.5
53.4
217
59.2
–15
1880
2.23 – j4.77
1.87 + j4.43
1.00 – j3.90
16.4
53.3
214
58.3
–16
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 8. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, IDQA = 785 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
1.32 – j3.98
1.35 + j3.89
2.22 – j2.08
22.4
49.9
98
72.1
–19
1840
1.57 – j4.28
1.55 + j4.11
2.07 – j2.49
22.0
50.3
108
71.1
–17
1880
2.23 – j4.77
2.11 + j4.44
1.93 – j2.67
21.8
50.4
109
70.0
–18
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2.04 – j2.31
20.1
51.1
128
73.3
–25
1.38 + j4.21
1.96 – j2.52
19.9
51.2
130
72.5
–24
1.94 + j4.64
1.93 – j2.64
19.9
51.0
127
71.4
–24
f
(MHz)
Zsource
()
Zin
()
1805
1.32 – j3.98
1.20 + j3.91
1840
1.57 – j4.28
1880
2.23 – j4.77
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T18H410--24SR6
RF Device Data
Freescale Semiconductor, Inc.
7
Table 9. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 0.8 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1805
1.32 – j3.98
1.55 + j4.16
1840
1.84 – j4.30
1.90 + j4.53
1880
2.67 – j4.46
2.83 + j4.90
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1.38 – j3.61
15.9
54.9
312
57.4
–33
1.22 – j3.80
15.6
55.1
321
54.6
–32
1.40 – j3.92
16.0
55.0
315
56.4
–33
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
1.32 – j3.98
1.59 + j4.36
1.35 – j3.73
13.7
55.7
370
59.3
–40
1840
1.84 – j4.30
2.01 + j4.79
1.19 – j3.91
13.4
55.8
380
57.1
–39
1880
2.67 – j4.46
3.20 + j5.21
1.38 – j4.21
13.6
55.7
372
57.3
–39
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 10. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, VGSB = 0.8 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
1.32 – j3.98
1.39 + j4.15
3.59 – j2.93
17.2
53.0
201
69.3
–41
1840
1.84 – j4.30
1.67 + j4.51
3.49 – j2.75
17.2
53.1
204
69.4
–40
1880
2.67 – j4.46
2.45 + j4.92
3.12 – j2.36
17.3
53.0
199
68.8
–41
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
3.30 – j3.71
14.8
53.9
248
66.3
–47
1.91 + j4.81
2.68 – j3.69
14.8
54.7
292
66.2
–45
2.96 + j5.27
2.97 – j3.26
15.0
54.3
269
66.9
–47
f
(MHz)
Zsource
()
Zin
()
1805
1.32 – j3.98
1.52 + j4.38
1840
1.84 – j4.30
1880
2.67 – j4.46
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T18H410--24SR6
8
RF Device Data
Freescale Semiconductor, Inc.
P1dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 1840 MHz
–1
–1
–1.5
E
E
–2.5
50
50.5
–3
–3.5
–2
49.5
51.5
P
–4
52.5
IMAGINARY ()
IMAGINARY ()
–2
–1.5
48.5
49
51
52
1
1.5
2
REAL ()
3
2.5
64
60
56
–5
0.5
3.5
–1
22.5
22
–3
21.5
21
P
P
20.5
–4
19.5
–4.5
1.5
2
REAL ()
3
3.5
–10
–16
–22
–24
–2.5
–20
–12
–14
EE
–18
–3
–3.5
P
P
–4.5
2.5
58
–4
20
19
1
2.5
--10
–2
IMAGINARY ()
EE
2
REAL ()
–1.5
–2
–2.5
1.5
1
62
Figure 9. P1dB Load Pull Efficiency Contours (%)
23
–1.5
IMAGINARY ()
66
P
P
–4.5
–1
–5
0.5
68
–3.5
Figure 8. P1dB Load Pull Output Power Contours (dBm)
–3.5
70
–3
–4
–4.5
–5
0.5
E
E
–2.5
3
3.5
Figure 10. P1dB Load Pull Gain Contours (dB)
NOTE:
–5
0.5
–10
1
–10
1.5
2
REAL ()
2.5
3
3.5
Figure 11. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
A2T18H410--24SR6
RF Device Data
Freescale Semiconductor, Inc.
9
P3dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 1840 MHz
–1
–1
–1.5
–1.5
49.5
50.5
E
E
–2.5
51
–3
–3.5
–2
50
IMAGINARY ()
IMAGINARY ()
–2
51.5
PP
52.5
53
–4
52
1.5
1
2
REAL ()
3
2.5
3.5
PP
64
–1.5
20.5
20
–3
19.5
PP
–4
19
18.5
16.5
–4.5
1
17
1.5
17.5
1.5
2
REAL ()
2.5
–24
–30 –28 –26
3.5
–18
–22
EE
–2.5
–3
–16
–3.5
P
P
–4
18
3
–20
–2
IMAGINARY ()
E
E
58
56
1
62
60
Figure 13. P3dB Load Pull Efficiency Contours (%)
–1.5
–2
IMAGINARY ()
66
–5
0.5
–1
–5
0.5
68
–3.5
–1
–2.5
70
72
–3
–4.5
Figure 12. P3dB Load Pull Output Power Contours (dBm)
–3.5
EE
–2.5
–4
–4.5
–5
0.5
66
–14
–4.5
2
REAL ()
2.5
3
3.5
Figure 14. P3dB Load Pull Gain Contours (dB)
NOTE:
–5
0.5
1
1.5
2
REAL ()
2.5
3
3.5
Figure 15. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
A2T18H410--24SR6
10
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL PEAKING LOAD PULL CONTOURS — 1840 MHz
0
0
62
51
51.5
–2
52
E
E
–3
54.5
PP 55
–4
–5
–1
IMAGINARY ()
IMAGINARY ()
–1
1
1.5
2
2.5
3
3.5
4
REAL ()
4.5
5
5.5
–5
6
66
64
PP
1.5
60
58
54
1
62
56
2
58
2.5
56
3
3.5
4
REAL ()
4.5
5
5.5
6
Figure 17. P1dB Load Pull Efficiency Contours (%)
0
0
–1
–1
18
–2
17.5
E
E
–3
IMAGINARY ()
IMAGINARY ()
–3
–4
Figure 16. P1dB Load Pull Output Power Contours (dBm)
17
16.5
PP
–4
1
–30
–3
1.5
2
2.5
3
3.5
4
REAL ()
4.5
5
5.5
6
Figure 18. P1dB Load Pull Gain Contours (dB)
NOTE:
–5
–42
EE
–40
P
16
16
15.5
–44
–28
–2
–4
15
–5
68
EE
53
53.5
54
52.5
–2
–38
1
1.5
–36
–34
–32
2
2.5
3
3.5
4
REAL ()
4.5
5
5.5
6
Figure 19. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
A2T18H410--24SR6
RF Device Data
Freescale Semiconductor, Inc.
11
P3dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 1840 MHz
–2
52
–2
52.5
–2.5
IMAGINARY ()
–3.5
EE
P
P
–4
55.5
–4.5
53
52
52.5
–3
IMAGINARY ()
53.5
–3
54
55 54.5
–5.5
–6
–6
4
REAL ()
5
6
7
–2
58
56
54
50 52
1
3
2
52
4
REAL ()
5
6
7
–2
15.5
–2.5
IMAGINARY ()
E
E
P
P
–4
14.5
–4.5
14
–5
–5.5
1
12.5
13.5
12
13
2
–50
–3
15
–3.5
–50
–2.5
–3
IMAGINARY ()
60
Figure 21. P3dB Load Pull Efficiency Contours (%)
Figure 20. P3dB Load Pull Output Power Contours (dBm)
–6
62
64
–4.5
–5.5
3
E
E
P
P
–4
–5
2
66
–3.5
–5
1
50
–2.5
–48
–3.5
P
P
–4
–4.5
–42
–36
–5.5
4
REAL ()
5
6
7
Figure 22. P3dB Load Pull Gain Contours (dB)
NOTE:
–46
–44
–5
3
E
E
–6
–40
–38
–34
1
2
3
4
REAL ()
5
6
7
Figure 23. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
A2T18H410--24SR6
12
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2T18H410--24SR6
RF Device Data
Freescale Semiconductor, Inc.
13
A2T18H410--24SR6
14
RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
 AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
 EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
 Electromigration MTTF Calculator
 RF High Power Model
 .s2p File
Development Tools
 Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.freescale.com/rf
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
May 2015
Description
 Initial Release of Data Sheet
A2T18H410--24SR6
RF Device Data
Freescale Semiconductor, Inc.
15
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A2T18H410--24SR6
Document Number: A2T18H410--24S
Rev. 0, 5/2015
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RF Device Data
Freescale Semiconductor, Inc.
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