Data Sheet

Document Number: A2T07H310--24S
Rev. 0, 6/2014
Freescale Semiconductor
Technical Data
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 47 W asymmetrical Doherty RF power LDMOS transistor is designed for
cellular base station applications covering the frequency range of 716 to
960 MHz.
870 MHz
• Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 700 mA, VGSB = 0.7 Vdc, Pout = 47 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
ηD
(%)
Output PAR
(dB)
851 MHz
18.9
50.5
7.7
–29.8
865 MHz
18.9
51.6
7.7
–30.1
880 MHz
18.6
51.3
7.7
–30.9
A2T07H310--24SR6
716–960 MHz, 47 W AVG., 28 V
AIRFAST RF POWER LDMOS
TRANSISTOR
ACPR
(dBc)
800 MHz
• Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 700 mA, VGSB = 0.7 Vdc, Pout = 47 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
ηD
(%)
Output PAR
(dB)
790 MHz
19.5
50.7
7.7
–30.2
806 MHz
19.3
50.8
7.7
–31.2
822 MHz
18.9
50.5
7.7
–32.3
ACPR
(dBc)
Features
• Advanced High Performance In--Package Doherty
• Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
• Designed for Digital Predistortion Error Correction Systems
• In Tape and Reel. R6 Suffix = 150 Units, 56 mm Tape Width, 13--inch Reel.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
NI--1230S--4L2L
6 VBWA(1)
Carrier
RFinA/VGSA 1
5 RFoutA/VDSA
RFinB/VGSB 2
4 RFoutB/VDSB
Peaking
3 VBWB(1)
(Top View)
Figure 1. Pin Connections
1. Device cannot operate with the VDD current
supplied through pin 3 and pin 6.
A2T07H310--24SR6
1
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain--Source Voltage
Rating
VDSS
–0.5, +70
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
°C
Case Operating Temperature Range
TC
–40 to +150
°C
TJ
–40 to +225
°C
CW
199
1.8
W
W/°C
Operating Junction Temperature Range
(1,2)
CW Operation @ TC = 25°C
Derate above 25°C
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 71°C, 47 W W--CDMA, 28 Vdc, IDQA = 700 mA, VGSB = 0.7 Vdc, 865 MHz
Symbol
Value (2,3)
Unit
RθJC
0.36
°C/W
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
2
Machine Model (per EIA/JESD22--A115)
B
Charge Device Model (per JESD22--C101)
IV
Table 4. Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 70 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
μAdc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
μAdc
Gate--Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
μAdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 174 μAdc)
VGS(th)
1.0
1.5
2.0
Vdc
Gate Quiescent Voltage
(VDD = 28 Vdc, IDA = 700 mAdc, Measured in Functional Test)
VGS(Q)
1.5
2.0
2.5
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 1.74 Adc)
VDS(on)
0.1
0.2
0.3
Vdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 224 μAdc)
VGS(th)
1.0
1.5
2.0
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 2.24 Adc)
VDS(on)
0.05
0.1
0.3
Vdc
Characteristic
Off Characteristics
(4)
On Characteristics -- Side A (4) (Carrier)
On Characteristics -- Side B (4) (Peaking)
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf.
Select Documentation/Application Notes -- AN1955.
4. Each side of device measured separately.
(continued)
A2T07H310--24SR6
2
RF Device Data
Freescale Semiconductor, Inc.
Table 4. Electrical Characteristics (TA = 25°C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests (1,2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 700 mA, VGSB = 0.7 Vdc, Pout = 47 W Avg.,
f = 880 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in
3.84 MHz Channel Bandwidth @ ±5 MHz Offset.
Power Gain
Gps
17.7
18.6
20.7
dB
Drain Efficiency
ηD
48.0
51.3
—
%
PAR
7.2
7.7
—
dB
ACPR
—
–30.9
–26.9
dBc
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Load Mismatch (2) (In Freescale Doherty Test Fixture, 50 ohm system) IDQA = 700 mA, VGSB = 0.7 Vdc, f = 865 MHz
VSWR 10:1 at 32 Vdc, 316 W CW (4) Output Power
(3 dB Input Overdrive from 126 W CW Rated Power)
No Device Degradation
Typical Performance (2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 700 mA, VGSB = 0.7 Vdc,
851–880 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
126
—
W
Pout @ 3 dB Compression Point (3)
P3dB
—
330
—
W
Φ
—
–21
—
°
VBWres
—
180
—
MHz
Gain Flatness in 29 MHz Bandwidth @ Pout = 47 W Avg.
GF
—
0.4
—
dB
Gain Variation over Temperature
(–30°C to +85°C)
∆G
—
0.01
—
dB/°C
∆P1dB
—
0.2
—
dB/°C
AM/PM
(Maximum value measured at the P3dB compression point across
the 851–880 MHz frequency range)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30°C to +85°C) (4)
1. Part internally matched both on input and output.
2. Measurement made with device in an asymmetrical Doherty configuration.
3. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
4. Exceeds recommended operating conditions. See CW operation data in Maximum Ratings table.
A2T07H310--24SR6
RF Device Data
Freescale Semiconductor, Inc.
3
VGGA
VDDA
C18
C17
D58864
C33
C9
--
C29 C30
C10
C7
C19
C1 C3
C5
C11
Z1
C14
R1
CUT OUT AREA
R2
C23
C21
C
C24
C22
C25
C26
C28
P
C2
C6
C4
C27
R3
C8
A2T07H310--24S
Rev. 3
C13
C12
C31
C32
-C20
C15
VGGB
C34
VDDB
C16
Figure 2. A2T07H310--24SR6 Test Circuit Component Layout — 851–880 MHz
Table 5. A2T07H310--24SR6 Test Circuit Component Designations and Values — 851–880 MHz
Part
Description
Part Number
Manufacturer
C1, C2, C7, C8, C19, C20,
C23, C28
43 pF Chip Capacitors
ATC100B430JT500XT
ATC
C3, C4, C5, C6, C21, C22,
C25
6.8 pF Chip Capacitors
ATC100B6R8CT500XT
ATC
C9, C10, C12, C13
10 μF Chip Capacitors
GRM31CR61H106KA12
Muruta
C11, C14, C26
5.6 pF Chip Capacitors
ATC100B5R6CT500XT
ATC
C15, C16, C17, C18, C29,
C30, C31, C32
10 μF Chip Capacitors
C5750X7S2A106M230KB
TDK
C24
2.7 pF Chip Capacitor
ATC100B2R7BT500XT
ATC
C27
4.7 pF Chip Capacitor
ATC100B4R7CT500XT
ATC
C33, C34
330 μF Electrolytic Capacitors
MCRH63V337M13X21–RH
Multicomp
R1
50 Ω, 10 W Termination
81A7031–50–5F
Florida RF Labs
R2, R3
2.2 Ω, 1/4 W Chip Resistors
CRCW12062R20JNEA
Vishay
Z1
800–1000 MHz Band, 90°, 3 dB Hybrid Coupler
X3C09P1–03S
Anaren
PCB
Rogers RO4350B, 0.020″, εr = 3.66
D58864
MTL
A2T07H310--24SR6
4
RF Device Data
Freescale Semiconductor, Inc.
52
22
50
VDD = 28 Vdc, Pout = 47 W (Avg.)
IDQA = 700 mA, VGSB = 0.7 Vdc
Single--Carrier W--CDMA
20
19
48
ηD
46
44
18
17
Gps
PARC
16
15
14
13
800
840
860
880
--2
--29
--2.5
--30
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
820
--28
--31
ACPR
--32
ACPR (dBc)
Gps, POWER GAIN (dB)
21
--3
--3.5
--4
--33
900
920
940
PARC (dB)
23
ηD, DRAIN
EFFICIENCY (%)
TYPICAL CHARACTERISTICS — 851–880 MHz
--4.5
960
f, FREQUENCY (MHz)
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 47 Watts Avg.
--10
VDD = 28 Vdc, Pout = 20 W (PEP), IDQA = 700 mA
VGSB = 0.7 Vdc, Two--Tone Measurements
(f1 + f2)/2 = Center Frequency of 865 MHz
--20
IM3--U
--30
IM3--L
IM5--L
--40
IM7--L
--50
--60
IM5--U
IM7--U
1
10
100
200
TWO--TONE SPACING (MHz)
21
0
20
19
18
17
16
ηD
PARC
--1
--1 dB = 18 W
50
--25
40
--2 dB = 40 W
30
--3 dB = 70 W
--3
20
VDD = 28 Vdc, IDQA = 700 mA, VGSB = 0.7 Vdc
f = 865 MHz, Single--Carrier W--CDMA, 3.84 MHz
Channel Bandwidth, Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
--4
--5
--20
ACPR
Gps
--2
60
0
15
30
45
60
75
--30
--35
ACPR (dBc)
1
ηD, DRAIN EFFICIENCY (%)
22
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
--40
10
--45
0
--50
90
Pout, OUTPUT POWER (WATTS)
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T07H310--24SR6
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS — 851–880 MHz
Gps
18
VDD = 28 Vdc, IDQA = 700 mA
VGSB = 0.7 Vdc, Single--Carrier
W--CDMA
45
ACPR
865 MHz
851 MHz
14
12
851 MHz 55
880 MHz
35
25
880 MHz
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
ηD
5
400
10
1
10
15
100
0
--10
--20
--30
--40
ACPR (dBc)
851 MHz
880 MHz
20
16
65
865 MHz
865 MHz
ηD, DRAIN EFFICIENCY (%)
Gps, POWER GAIN (dB)
22
--50
--60
Pout, OUTPUT POWER (WATTS) AVG.
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
20
18
Gain
GAIN (dB)
16
14
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 700 mA
VGSB = 0.7 Vdc
12
10
8
700
750
800
850
900
950
1000
f, FREQUENCY (MHz)
Figure 7. Broadband Frequency Response
A2T07H310--24SR6
6
RF Device Data
Freescale Semiconductor, Inc.
Table 6. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 661 mA, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
851
1.12 – j2.70
1.13 + j2.77
865
1.16 – j2.79
1.21 + j2.89
880
1.16 – j2.89
1.30 + j3.03
Zload
(Ω)
(1)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
1.30 – j2.73
19.7
53.1
204
56.2
–8
1.24 – j2.80
19.5
53.2
210
56.8
–8
1.19 – j2.87
19.3
53.3
215
57.4
–8
Max Output Power
P3dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
Zload (2)
(Ω)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
851
1.12 – j2.70
1.12 + j2.86
1.29 – j3.01
17.5
54.1
258
59.8
–11
865
1.16 – j2.79
1.20 + j2.98
1.22 – j3.06
17.3
54.2
263
59.2
–11
880
1.16 – j2.89
1.29 + j3.11
1.12 – j3.12
16.9
54.3
268
58.6
–12
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 7. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, IDQA = 661 mA, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
3.72 – j0.98
23.1
50.5
113
73.7
–16
1.16 + j2.91
3.74 – j0.62
23.2
50.1
101
74.2
–19
1.24 + j3.02
3.23 – j1.04
22.8
50.4
110
72.8
–18
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
851
1.12 – j2.70
1.08 + j2.78
865
1.16 – j2.79
880
1.16 – j2.89
Zload
(Ω)
(1)
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
851
1.12 – j2.70
1.09 + j2.86
865
1.16 – j2.79
1.17 + j2.97
880
1.16 – j2.89
1.25 + j3.10
Zload
(Ω)
(2)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
4.40 – j1.30
21.3
50.9
124
75.8
–23
3.50 – j1.76
20.7
51.7
147
76.1
–21
3.36 – j1.39
20.7
51.3
135
75.8
–24
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T07H310--24SR6
RF Device Data
Freescale Semiconductor, Inc.
7
Table 8. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 0.7 Vdc, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
851
1.12 – j2.70
1.29 + j2.85
865
1.16 – j2.79
1.38 + j2.99
880
1.16 – j2.89
1.48 + j3.15
Zload
(Ω)
(1)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
0.92 – j3.03
15.1
53.7
237
53.2
–15
0.94 – j3.06
15.2
53.9
245
55.4
–15
0.88 – j3.16
14.9
54.0
251
55.0
–15
Max Output Power
P3dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
Zload (2)
(Ω)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
851
1.12 – j2.70
1.28 + j2.95
0.92 – j3.10
13.0
54.8
302
56.8
–19
865
1.16 – j2.79
1.38 + j3.10
0.90 – j3.25
12.8
54.9
310
57.4
–18
880
1.16 – j2.89
1.48 + j3.26
0.88 – j3.26
12.8
55.1
320
58.9
–19
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 9. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, VGSB = 0.7 Vdc, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
2.88 – j1.01
16.7
50.7
117
76.2
–26
1.28 + j2.87
2.60 – j1.20
16.6
50.8
121
76.0
–25
1.35 + j3.01
2.49 – j0.76
16.2
50.0
100
76.0
–29
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
851
1.12 – j2.70
1.19 + j2.73
865
1.16 – j2.79
880
1.16 – j2.89
Zload
(Ω)
(1)
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
851
1.12 – j2.70
1.20 + j2.84
865
1.16 – j2.79
1.30 + j3.01
880
1.16 – j2.89
1.41 + j3.18
Zload
(Ω)
(2)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
3.23 – j1.20
14.6
51.3
134
77.1
–32
2.60 – j1.80
14.6
52.1
162
76.6
–29
2.28 – j2.21
14.4
52.6
183
77.0
–28
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T07H310--24SR6
8
RF Device Data
Freescale Semiconductor, Inc.
2
2
1
1
0
IMAGINARY (Ω)
IMAGINARY (Ω)
P1dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 865 MHz
E
--1
--2
52
P 53
--3
52.5
0
1
2
49
4
3
72
70
--2
68
P
5
--5
7
6
66
64
--4
50.5
--5
E
--1
--3
49.5
50
51
51.5
--4
0
60
0
1
2
4
3
62
58
5
6
7
REAL (Ω)
Figure 8. P1dB Load Pull Output Power Contours (dBm)
Figure 9. P1dB Load Pull Efficiency Contours (%)
2
2
1
1
24
0
E
--1
23.5
--2
23
P
--3
1
--20
0
--16
--2
--14
P
2
3
4
5
6
7
--5
--12
--10
--8
--4
21.5
--18
E
--1
22.5
22
21
20.5
0
--22
--3
20
--4
--5
IMAGINARY (Ω)
IMAGINARY (Ω)
REAL (Ω)
--6
0
1
2
3
4
5
6
REAL (Ω)
REAL (Ω)
Figure 10. P1dB Load Pull Gain Contours (dB)
Figure 11. P1dB Load Pull AM/PM Contours (°)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
7
Gain
Drain Efficiency
Linearity
Output Power
A2T07H310--24SR6
RF Device Data
Freescale Semiconductor, Inc.
9
2
2
1
1
0
0
IMAGINARY (Ω)
IMAGINARY (Ω)
P3dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 865 MHz
--1
50
E
--2
--3
P
53.5
--4
50.5
53
54
52
52.5
--1
P
66
--4
51.5
--5
0
1
2
4
3
5
--5
7
6
70
68
--3
51
72
74
E
--2
64
62
60
0
1
2
4
3
5
6
7
REAL (Ω)
Figure 13. P3dB Load Pull Output Power Contours (dBm)
Figure 14. P3dB Load Pull Efficiency Contours (%)
2
2
1
1
0
0
--1
21
--3
17.5
1
20
19
18
0
--26
3
4
5
6
7
--5
--22
E
--2
--20
--18
P
--12
--10
0
1
--16
--14
--4
19.5
18.5
2
20.5
--24
--1
--3
P
--4
--5
21.5
E
--2
IMAGINARY (Ω)
IMAGINARY (Ω)
REAL (Ω)
2
3
4
5
6
REAL (Ω)
REAL (Ω)
Figure 15. P3dB Load Pull Gain Contours (dB)
Figure 12. P3dB Load Pull AM/PM Contours (°)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
7
Gain
Drain Efficiency
Linearity
Output Power
A2T07H310--24SR6
10
RF Device Data
Freescale Semiconductor, Inc.
1
1
0
0
--1
E
50.5
--2
--3
P
1
0
50
51
53.5
52 51.5
53 52.5
--4
--5
IMAGINARY (Ω)
IMAGINARY (Ω)
P1dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 865 MHz
2
--1
E
74
--2
70
72
4
5
--5
6
64
62
--3
P
60
--4
3
66
68
0
1
2
3
4
5
6
REAL (Ω)
REAL (Ω)
Figure 16. P1dB Load Pull Output Power Contours (dBm)
Figure 17. P1dB Load Pull Efficiency Contours (%)
1
1
0
15.5
--1
IMAGINARY (Ω)
IMAGINARY (Ω)
0
E
--2
16.5
--3
P
--5
15.5
14
--4
13
0
16
--1
E
15
--20
--3
3
4
5
--18
P
--16
--14
--12
15
2
--24
--22
--2
--4
13.5 14.5
1
--28
--26
6
--5
0
1
2
3
4
5
REAL (Ω)
REAL (Ω)
Figure 18. P1dB Load Pull Gain Contours (dB)
Figure 19. P1dB Load Pull AM/PM Contours (°)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
6
Gain
Drain Efficiency
Linearity
Output Power
A2T07H310--24SR6
RF Device Data
Freescale Semiconductor, Inc.
11
1
1
0
0
--1
--1
E
--2
P 54.5
53
53.5
--4
1
0
51
52.5 52 51.5
54
--3
--5
IMAGINARY (Ω)
IMAGINARY (Ω)
P3dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 865 MHz
76
74
E
--2
66 64
70 68
72
--3
62
P
60
--4
2
3
5
4
--5
6
0
1
2
3
5
4
6
REAL (Ω)
REAL (Ω)
Figure 20. P3dB Load Pull Output Power Contours (dBm)
Figure 21. P3dB Load Pull Efficiency Contours (%)
IMAGINARY (Ω)
0
1
11.5
13
12.5
11
13.5
14
12
13.5
14.5
--1
--3
P
13.5
--4
--5
1
2
3
4
--1
--26
E
--2
--24
--3
--22
--20
--18
P
--4
10.5
0
5
--28
--30
E
--2
--32
--34
0
IMAGINARY (Ω)
1
6
--5
0
1
2
3
4
5
REAL (Ω)
REAL (Ω)
Figure 22. P3dB Load Pull Gain Contours (dB)
Figure 23. P3dB Load Pull AM/PM Contours (°)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
6
Gain
Drain Efficiency
Linearity
Output Power
A2T07H310--24SR6
12
RF Device Data
Freescale Semiconductor, Inc.
790–822 MHz CHARACTERISTICS
VGGA
VDDA
C18
C17
--
J3
C33
C9
C10
C29 C19
C7
C30
R2
C1 C3
C5
C11
Z1
C14
R1
J2
C2
C4
C21
CUT OUT AREA
J1
C22
C23
C24
C
C26
C25
C28
P
C6
C27
R3
J4
C8
C13
C12
C31 C32
C20
--
A2T07H310--24S
790–821 MHz
Rev. 1
D59215
C15
VGGB
C34
VDDB
C16
Figure 24. A2T07H310--24SR6 Test Circuit Component Layout — 790–822 MHz
Table 10. A2T07H310--24SR6 Test Circuit Component Designations and Values — 790–822 MHz
Part
Description
Part Number
Manufacturer
C1, C2, C7, C8, C19, C20,
C23, C28
43 pF Chip Capacitors
ATC100B430JT500XT
ATC
C3, C4, C5, C6, C21, C22,
C25
9.1 pF Chip Capacitors
ATC100B9R1CT500XT
ATC
C9, C10, C12, C13
10 μF Chip Capacitors
GRM31CR61H106KA12
Muruta
C11, C14
7.5 pF Chip Capacitors
ATC100B7R5CT500XT
ATC
C15, C16, C17, C18, C29,
C30, C31, C32
10 μF Chip Capacitors
C5750X7S2A106M230KB
TDK
C24
2.7 pF Chip Capacitor
ATC100B2R7BT500XT
ATC
C26
6.8 pF Chip Capacitor
ATC100B6R8CT500XT
ATC
C27
4.7 pF Chip Capacitor
ATC100B4R7CT500XT
ATC
C33, C34
330 μF Electrolytic Capacitors
MCRH63V337M13X21–RH
Multicomp
J1, J2, J3, J4
Copper Foil
R1
50 Ω, 10 W Termination
81A7031–50–5F
Florida RF Labs
R2, R3
2.2 Ω, 1/4 W Chip Resistors
CRCW12062R20JNEA
Vishay
Z1
800–1000 MHz Band, 90°, 3 dB Hybrid Coupler
X3C09P1–03S
Anaren
PCB
Rogers RO4350B, 0.020″, εr = 3.66
D59215
MTL
A2T07H310--24SR6
RF Device Data
Freescale Semiconductor, Inc.
13
Gps, POWER GAIN (dB)
19
18
Single--Carrier W--CDMA
17 3.84 MHz Channel Bandwidth
16 Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
15
14
40
ηD
35
Gps
12
780
800
820
840
860
--25
--2
--35
PARC
11
760
--1
--30
ACPR
13
--20
880
900
--40
920
940
--45
960
--3
--4
--5
PARC (dB)
55
VDD = 28 Vdc, Pout = 47 W (Avg.)
IDQA = 700 mA, VGSB = 0.7 Vdc 50
45
20
ACPR (dBc)
21
ηD, DRAIN
EFFICIENCY (%)
TYPICAL CHARACTERISTICS — 790–822 MHz
--6
f, FREQUENCY (MHz)
Figure 25. Single--Carrier Output Peak--to--Average Ratio
Compression (PARC) Broadband Performance @ Pout = 47 Watts Avg.
Gps, POWER GAIN (dB)
21
20
19
18
ACPR
17
15
ηD
16
1
10
100
5
200
--10
--20
--30
--40
--50
ACPR (dBc)
65
822 MHz
VDD = 28 Vdc, IDQA = 700 mA
806 MHz
VGSB = 0.7 Vdc, Single--Carrier
55
790 MHz
W--CDMA, 3.84 MHz Channel
790 MHz
Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
45
806 MHz
822 MHz
Gps
35
790 MHz
806 MHz
25
822 MHz
ηD, DRAIN EFFICIENCY (%)
22
--60
--70
Pout, OUTPUT POWER (WATTS) AVG.
Figure 26. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
22
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 700 mA
VGSB = 0.7 Vdc
20
GAIN (dB)
18
Gain
16
14
12
10
650
700
750
800
850
900
950
f, FREQUENCY (MHz)
Figure 27. Broadband Frequency Response
A2T07H310--24SR6
14
RF Device Data
Freescale Semiconductor, Inc.
Table 11. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 680 mA, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
790
0.96 – j2.26
0.93 + j2.40
806
0.95 – j2.37
0.97 + j2.49
822
1.07 – j2.57
1.02 + j2.60
Zload
(Ω)
(1)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
1.46 – j2.24
20.4
52.8
192
54.3
–9
1.43 – j2.35
20.2
52.3
171
50.8
–9
1.42 – j2.59
19.9
52.3
168
50.3
–8
Max Output Power
P3dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
Zload (2)
(Ω)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
790
0.96 – j2.26
0.90 + j2.48
1.32 – j2.47
18.0
53.8
240
55.5
–12
806
0.95 – j2.37
0.95 + j2.57
1.30 – j2.74
17.7
53.4
218
52.6
–13
822
1.07 – j2.57
1.00 + j2.68
1.36 – j2.90
17.7
53.4
220
53.9
–11
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 12. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, IDQA = 680 mA, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
4.00 – j0.94
23.4
50.6
114
67.8
–17
0.93 + j2.49
3.65 – j1.48
23.0
50.5
111
63.5
–14
0.99 + j2.61
4.49 – j1.29
23.2
49.9
99
65.5
–13
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
790
0.96 – j2.26
0.88 + j2.41
806
0.95 – j2.37
822
1.07 – j2.57
Zload
(Ω)
(1)
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
790
0.96 – j2.26
0.87 + j2.49
806
0.95 – j2.37
0.92 + j2.57
822
1.07 – j2.57
0.99 + j2.70
Zload
(Ω)
(2)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
4.15 – j1.31
21.4
51.3
135
70.7
–23
3.82 – j1.72
21.0
51.3
136
67.1
–20
4.56 – j1.89
21.2
51.0
127
69.4
–18
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T07H310--24SR6
RF Device Data
Freescale Semiconductor, Inc.
15
Table 13. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 0.7 Vdc, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Output Power
P1dB
Zload
(Ω)
(1)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
1.11 – j2.38
15.6
53.4
218
54.0
–16
1.15 – j2.52
15.2
53.1
202
52.6
–16
14.8
53.1
203
50.5
–13
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
790
1.21 – j2.23
1.06 + j2.38
806
1.18 – j2.27
1.11 + j2.50
822
1.32 – j2.41
1.17 + j2.66
1.06 – j2.79
Max Output Power
P3dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
Zload (2)
(Ω)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
790
1.21 – j2.23
1.05 + j2.48
1.04 – j2.59
13.3
54.4
275
55.2
–19
806
1.18 – j2.27
1.10 + j2.61
1.00 – j2.78
12.7
54.2
262
52.5
–19
822
1.32 – j2.41
1.16 + j2.76
1.01 – j2.97
12.5
54.2
263
52.5
–16
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 14. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, VGSB = 0.7 Vdc, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
3.32 – j0.43
17.0
50.5
113
73.5
–28
1.04 + j2.41
3.04 – j0.87
16.6
50.6
114
69.7
–25
1.10 + j2.55
3.34 – j1.03
16.4
50.5
113
70.8
–21
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
790
1.21 – j2.23
0.98 + j2.27
806
1.18 – j2.27
822
1.32 – j2.41
Zload
(Ω)
(1)
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
(Ω)
Zin
(Ω)
790
1.21 – j2.23
0.99 + j2.39
806
1.18 – j2.27
1.05 + j2.52
822
1.32 – j2.41
1.10 + j2.67
Zload
(Ω)
(2)
Gain (dB)
(dBm)
(W)
ηD
(%)
AM/PM
(°)
3.41 – j0.81
15.0
51.3
135
73.9
–32
3.05 – j1.36
14.6
51.7
147
70.9
–29
3.46 – j1.34
14.3
51.4
138
72.2
–26
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T07H310--24SR6
16
RF Device Data
Freescale Semiconductor, Inc.
P1dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 806 MHz
1
1
49
0
--1
--1
IMAGINARY (Ω)
IMAGINARY (Ω)
48.5
0
E
--2
P
--3
51.5
52
50
50.5
51
62
P
--3
49
49.5
--4
E
--2
60
48
--4
48.5
--5
0
1
2
3
5
4
50 52
--5
7
6
1
0
2
58
56
54
3
4
5
6
7
REAL (Ω)
Figure 28. P1dB Load Pull Output Power Contours (dBm)
Figure 29. P1dB Load Pull Efficiency Contours (%)
1
1
0
0
--1
--1
IMAGINARY (Ω)
IMAGINARY (Ω)
REAL (Ω)
E
--2
P
24
--3
20.5 21.5
--4
20
--5
0
1
22
3
4
5
--16
E
--2
P
--14
--12
--3
--4
21
2
--18
--10
23.5
23
22.5
--20
6
7
--5
--4
0
--6
1
--8
2
3
4
5
6
REAL (Ω)
REAL (Ω)
Figure 30. P1dB Load Pull Gain Contours (dB)
Figure 31. P1dB Load Pull AM/PM Contours (°)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
7
Gain
Drain Efficiency
Linearity
Output Power
A2T07H310--24SR6
RF Device Data
Freescale Semiconductor, Inc.
17
P3dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 806 MHz
1
1
49.5
50
0
50.5
51
--1
E
--2
P
--3
52.5
53
--4
--5
IMAGINARY (Ω)
IMAGINARY (Ω)
0
0
1
2
--1
66
E
--2
64
P
--3
51.5
52
62
--4
3
5
4
--5
7
6
56
52 54
0
1
2
60
58
3
4
5
6
7
REAL (Ω)
Figure 32. P3dB Load Pull Output Power Contours (dBm)
Figure 33. P3dB Load Pull Efficiency Contours (%)
1
1
0
0
--1
--1
E
--2
22
P
--3
18.5 19.5 20 20.5
--4
18
--5
IMAGINARY (Ω)
IMAGINARY (Ω)
REAL (Ω)
0
1
21
3
4
5
--22
E
--2
--20
--18
P
--3
--14
21.5
--4
19
2
--24
6
7
--5
--8
0
1
--12
--10
2
--16
3
4
5
6
REAL (Ω)
REAL (Ω)
Figure 34. P3dB Load Pull Gain Contours (dB)
Figure 35. P3dB Load Pull AM/PM Contours (°)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
7
Gain
Drain Efficiency
Linearity
Output Power
A2T07H310--24SR6
18
RF Device Data
Freescale Semiconductor, Inc.
1
1
0
0
49
E
--1
IMAGINARY (Ω)
IMAGINARY (Ω)
P1dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 806 MHz
--2
P
--3
49.5
52 51.5 51
52.5
68
64
P
--3
0
1
2
3
4
5
--5
6
62
60
58
--4
50.5
66
--2
50
50.5
--4
--5
E
--1
56
54
0
1
2
3
5
4
6
REAL (Ω)
REAL (Ω)
Figure 36. P1dB Load Pull Output Power Contours (dBm)
Figure 37. P1dB Load Pull Efficiency Contours (%)
1
1
0
16.5
16
E
--1
--2
P
--3
--22
--2
--5
3
4
5
6
--18
--3
--5
2
--20
P
--4
1
E
--1
--4
0
--30
--28
--26
--24
16
IMAGINARY (Ω)
IMAGINARY (Ω)
12.5 13.5 14.5
15.5
15
0
13 14
--16
--14
0
1
2
3
4
5
REAL (Ω)
REAL (Ω)
Figure 38. P1dB Load Pull Gain Contours (dB)
Figure 39. P1dB Load Pull AM/PM Contours (°)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
6
Gain
Drain Efficiency
Linearity
Output Power
A2T07H310--24SR6
RF Device Data
Freescale Semiconductor, Inc.
19
1
1
0
0
--1
E
50.5
50
--2
53 52.5 52
P 54 53.5
--3
51.5
IMAGINARY (Ω)
IMAGINARY (Ω)
P3dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 806 MHz
51
--1
E
--4
--5
--5
0
1
2
3
4
5
6
66
64
P
--3
--4
68
70
--2
62
54
0
1
2
3
60
58
56
5
4
6
REAL (Ω)
REAL (Ω)
Figure 40. P3dB Load Pull Output Power Contours (dBm)
Figure 41. P3dB Load Pull Efficiency Contours (%)
1
14
14.5
14
--30
--1
E
--2
P
--3
--4
--5
--32
0
IMAGINARY (Ω)
IMAGINARY (Ω)
0
1
10.5 11.5 12.5
11 12 13 13.5
E
--26
1
2
3
4
5
6
--24
--2
--22
P
--3
--20
--18
--4
0
--28
--1
--5
--16
0
1
2
3
4
5
REAL (Ω)
REAL (Ω)
Figure 42. P3dB Load Pull Gain Contours (dB)
Figure 43. P3dB Load Pull AM/PM Contours (°)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
6
Gain
Drain Efficiency
Linearity
Output Power
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Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
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Freescale Semiconductor, Inc.
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RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
• AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
• EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
• Electromigration MTTF Calculator
• RF High Power Model
• .s2p File
Development Tools
• Printed Circuit Boards
For Software and Tools, do a Part Number search at http://www.freescale.com, and select the “Part Number” link. Go to the
Software & Tools tab on the part’s Product Summary page to download the respective tool.
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
June 2014
Description
• Initial Release of Data Sheet
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Freescale Semiconductor, Inc.
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A2T07H310--24SR6
Document Number: A2T07H310--24S
Rev.
24 0, 6/2014
RF Device Data
Freescale Semiconductor, Inc.
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