Document No. 001-58834 Rev *D
ECN #4257074
Cypress Semiconductor
Product Qualification Plan
QTP# 090604
January 2014
S8 K2 Product Qualification
Non-Volatile SRAM Product Family Qualification
Cypress, CMI (Fab 4)
CY14B101LA (x8)
CY14B101NA (x16)
3V 1M Parallel Non-RTC nvSRAM Device
CY14B101KA (x8)
CY14B101MA (x16)
3V 1M Parallel RTC nvSRAM Device
CY14E101LA (x8)
5V 1M Parallel Non-RTC nvSRAM Device
CY14B256LA (x8)
CY14B256NA (x16)
3V 256K Parallel Non-RTC nvSRAM Device
CY14B256KA (x8)
3V 256K Parallel RTC nvSRAM Device
CY14E256LA (x8)
5V 256K Parallel Non-RTC nvSRAM Device
CY14B101Q1
CY14B101Q2
CY14B101Q3
3V 1M Serial Non-RTC nvSRAM Device
CY14B101P
3V 1M Serial RTC nvSRAM Device
CY14B512Q1
CY14B512Q2
CY14B512Q3
3V 512K Serial Non-RTC nvSRAM Device
CY14B512P
3V 512K Serial RTC nvSRAM Device
CY14B256Q1
CY14B256Q2
CY14B256Q3
3V 256K Serial Non-RTC nvSRAM Device
CY14B256P
3V 512K Serial RTC nvSRAM Device
CY14V101LA
CY14V101NA
1.8V 1M Parallel nvSRAM Device
CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:
Zhaomin Ji
Principal Reliability Engineer
(408) 432-7021
Mira Ben-Tzur
Quality Engineering Director
(408) 943-2675
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Page 1 of 11
Document No.001-58834 Rev *D
ECN # 4257074
QUALIFICATION HISTORY
Qual
Report
Description of Qualification Purpose
Date
Comp
071304
To qualify S8 SONOS technology and 4M nvSRAM devices CY14B104L /
CY14B104N (7C14104AC base die) using S8TNV-5R, fabricated at Cypress
Minnesota CMI (Fab4)
Nov 2008
090604
To qualify 1M nvSRAM K2 (with both RTC-Real Time Clock and bond options for
Non-RTC) devices CY14B101*/CY14B512*/CY14E256* (7C14101CC base die)
using S8TNV-5R, fabricated at Cypress Minnesota CMI (Fab4)
Sep 2009
100203
To qualify 1M nvSRAM K2 1.8V device option CY14V101LA/CY14V101NA
(7C14121CC base die) using S8TNV-5R, fabricated at Cypress Minnesota CMI
(Fab4)
July 2010
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Page 2 of 11
Document No.001-58834 Rev *D
ECN # 4257074
PRODUCT DESCRIPTION (for qualification)
Purpose: Qualification of S8 technology & S8TNV-5R 1M nvSRAM product at CMI (Fab 4)
Marketing Part #:
CY14B101*/CY14B512*/CY14B256*/ CY14V101*
Device Description:
1.8V, 3V & 5V Commercial/Industrial, available in 44-Lead TSOP II / 48-Lead SSOP
/ 32-Lead SOIC
Cypress Semiconductor Corporation – MID
Cypress Division:
TECHNOLOGY/FAB PROCESS DESCRIPTION – S8TNV-5R
Number of Metal Layers:
3
Metal 1: 300Å TiW /3,200Å Al 0.5%Cu /100Å Ti
Metal
Composition: Metal 2: 300Å TiW /3,200Å Al 0.5%Cu /100Å Ti
Metal 3: 300Å TiW /7,200Å Al 0.5% Cu /150Å Ti
Passivation Type:
9000A Si3N4 / 1000A SiO2
Generic Process Technology/Design Rule
(drawn):
S8/0.13µm
Gate Oxide Material/Thickness (MOS):
SiO2 32Å (LV) & SiO2 120 Å (HV)
Name/Location of Die Fab (prime) Facility:
Cypress Semiconductor -- Bloomington, MN
Die Fab Line ID/Wafer Process ID:
Fab4 / S8TNV-5R
PACKAGE / ASSEMBLY INFORMATION
Assembly Site:
CML-R , ASE-TAIWAN / AMKOR-M
Package:
{48-Lead SSOP/44-Lead TSOP} / {32-Lead SOIC/16-Lead SOIC}
Mold Compound:
KEG600DA / G600
Die Attach:
Dexter QMI509 / Ablestik 8290
Die Size (Mils):
161.61 x 149.6
Leadframe Design:
{C7025-HALFHARD /8 DOT SLOTTED RMP} / {Cu/RMP (Reduced Metal Pad)}
Leadfinish/solder ball:
NiPdAu / Pure Sn
Wire (Al/Au) diam:
0.8 Mil / 1.0 Mil
MSL:
3
Solder Reflow Temp:
260C
Note: Package Qualification details upon request
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Page 3 of 11
Document No.001-58834 Rev *D
ECN # 4257074
*** RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT
Stress/Test
Test Condition
(Temp/Bias)
Result
P/F
High Temperature Operating Life
Dynamic Operating Condition, 150°C, 2.7V/5.25V, 48 Hours
P
Early Failure Rate (EFR)
JESD22-A-108-B
High Temperature Operating Life
Dynamic Operating Condition, 150°C, 2.7V/5.25V, 500 Hours
Latent Failure Rate (LFR)
JESD22-A-108-B
Pre/Post LFR AC/DC Char
AC/DC Critical Parameter Char at LFR 0hrs, 80hrs & 500hrs
P
Endurance
200K Cycles @ 90C, Per datasheet
P
Endurance
1M Cycles @ 90C
P
Data Retention
150°C, 1000 Hours
P
Temperature Cycle
-650C to 1500C, JESD22-A-104
P
P
500 Cycs, Require Precondition
High Accelerated Saturation Test
130°C, 3.63V, 85%RH, JESD22-A-110-B
(HAST)
128 Hours, Require Precondition
Pressure Cooker
121°C/100%RH, JESD22-A102-C
P
P
168 Hours, Require Precondition
Precondition
JESD22 Moisture Sensitivity
P
Electrostatic Discharge
Human Body Model (ESD-HBM)
2,200V, JESD22-A114E
Electrostatic Discharge
Charge Device Model (ESD-CDM)
500V, JESD22-C101C
Electrostatic Discharge
Machine Model (ESD-MM)
200V, JESD22-A115-A
Latch-up Sensitivity
5.4V,± 200mA, 125°C, EIA/JESD78
P
Age Bond Strength
Mil-Std-883, Method 2011
P
Acoustic
Per MSL3 Spec
P
Soft Error (Alpha Particle)
JESD89A
P
Soft Error (Neutron/Proton)
JESD89A
P
SEM X-Section
XY audit at center wafer and edge wafer
P
Low Temperature Operating Life Test
Dynamic Operating Condition, 2.7V, -30°C, 500 Hours
P
High Temp Steady State Life Test
Static Operating Condition, 2.7V, 150°C, 1000 Hours
P
P
P
P
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Page 4 of 11
Document No.001-58834 Rev *D
ECN # 4257074
RELIABILITY FAILURE RATE SUMMARY
Stress/Test
Device Tested/
Device Hours
#
Fails
Activation
Energy
Thermal
AF4
Failure Rate
High Temperature Operating Life
Early Failure Rate
4,009 Devices*
0
N/A
N/A
0 PPM
High Temperature Operating Life1,2,
Long Term Failure Rate
387,000 DHRs*
0
0.7
170
14 FITs
* EFR data is based on QTP 090604 and QTP 100203 only, LFR data is based on QTP 071304, 090604 and 100203 data
1
2
3
Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C.
Chi-squared 60% estimations used to calculate the failure rate.
Thermal Acceleration Factor is calculated from the Arrhenius equation
E 1 1
AF = exp A -
k T 2 T1
where:
EA =The Activation Energy of the defect mechanism.
k = Boltzmann's constant = 8.62x10-5 eV/Kelvin.
T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device
at use conditions.
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Page 5 of 11
Document No.001-58834 Rev *D
ECN # 4257074
Reliability Test Data
QTP # 071304
Device
Mechanism
Fab Lot #
Assy Lot #
Assy Loc
Duration
Samp
Rej
Failure
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 2.7V, Vcc Max
CY14B104L (7C14104AC)
4811240
610819876
CML-R
48
1222
0
CY14B104L (7C14104AC)
4814841
610832326
CML-R
48
1316
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
48
932
0
CY14B104L (7C14104AC)
4819437
610842294
CML-R
48
813
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 2.7V, Vcc Max
CY14B104L (7C14104AC)
4811240
610819876
CML-R
500
120
0
CY14B104L (7C14104AC)
4814841
610832326
CML-R
500
120
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
500
119
0
CY14B104L (7C14104AC)
4819437
610842294
CML-R
500
119
0
STRESS: Pre-/ Post HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE CHAR
CY14B104L (7C14104AC)
4811240
610819876
CML-R
80/500
10
0
CY14B104L (7C14104AC)
4814841
610832326
CML-R
80/500
10
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
80/500
10
0
CY14B104L (7C14104AC)
4819437
610842294
CML-R
80/500
10
0
STRESS: ENDURANCE, 200K CYCLES, 90C
CY14B104L (7C14104AC)
4811240
610819876
CML-R
COMP
80
0
CY14B104L (7C14104AC)
4817305
610841260
CML-R
COMP
77
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
COMP
160
0
CY14B104L (7C14104AC)
4819437
610842294
CML-R
COMP
80
0
CY14B104L (7C14104AC)
4817306/4818074
CML-R
COMP
3307
0
STRESS: DATA RETENTION, 150C
CY14B104L (7C14104AC)
4817306
610830615
CML-R
1000
77
0
CY14B104L (WAFER)
4817306
610830615
CML-R
1008
228
0
CY14B104L (7C14104AC)
4817305
610841260
CML-R
1000
80
0
CY14B104L (WAFER)
4817305
610841260
CML-R
1008
216
0
CY14B104L (7C14104AC)
4818074
N/A
CML-R
1000
80
0
CY14B104L (WAFER)
4818074
N/A
CML-R
1008
402
0
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Page 6 of 11
Document No.001-58834 Rev *D
ECN # 4257074
Reliability Test Data
QTP # 071304
Device
Mechanism
Fab Lot #
Assy Lot #
Assy Loc
Duration
Samp
Rej
Failure
STRESS: ESD-HUMAN BODY CIRCUIT PER JEDEC EIA/JESD22-A114-B, 2,200V
CY14B104L (7C14104AC)
4807004
610812949
CML-R
COMP
8
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
COMP
8
0
CY14B104L (7C14104AC)
4811240
610819876
CML-R
COMP
8
0
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY14B104L (7C14104AC)
4807004
610812949
CML-R
COMP
9
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
COMP
9
0
CY14B104L (7C14104AC)
4811240
610819876
CML-R
COMP
9
0
STRESS: ESD-MACHINE MODEL, 200V
CY14B104L (7C14104AC)
4807004
610812949
CML-R
COMP
5
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
COMP
5
0
CY14B104L (7C14104AC)
4811240
610819876
CML-R
COMP
5
0
STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 1.98V, PRE COND 192 HR 30C/60%RH, MSL3
CY14B104L (7C14104AC)
4811240
610819876
CML-R
128
77
0
CY14B104L (7C14104AC)
4814841
610832326
CML-R
128
80
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
128
77
0
STRESS: PRESSURE COOKER TEST, 121C, 100%RH, 15 Psig, PRE COND 192 HR 30C/60%RH, MSL3
CY14B104L (7C14104AC)
4807004
610812949
CML-R
168
77
0
CY14B104L (7C14104AC)
4814841
610832326
CML-R
168
80
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
168
77
0
STRESS: Temperature Cycle COND. C, -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3
CY14B104L (7C14104AC)
4807004
610812949
CML-R
1000
77
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
1000
80
0
CY14B104L (7C14104AC)
4814841
610832326
CML-R
500
80
0
STRESS: STATIC LATCH-UP TESTING, 125C, 5.4V, ±200mA
CY14B104L (7C14104AC)
4807004
610812949
CML-R
COMP
6
0
CY14B104L (7C14104AC)
4814841
610832326
CML-R
COMP
6
0
CY14B104L (7C14104AC)
4819437
610842294
CML-R
COMP
6
0
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Page 7 of 11
Document No.001-58834 Rev *D
ECN # 4257074
Reliability Test Data
QTP # 071304
Device
Mechanism
Fab Lot #
Assy Lot #
Assy Loc
Duration
Samp
Rej
Failure
STRESS: AGE BOND
CY14B104L (7C14104AC)
4807004
610812949
CML-R
COMP
10
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
COMP
10
0
CY14B104L (WAFER)
4818074
N/A
CML-R
COMP
10
0
CY14B104L (7C14104AC)
4807004
610812949
CML-R
COMP
15
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
COMP
15
0
CY14B104L (7C14104AC)
4814841
610832326
CML-R
COMP
15
0
STRESS: ACOUSTIC-MSL3
STRESS: SER – ALPHA PARTICLE, 3-TEPM, 3-VOLTAGE, FIT=550 FIT/Mbit @ 85C, Vcc Nom
CY14B104L (7C14104AC)
4811240
610819876
CML-R
COMP
3
0
CY14B104L (7C14104AC)
4817306
610830615
CML-R
COMP
3
0
CY14B104L (7C14104AC)
4819437
610842294
CML-R
COMP
3
0
N/A
CML-R
COMP
3
0
500
77
0
1000
76
0
STRESS: SER – NEUTRON/PROTON
CY14B104L (7C14104AC)
4808220
STRESS: LOW TEMPERATURE OPERATING LIFE TEST, -30C, 2.7V, Vcc Max
CY14B104L (7C14104AC)
4817306
610830615
CML-R
STRESS: HIGH TEMP STEADY STATE LIFE TEST, 150C, 2.7V, Vcc Max
CY14B104L (7C14104AC)
4811240
610819876
CML-R
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Page 8 of 11
Document No.001-58834 Rev *D
ECN # 4257074
Reliability Test Data
QTP # 090604
Device
Mechanism
Fab Lot #
Assy Lot #
Assy Loc
Duration
Samp
Rej
Failure
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 2.7V, Vcc Max
CY14101B8C (7C14101CC)
4908403
610918063
CML-R
48
1153
0
CY14101B8CC (7C14101CC)
4910444
610922709
CML-R
48
688
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 2.7V, Vcc Max
CY14101B8C (7C14101CC)
4908403
610918063
CML-R
500
118
0
STRESS: Pre-/ Post HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE CHAR
CY14101B8C (7C14101CC)
4908403
610918063
CML-R
80/500
10
0
STRESS: ENDURANCE (90C), 200K CYCLES+168 HOURS DATA RETENSION
CY14101B8C (7C14101CC)
4908403
610918063
CML-R
COMP
80
0
CML-R
1000
80
0
STRESS: DATA RETENTION (150C) + 200K ENDURANCE
CY14101B8C (7C14101CC)
4908403
610918063
STRESS: ESD-HUMAN BODY CIRCUIT PER JEDEC EIA/JESD22-A114-B, 2,200V
CY14101B8C (7C14101CC)
4908403
610918063
CML-R
COMP
8
0
CML-R
COMP
9
0
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY14101B8C (7C14101CC)
4908403
610918063
STRESS: PRESSURE COOKER TEST, 121C, 100%RH, 15 Psig, PRE COND 192 HR 30C/60%RH, MSL3
CY14101B8C (7C14101CC)
4908403
610918063
CML-R
288
77
0
STRESS: TEMPERATURE CYCLE COND. C, -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3
CY14101B8C (7C14101CC)
4908403
610918063
CML-R
1000
77
0
STRESS: STATIC LATCH-UP TESTING, 125C, 5.4V, ±200mA
CY14101B8C (7C14101CC)
4908403
610918063
CML-R
COMP
9
0
4908403
610918063
CML-R
COMP
15
0
STRESS: ACOUSTIC-MSL3
CY14101B8C (7C14101CC)
STRESS: SER – ALPHA PARTICLE, 3-TEPM, 3-VOLTAGE, @ 85C, Vcc Nom
CY14101B8C (7C14101CC)
4908403
610918063
CML-R
COMP
3
0
4908403
610918063
CML-R
COMP
3
0
80
0
STRESS: AGE BOND
CY14101B8C (7C14101CC)
STRESS: ENDURANCE (90C) 1 MILLION CYCLES+168 HOURS DATA RETENTION
CY14B101LA (7C1401B8CC)
4910267
610935909
CML-R
COMP
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Page 9 of 11
Document No.001-58834 Rev *D
ECN # 4257074
Reliability Test Data
QTP # 100203
Device
Mechanism
Fab Lot #
Assy Lot #
Assy Loc
Duration
Samp
Rej
COMP
15
0
Failure
STRESS: ACOUSTIC-MSL3
CY14V101LA (7C1421B8C)
4944705
HA1011002
T-Taiwan
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 5.25V, Vcc Max
CY7C1421B8C (7C1421B8C)
4944705
611017304
G-Taiwan
48
2162
0
STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 5.25V, Vcc Max
CY7C1421B8C (7C1421B8C)
4944705
611017304
G-Taiwan
500
178
0
STRESS: ESD-HUMAN BODY CIRCUIT PER JEDEC EIA/JESD22-A114-B, 2,200V
CY14V101LA (7C1421B8C)
4944705
HA1011002
T-Taiwan
COMP
8
0
HA1011002
T-Taiwan
COMP
9
0
HA1011002
T-Taiwan
COMP
5
0
T-Taiwan
COMP
6
0
STRESS: ESD-CHARGE DEVICE MODEL, 500V
CY14V101LA (7C1421B8C)
4944705
STRESS: ESD-MACHINE MODEL, 200V
CY14V101LA (7C1421B8C)
4944705
STRESS: STATIC LATCH-UP TESTING, 125C, 5.4V, ±140mA
CY14V101LA (7C1421B8C)
4944705
HA1011002
STRESS: TEMPERATURE CYCLE COND. C, -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3
CY14V101LA (7C1421B8C)
4944705
HA1011002
T-Taiwan
500
80
0
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Page 10 of 11
Document No.001-58834 Rev *D
ECN # 4257074
Document History Page
Document Title:
Document Number:
QTP 090604: S8 K2 1M NVSRAM PRODUCT QUALIFICATION REPORT
001-58834
Rev. ECN
Orig. of
No.
Change
**
2846750 ZIJ
*A
2879283 NRG
*B
3416227 NSR
*C
3888273 ZIJ
*D
4257074 HSTO
Description of Change
Initial Spec Release
Added 1 Million Endurance Qualification data from 4 Meg Evans
nvSRAM QTP 092804
Changed the version from Version 2 to Version 3 and month from
January to February
Changed the Assembly Site from CML-RA to CML-R and added ASETaiwan on Package / Assembly Information Table
Changed all Assy Loc from CML-RA to CML-R
Added 1 Million Endurance Cycling Test data to K2 1M QTP 090604
Removed ** markers.
Removed QTP version in front page
Removed QTP#082704 and 092804 in qualification history page and
QTP data
Added QTP# 090604 in the title
Added QTP#100203 in qualification history page and QTP data
Added CY14V101LA/CY14V101NA devices in Title page
Recomputed EFR and LFR failure rate
Changed of QTP revision date in the title page.
Sunset review
Removed all Cypress spec reference number in page4 table.
Updated the “Technology/Fab Process Description” table in page3.
Distribution: WEB
Posting:
None
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Page 11 of 11