STMICROELECTRONICS STD22NM20NT4

STD22NM20N
N-CHANNEL 200V - 0.088Ω - 22A DPAK
ULTRA LOW GATE CHARGE MDmesh™ II MOSFET
Table 1: General Features
TYPE
STD22NM20N
■
■
■
■
■
Figure 1: Package
VDSS
RDS(on)
ID
200 V
< 0.105 Ω
22 A
WORLDWIDE LOWEST GATE CHARGE
TYPICAL RDS(on) = 0.088 Ω
HIGH dv/dt and AVALANCHE CAPABILITIES
LOW INPUT CAPACITANCE
LOW GATE RESISTANCE
DESCRIPTION
This 200V MOSFET with a new advanced layout
brings all unique advantages of MDmesh technology to lower voltages. The device exhibits worldwide lowest gate charge for any given onresistance. Its use is therefore ideal as primary
switch in isolated DC-DC converters for Telecom
and Computer applications. Used in combination
with secondary-side low-voltage STripFET™
products, it contributes to reducting losses and
boosting effeciency.
3
1
DPAK
Figure 2: Internal Schematic Diagram
APPLICATIONS
The MDmesh™ family is very suitable for increasing power density allowing system miniaturization
and higher efficiencies
Table 2: Order Codes
SALES TYPE
MARKING
PACKAGE
PACKAGING
STD22NM20NT4
D22NM20N
DPAK
TAPE & REEL
Rev. 4
June 2005
1/10
STD22NM20N
Table 3: Absolute Maximum ratings
Symbol
VDS
VDGR
VGS
ID
Parameter
Value
Unit
200
V
Drain-gate Voltage (RGS = 20 kΩ)
200
V
Gate- source Voltage
± 20
V
Drain Current (continuous) at TC = 25°
Drain Current (continuous) at TC = 100°
22
13.7
A
A
Drain-source Voltage (VGS = 0)
IDM (*)
Drain Current (pulsed)
88
A
PTOT
Total Dissipation at TC = 25°C
100
W
Derating Factor
0.8
W/°C
dv/dt (2)
Tj
Tstg
Peak Diode Recovery voltage slope
Storage Temperature
Max Operating Junction Temperature
14
V/ns
150
-65 to 150
°C
°C
°C/W
(*) ISD ≤ 22A, di/dt ≤ 400A/µs, VDD = 80% V(BR)DSS
Table 4: Thermal Data
Rthj-case
Thermal Resistance Junction-case Max
1.25
Rthj-amb
Thermal Resistance Junction-ambient Max
100
°C/W
Thermal Resistance Junction-pcb (*)
Maximum Lead Temperature For Soldering Purpose
43
275
°C/W
°C
Max Value
Unit
Rthj-ambTl
(*) When mounted on 1 inch² FR-4 board, 2 oz Cu, t ≤ 10 sec
Table 5: Avalanche Characteristics
Symbol
2/10
Parameter
IAS
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
22
A
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = 22 A, VDD = 50 V)
380
mJ
STD22NM20N
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 6: On/Off
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
200
Unit
Drain-source
Breakdown Voltage
ID = 1mA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating, TC = 125 °C
1
10
µA
µA
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20V
100
nA
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
4.2
5
V
RDS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 11 A
0.088
0.105
Ω
Typ.
Max.
Unit
V(BR)DSS
3.5
V
Table 7: Dynamic
Symbol
gfs (2)
Parameter
Test Conditions
Min.
Forward Transconductance
VDS = 15 V, ID=11 A
8
S
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25V, f = 1 MHz, VGS = 0
800
330
130
pF
pF
pF
Equivalent Output
Capacitiance
VGS = 0 V, VDS = 0 V to 400 V
225
pF
Gate Input Resistance
f= 1MHz Gate DC Bias = 0
Test Sgnal Level = 20 mV
Open Drain
5
Ω
td(on)
tr
tr(Voff)
tf
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
VDD = 100 V, ID = 11 A
RG = 4.7Ω VGS = 10 V
(see Figure 15)
40
15
40
11
ns
ns
ns
ns
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 100 V, ID = 20 A,
VGS = 10 V
(see Figure 19)
32
6
25
Ciss
Coss
Crss
Coss eq. (**)
RG
50
nC
nC
nC
(**) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
Table 8: Source Drain Diode
Symbol
Parameter
ISD
ISDM (1)
Source-drain Current
Source-drain Current (pulsed)
VSD (2)
Forward On Voltage
ISD = 20 A, VGS = 0
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 20 A, di/dt = 100 A/µs
VDD = 100V, Tj = 25°C
(see test circuit, Figure 17)
160
960
128
ns
µC
A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 20 A, di/dt = 100 A/µs
VDD = 100V, Tj = 150°C
(see test circuit, Figure 17)
225
1642
15
ns
µC
A
trr
Qrr
IRRM
trr
Qrr
IRRM
Test Conditions
Min.
Typ.
Max.
Unit
22
88
A
A
1.3
V
(1) Pulse width limited by safe operating area.
(2) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
3/10
STD22NM20N
Figure 3: Safe Operating Area
Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
4/10
STD22NM20N
Figure 9: Gate Charge vs Gate-source Voltage
Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized On Resistance vs Temperature
Figure 11: Source-Drain Diode Forward Characteristics
Figure 14: Normalized BVdss vs Temperature
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STD22NM20N
Figure 15: Unclamped Inductive Load Test Circuit
Figure 18: Unclamped Inductive Wafeform
Figure 16: Switching Times Test Circuit For
Resistive Load
Figure 19: Gate Charge Test Circuit
Figure 17: Test Circuit For Inductive Load
Switching and Diode Recovery Times
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STD22NM20N
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
A
2.20
2.40
0.087
TYP.
0.094
MAX.
A1
0.90
1.10
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.90
0.025
0.035
B2
5.20
5.40
0.204
0.213
C
0.45
0.60
0.018
0.024
C2
0.48
0.60
0.019
0.024
D
6.00
6.20
0.236
0.244
E
6.40
6.60
0.252
0.260
G
4.40
4.60
0.173
0.181
H
9.35
10.10
0.368
0.398
L2
0.8
0.031
L4
0.60
1.00
0.024
0.039
V2
0o
8o
0o
0o
P032P_B
7/10
STD22NM20N
DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
DIM.
mm
MIN.
A
B
DIM.
mm
MIN.
MAX.
A0
6.8
7
0.267 0.275
B0
10.4
10.6
0.409 0.417
12.1
0.476
1.6
0.059 0.063
1.85
0.065 0.073
B1
8/10
inch
D
1.5
D1
1.5
E
1.65
MIN.
MAX.
0.059
F
7.4
7.6
0.291 0.299
K0
2.55
2.75
0.100 0.108
0.153 0.161
P0
3.9
4.1
P1
7.9
8.1
0.311 0.319
P2
1.9
2.1
0.075 0.082
R
40
W
15.7
1.574
16.3
0.618
0.641
MIN.
330
1.5
C
12.8
D
20.2
G
16.4
N
50
T
TAPE MECHANICAL DATA
inch
MAX.
MAX.
12.992
0.059
13.2
0.504 0.520
18.4
0.645 0.724
0.795
1.968
22.4
0.881
BASE QTY
BULK QTY
2500
2500
STD22NM20N
Table 9: Revision History
Date
Revision
31-May-2004
15-Mar-2005
09-May-2005
09-Jun-2005
1
2
3
4
Description of Changes
First Release.
Update version.
Complete version.
New update
9/10
STD22NM20N
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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