STP40N20 STB40N20 - STW40N20 N-CHANNEL 200V - 0.038Ω - 40A TO-220/TO-247/D2PAK LOW GATE CHARGE STripFET™ MOSFET Figure 1: Package Table 1: General Features TYPE VDSS RDS(on) ID Pw STP40N20 STW40N20 STB40N20 200 V 200 V 200 V < 0.045 Ω < 0.045 Ω < 0.045 Ω 40 A 40 A 40 A 160 W 160 W 160 W ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.038 Ω GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY EXCELLENT FIGURE OF MERIT (RDS*Qg) 100% AVALANCHE TESTED 3 1 3 2 2 1 TO-220 TO-247 3 DESCRIPTION This MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency isolated DC-DC converters. 1 D2PAK Figure 2: Internal Schematic Diagram APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ UPS Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STP40N20 P40N20 TO-220 TUBE STW40N20 W40N20 TO-247 TUBE STB40N20 B40N20 D2PAK TAPE & REEL Rev. 3 June 2005 1/13 STB40N20 - STP40N20 - STW40N20 Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS Parameter Value Unit 200 V Drain-gate Voltage (RGS = 20 kΩ) 200 V Gate- source Voltage ± 20 V Drain-source Voltage (VGS = 0) ID Drain Current (continuous) at TC = 25°C 40 A ID Drain Current (continuous) at TC = 100°C 25 A IDM ( ) Drain Current (pulsed) 160 A PTOT Total Dissipation at TC = 25°C 160 W Derating Factor 1.28 W/°C 12 V/ns -55 to 150 °C dv/dt (1) Tj Tstg Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature ( ) Pulse width limited by safe operating area (1) ISD ≤ 40A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, T j ≤ T JMAX. Table 4: Thermal Data TO-220/ Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max Tl Maximum Lead Temperature For Soldering Purpose TO-247 0.78 62.5 °C/W 50 °C/W 300 °C Max Value Unit Table 5: Avalanche Characteristics Symbol 2/13 Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 40 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 230 mJ STB40N20 - STP40N20 - STW40N20 ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 6: On/Off Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 1mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 20 A V(BR)DSS Min. Typ. Max. 200 2 Unit V 1 10 µA µA ±100 nA 3 4 V 0.038 0.045 Ω Typ. Max. Unit Table 7: Dynamic Symbol gfs (1) Parameter Test Conditions Forward Transconductance VDS = 15 V, ID=20 A Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance td(on) tr td(off) tr Qg Qgs Qgd Min. 30 S VDS = 25V, f = 1 MHz, VGS = 0 2500 510 78 pF pF pF Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time VDD = 100 V, ID = 20 A, RG= 4.7 Ω VGS = 10 V (Resistive Load see, Figure 17) 20 44 74 22 ns ns ns ns Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 160V, ID = 40 A, VGS = 10V 75 13.2 35.5 nC nC nC Table 8: Source Drain Diode Symbol Parameter ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 20 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 20 A, di/dt = 100A/µs VDD = 100V, Tj = 25°C (see test circuit, Figure 18) 192 922 9.6 ns nC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 20 A, di/dt = 100A/µs VDD = 100V, Tj = 150°C (see test circuit, Figure 18) 242 1440 11.9 ns nC A trr Qrr IRRM trr Qrr IRRM Test Conditions Min. Typ. Max. Unit 40 160 A A 1.5 V (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. 3/13 STB40N20 - STP40N20 - STW40N20 Figure 3: Safe Operating Area For TO-220/ D2PAK Figure 6: Thermal Impedance For TO-220/ D2PAK Figure 4: Safe Operating Area For TO-247 Figure 7: Thermal Impedance For TO-247 Figure 5: Output Characteristics Figure 8: Transfer Characteristics 4/13 STB40N20 - STP40N20 - STW40N20 Figure 9: Transconductance Figure 12: Static Drain-source On Resistance Figure 10: Gate Charge vs Gate-source Voltage Figure 13: Capacitance Variations Figure 11: Normalized Gate Threshold Voltage vs Temperature Figure 14: Normalized On Resistance vs Temperature 5/13 STB40N20 - STP40N20 - STW40N20 Figure 15: Source-Drain Forward Characteristics 6/13 STB40N20 - STP40N20 - STW40N20 Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform Figure 17: Switching Times Test Circuit For Resistive Load Figure 20: Gate Charge Test Circuit Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times 7/13 STB40N20 - STP40N20 - STW40N20 TO-220 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 8/13 TYP 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 STB40N20 - STP40N20 - STW40N20 TO-247 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 0.134 b2 3.0 3.40 0.118 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 e 5.45 L 14.20 14.80 0.560 L1 3.70 4.30 0.14 L2 0.620 0.214 18.50 0.582 0.17 0.728 øP 3.55 3.65 0.140 0.143 øR 4.50 5.50 0.177 0.216 S 5.50 0.216 9/13 STB40N20 - STP40N20 - STW40N20 D2PAK MECHANICAL DATA TO-247 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 D1 E 8 10 E1 0.315 10.4 0.393 8.5 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.625 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 M 2.4 3.2 0.094 0.126 R 0.4 0º 0.015 4º 3 V2 1 10/13 STB40N20 - STP40N20 - STW40N20 D2PAK FOOTPRINT TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 24.4 N 100 T TAPE MECHANICAL DATA DIM. mm inch MIN. MAX. MIN. A0 10.5 10.7 0.413 0.421 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 0.449 0.456 inch MAX. MIN. MAX. 330 12.992 13.2 0.504 0.520 26.4 0.960 1.039 0.059 0795 3.937 30.4 1.197 BASE QTY BULK QTY 1000 1000 MAX. F 11.4 11.6 K0 4.8 5.0 0.189 0.197 P0 3.9 4.1 0.153 0.161 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 0.075 0.082 R 50 1.574 T 0.25 0.35 0.0098 0.0137 W 23.7 24.3 0.933 0.956 * on sales type 11/13 STB40N20 - STP40N20 - STW40N20 Table 9: Revision History Date Revision 27-Sep-2004 03-Feb-2005 1 2 First Release. Complete Version 03-Jun-2005 3 Update with D2PAK 12/13 Description of Changes STB40N20 - STP40N20 - STW40N20 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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