STE53NA50 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR TYPE ST E53NA50 ■ ■ ■ ■ ■ ■ ■ ■ ■ V DSS R DS(on) ID 500 V < 0.085 Ω 53 A TYPICAL RDS(on) = 0.075 Ω HIGH CURRENT POWER MODULE AVALANCHE RUGGED TECHNOLOGY VERY LARGE SOA - LARGE PEAK POWER CAPABILITY EASY TO MOUNT SAME CURRENT CAPABILITY FOR THE TWO SOURCE TERMINALS EXTREMELY LOW Rth (Junction to case) VERY LOW INTERNAL PARASITIC INDUCTANCE ISOLATED PACKAGE UL RECOGNIZED ISOTOP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SMPS & UPS ■ MOTOR CONTROL ■ WELDING EQUIPMENT ■ OUTPUT STAGE FOR PWM, ULTRASONIC CIRCUITS ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Drain-source Voltage (VGS = 0) 500 V V DGR Drain- gate Voltage (RGS = 20 kΩ) 500 V V GS Gate-source Voltage ± 30 V V DS Parameter o ID Drain Current (continuous) at T c = 25 C 53 A ID Drain Current (continuous) at T c = 100 o C 33 A 212 A Total Dissipation at Tc = 25 C 460 W Derating Factor 3.68 W/ o C I DM (•) P to t T st g Tj V ISO Drain Current (pulsed) o -55 to 150 o C Max. Operating Junction T emperature 150 o C Insulation W ithhstand Voltage (AC-RMS) 2500 Storage Temperature V (•) Pulse width limited by safe operating area February 1998 1/7 STE53NA50 THERMAL DATA R t hj-ca se R thc -h Thermal Resistance Junction-case Thermal Resistance Case-heatsink W ith Conductive Grease Applied Max 0.27 o C/W Max 0.05 o C/W AVALANCHE CHARACTERISTICS Symb ol Parameter I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) E AS Single Pulse Avalanche Energy o (starting Tj = 25 C, I D = IAR , VDD = 50 V) Max Valu e Unit 26 A 1014 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symb ol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 1 mA V GS = 0 V DS = Max Rating Zero G ate Voltage Drain Current (VGS = 0) V DS = Max Rating Gate-body Leakage Current (V DS = 0) Min. Typ . Max. 500 Un it V o T c = 125 C V GS = ± 30 V 100 1000 µA µA ± 400 nA ON (∗) Symb ol Parameter Test Cond ition s V GS(th) Gate Threshold Voltage V DS = VGS ID = 1 mA R DS( on) Static Drain-source On V GS = 10V Resistance ID = 27 A ID(o n) On State Drain Current V DS > I D(on) x R DS(on) max V GS = 10 V Min. Typ . Max. Un it 2.25 3 3.75 V 0.075 0.085 Ω 53 A DYNAMIC Symb ol g fs (∗) C iss C oss C rss 2/7 Parameter Test Cond ition s Forward Transconductance V DS >I D(on ) X RDS(on)MAX I D = 27 A Input Capacitance Output Capacitance Reverse T ransfer Capacitance V DS = 25 V f = 1 MHz VGS = 0 Min. Typ . Max. 25 Un it S 13 1500 450 16 2000 650 nF pF pF STE53NA50 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symb ol Typ . Max. Un it t d(on) tr Turn-on Time Rise Time Parameter V DD = 250 V I D = 27 A VGS = 10 V R G = 4.7 Ω (see test circuit, figure 1) Test Cond ition s Min. 57 92 80 130 ns ns Qg Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 400 V 470 54 219 658 nC nC nC Typ . Max. Un it 105 36 145 145 50 205 ns ns ns Typ . Max. Un it 53 212 A A 1.6 V I D = 53 A VGS = 10 V SWITCHING OFF Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Cond ition s Min. V DD = 400 V I D = 53 A V GS = 10 V R G = 4.7 Ω (see test circuit, figure 3) SOURCE DRAIN DIODE Symb ol Parameter Test Cond ition s I SD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 53 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 53 A di/dt = 100 A/µs o Tj = 150 C V R = 100 V (see test circuit, figure 3) t rr Q rr I RRM Min. V GS = 0 1000 ns 31.5 µC 63 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area for Thermal Impedance 3/7 STE53NA50 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/7 STE53NA50 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Fig. 1: Switching Times Test Circuits For Resistive Load Fig. 2: Gate Charge test Circuit Fig. 3: Test Circuit For Inductive Load Switching And Diode Recovery Times 5/7 STE53NA50 ISOTOP MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 11.8 12.2 0.466 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 J 4.1 4.3 0.161 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 N 4 O 7.8 0.157 0.157 8.2 0.307 0.322 A G B O H J C K L M 6/7 F E D N STE53NA50 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1998 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . .. 7/7