STU13NB60 N-CHANNEL ENHANCEMENT MODE PowerMESH MOSFET PRELIMINARY DATA TYPE STU13NB60 ■ ■ ■ ■ ■ ■ V DSS R DS(on) ID 600 V < 0.45 Ω 12.6 A TYPICAL RDS(on) = 0.4 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED ± 30V GATE TO SOURCE VOLTAGE RATING DESCRIPTION Using the latest high voltage MESH OVERLAY process, SGS-Thomson has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. 1 2 3 Max220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS SWITCH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ■ ABSOLUTE MAXIMUM RATINGS Symbol V DS Parameter Value Uni t Drain-source Voltage (V GS = 0) 600 V V DGR Drain- gate Voltage (R GS = 20 kΩ) 600 V V GS Gate-source Voltage ± 30 V 12.6 A o ID Drain Current (continuous) at Tc = 25 C ID o IDM (•) P t ot dv/dt( 1 ) T stg Tj Drain Current (continuous) at Tc = 100 C 7.9 A 50.4 A Total Dissipation at Tc = 25 C 160 W Derating F actor 1.28 W/ C 4.5 V/ ns Drain Current (pulsed) o Peak Diode Recovery voltage slope Storage T emperature Max. O perating Junction Temperature (•) Pulse width limited by safe operating area October 1997 o -65 to 150 o C 150 o C (1) ISD ≤13A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/6 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. STU13NB60 THERMAL DATA R t hj-ca se Rthj -amb R thc- si nk Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose o 0.78 62.5 0.5 300 C/W oC/W o C/W o C Max Valu e Unit AVALANCHE CHARACTERISTICS Symb ol Parameter I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) 12.6 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, I D = IAR , VDD = 50 V) 800 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symb ol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 250 µA o @ 100 C Typ . Max. 600 V GS = 0 V DS = Max Rating Zero G ate Voltage Drain Current (VGS = 0) V DS = Max Rating Gate-body Leakage Current (V DS = 0) Min. Un it V o T c = 125 C V GS = ± 30 V 1 50 µA µA ± 100 nA ON (∗) Symb ol Parameter Test Cond ition s ID = 250 µA V GS(th) Gate Threshold Voltage R DS( on) Static Drain-source On V GS = 10V Resistance ID(o n) V DS = VGS Min. Typ . Max. Un it 3 4 5 V 0.4 0.45 Ω ID =6.3 A 12.6 On State Drain Current V DS > I D(on) x R DS(on) max V GS = 10 V A DYNAMIC Symb ol g fs (∗) C iss C oss C rss 2/6 Parameter Test Cond ition s Forward Transconductance V DS > I D(on) x R DS(on) max Input Capacitance Output Capacitance Reverse T ransfer Capacitance V DS = 25 V f = 1 MHz I D =6.3 A VGS = 0 Min. Typ . 6 9 2950 370 33 Max. Un it S 3840 480 43 pF pF pF STU13NB60 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symb ol Typ . Max. Un it t d(on) tr Turn-on Time Rise Time Parameter V DD = 300 V I D = 6.3 A VGS = 10 V R G = 4.7 Ω (see test circuit, figure 3) Test Cond ition s Min. 30 14 42 20 ns ns Qg Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 480 V 65 18 27 91 nC nC nC Typ . Max. Un it 21 18 32 29 25 45 ns ns ns Typ . Max. Un it 12.6 A A 1.6 V I D =12.6 A V GS = 10 V SWITCHING OFF Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Cond ition s Min. V DD = 480 V I D = 12.6 A R G = 4.7 Ω V GS = 10 V (see test circuit, figure 5) SOURCE DRAIN DIODE Symb ol Parameter Test Cond ition s I SD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 12.6 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 12.6 A di/dt = 100 A/µs o T j = 150 C V DD = 100 V (see test circuit, figure 5) t rr Q rr I RRM Min. V GS = 0 820 ns 9.6 µC 23.5 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area 3/6 STU13NB60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STU13NB60 Max220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.3 4.6 0.169 0.181 A1 2.2 2.4 0.087 0.094 A2 2.9 3.1 0.114 0.122 b 0.7 0.93 0.027 0.036 b1 1.25 1.4 0.049 0.055 b2 1.2 1.38 0.047 0.054 c 0.45 0.6 0.18 0.023 D 15.9 16.3 0.626 0.641 D1 9 9.35 0.354 0.368 D2 0.8 1.2 0.031 0.047 D3 2.8 3.2 0.110 0.126 e 2.44 2.64 0.096 0.104 E 10.05 10.35 0.396 0.407 L 13.2 13.6 0.520 0.535 L1 3 3.4 0.118 0.133 D1 D2 A1 A2 A C D3 b b2 b1 D e E L1 L P011R 5/6 STU13NB60 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada- China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . .. 6/6