NTLTS3107P Power MOSFET −20 V, −8.3 A, Single P−Channel, Micro8 Leadless Package Features • • • • • Low RDS(on) for Extended Battery Life Surface Mount Micro8 Leadless for Improved Thermal Performance Low Profile (<1.0 mm) Optimal for Portable Designs Low Turn−On Voltage This is a Pb−Free Device Applications http://onsemi.com V(BR)DSS RDS(on) TYP 12.2 mW @ −4.5 V −20 V • Optimized for Load Management Applications • Charge Control in Battery Powered Systems • Cell Phones, DSC, Notebooks, Portable Games, etc. 26.2 mW @ −1.8 V P−Channel MOSFET S Symbol Value Unit Drain−to−Source Voltage VDSS −20 V Gate−to−Source Voltage VGS $8.0 V ID −8.3 A Continuous Drain Current (Note 1) Steady State TA = 25°C TA = 85°C −6.0 t v 10 s TA = 25°C −12 Power Dissipation (Note 1) Steady State TA = 25°C Continuous Drain Current (Note 2) Steady State PD t v 10 s D W 1.6 TA = 25°C ID TA = 25°C −3.7 W IDM −25 A TJ, TSTG −55 to 150 °C Source Current (Body Diode) IS −1.6 A Lead Temperature for Soldering Purposes (1/8 in from case for 10 s) TL 260 °C tp = 10 ms Operating Junction and Storage Temperature THERMAL RESISTANCE RATINGS Parameter Symbol Max Unit Junction−to−Ambient – Steady State (Note 1) RqJA 80 °C/W Junction−to−Ambient – t v 10 s (Note 1) RqJA 38 °C/W Junction−to−Ambient – Steady State (Note 2) RqJA 160 °C/W Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface−mounted on FR4 board using 1 sq. in. pad size (Cu. area = 1.127 sq. in. [1 oz] including traces). 2. Surface−mounted on FR4 board using minimum recommended pad size (Cu. area = TBD sq. in.). © Semiconductor Components Industries, LLC, 2005 1 1 0.8 October, 2005 − Rev. 0 MARKING DIAGRAM A −5.9 PD Pulsed Drain Current (Note 1) G 3.3 TA = 85°C Power Dissipation (Note 2) −8.3 A 15.6 mW @ −2.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter ID MAX 1 Micro8 Leadless CASE 846C A Y WW G 3107 AYWW G = Assembly Location = Year = Work Week = Pb−Free Package PIN ASSIGNMENT Drain 8 Drain 7 Drain Drain 1 Source 2 Source 6 3 Source 5 4 Gate Drain (Bottom View) ORDERING INFORMATION Device Package Shipping † NTLTS3107PR2G Micro8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTLTS3107P/D NTLTS3107P ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA −20 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Parameter Typ Max Unit OFF CHARACTERISTICS V 11 Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = −16 V Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = $8.0 V TJ = 25°C mV/°C −10 mA ±100 nA −1.2 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH) VGS(TH)/TJ RDS(on) gFS VGS = VDS, ID = −250 mA −0.45 3.4 mV/°C VGS = −4.5 V, ID = −8.0 A 12.2 16 VGS = −2.5 V, ID = −7.0 A 15.6 21 VGS = −1.8 V, ID = −5.8 A 26.2 VDS = −5 V, ID = −8.0 A 25 mW S CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 4645 6500 VGS = 0 V, f = 1 MHz, VDS = −16 V 465 650 285 400 60 VGS = −4.5 V, VDS = −16 V, ID = −8.0 A Total Gate Charge QG(TOT) 40 Threshold Gate Charge QG(TH) 3.0 Gate−to−Source Gate Charge QGS Gate−to−Drain “Miller” Charge QGD 11 td(on) 30 pF nC 7.0 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = −4.5 V, VDS = −10 V, ID = −8.0 A, RG = 3.0 W tf ns 20 250 80 DRAIN−SOURCE DIODE CHARACTERISTICS (Note 3) Forward Diode Voltage Reverse Recovery Time VSD VGS = 0 V, IS = −1.6 A TJ = 25°C −0.7 TJ = 125°C 0.5 tRR 75 Charge Time ta 28 Discharge Time tb Reverse Recovery Charge VGS = 0 V, dIS/dt = 100 A/ms, IS = −1.6 A QRR http://onsemi.com 2 V 100 ns 47 81.5 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. −1.2 nC NTLTS3107P 5V 4V −ID, DRAIN CURRENT (A) 4.5 V 24 3.6 V 3.2 V 16 2.8 V 2.4 V 8 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 32 VGS = 10 V 2V 0 2 4 6 8 TJ = 125°C 8 0 6 Figure 2. Transfer Characteristics 0.018 TJ = 25°C 0.014 TJ = −55°C 5 10 15 20 −ID, DRAIN CURRENT (A) 25 30 0.026 VGS = −2.5 V TJ = 25°C 0.018 TJ = −55°C 0.014 0.01 0 0.019 VGS = 2.5 V 0.017 VGS = 3.5 V 0.015 VGS = 4.5 V 6 12 18 24 30 −ID, DRAIN CURRENT (A) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 25°C 0.016 5 10 15 20 −ID, DRAIN CURRENT (A) 25 30 Figure 4. On−Resistance versus Drain Current and Temperature 0.02 0.018 TJ = 125°C 0.022 Figure 3. On−Resistance versus Drain Current and Temperature RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 4 Figure 1. On−Region Characteristics TJ = 125°C 0 2 −VGS, GATE−TO−SOURCE VOLTAGE (V) 0.022 0.014 TJ = −55°C TJ = 25°C −VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS = −4.5 V 0 16 0 10 0.026 0.01 24 1.8 V 1.2 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (A) 32 0.06 0.055 0.05 0.045 ID = 13.2 A 0.04 0.035 0.03 0.025 ID = 3.5 A 0.02 0.015 0.01 1 Figure 5. On−Resistance versus Drain Current and Gate Voltage 2 3 4 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 6. On−Resistance versus Gate Voltage http://onsemi.com 3 5 1.4 0.2 −VGS, THRESHOLD VARIANCE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) NTLTS3107P ID = −8 A VGS = −4.5 V 1.2 1 0.8 0.6 −50 −25 0 25 50 75 100 125 150 −VGS, GATE−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) −0.3 −0.4 −50 −25 0 25 50 75 100 Figure 8. Threshold Voltage 6000 4000 Coss 0 4 8 12 16 125 150 5 ID = 3.2 A TJ = 25°C 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 20 0 10 20 30 40 50 60 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 9. Capacitance Variation Figure 10. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 10000 100 −IS, SOURCE CURRENT (A) VDS = −10 V ID = −1 A VGS = −10 V 1000 t, TIME (ns) −0.2 Figure 7. On−Resistance Variation with Temperature Ciss 0 −0.1 TJ, JUNCTION TEMPERATURE (°C) TJ = 25°C VGS = 0 V 2000 0 TJ, JUNCTION TEMPERATURE (°C) 10000 8000 ID = −250 mA 0.1 td(off) 100 tf 10 td(on) tr 1 1 10 100 VGS = 0 V TJ = 25°C 10 1 0.1 0 0.4 0.8 1.2 1.6 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 11. Resistive Switching Time Variation versus Gate Resistance Figure 12. Diode Forward Voltage versus Current http://onsemi.com 4 2 NTLTS3107P PACKAGE DIMENSIONS MICRO8 LEADLESS CASE 846C−01 ISSUE B ÉÉÉ ÉÉÉ ÉÉÉ INDEX AREA 2X T W Y A J SEATING PLANE NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95−1 SPP−012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 4. DIMENSION D APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 MM AND 0.30 MM FROM TERMINAL TIP. DIMENSION L1 IS THE TERMINAL PULL BACK FROM PACKAGE EDGE, UP TO 0.1 MM IS ACCEPTABLE. L1 IS OPTIONAL. 5. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 6. OPTIONAL SIDE VIEW CAN SHOW LEADS 5 AND 8 REMOVED. AA 8 7 B NOTE 6 6 5 0.15 T K AA C 2X TOP VIEW 0.15 T 0.10 T 8X DIM A B C D E F G H J K L L1 P U 0.08 T NOTE 4 0.10 T W Y 0.05 T W D G E L 8X SIDE VIEW 8X 6X 8 1 7 2 6 3 5 4 DETAIL Z L1 NOTE 4 F P SOLDERING FOOTPRINT* DETAIL Z U MILLIMETERS MIN MAX 3.30 BSC 3.30 BSC 0.85 0.95 0.25 0.35 1.30 1.50 2.55 2.75 0.65 BSC 0.95 1.15 0.25 BSC 0.00 0.05 0.35 0.45 0.00 0.10 1.28 1.38 0.20 −−− 4X 2.75 H VIEW AA−AA 1.23 1.50 0.40 8X 3.60 0.58 8X 0.33 0.65 PITCH *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice 1 suitability of its products for any particular purpose, nor does SCILLC assume any liability to any products herein. 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