STD45NF75 N-CHANNEL 75V - 0.018 Ω -40A DPAK STripFET™ II POWER MOSFET TYPE STD45NF75 ■ ■ ■ ■ VDSS RDS(on) ID 75 V <0.024 Ω 40 A(**) TYPICAL RDS(on) = 0.018 Ω 100% AVALANCHE TESTED GATE CHARGE MINIMIZED SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX “T4") DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 3 1 DPAK TO-252 (Suffix “T4”) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH CURRENT, SWITCHING APPLICATIONS Ordering Information SALES TYPE STD45NF75T4 MARKING D45NF75 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Drain-source Voltage (VGS = 0) VDS VDGR Drain-gate Voltage (RGS = 20 kΩ) VGS Gate- source Voltage ID(**) Drain Current (continuous) at TC = 25°C ID Drain Current (continuous) at TC = 100°C IDM(•) Drain Current (pulsed) Ptot Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope dv/dt (1) Single Pulse Avalanche Energy EAS (2) Tstg Storage Temperature Tj Operating Junction Temperature (•) Pulse width limited by safe operating area. (**) Current Limited by Package April 2004 PACKAGE DPAK PACKAGING TAPE & REEL Value 75 75 ± 20 40 30 160 100 0.67 20 500 Unit V V V A A A W W/°C V/ns mJ -55 to 175 °C (1) ISD ≤40A, di/dt ≤800A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX (2) Starting Tj = 25 oC, ID = 20 A, VDD = 40V 1/12 STD45NF75 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 1.5 °C/W Rthj-pcb Thermal Resistance Junction-pcb Max see curve on page 6 °C/W 275 °C Tl Maximum Lead Temperature For Soldering Purpose (for 10 sec. 1.6 mm from case) ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20 V V(BR)DSS VGS = 0 Min. Typ. Max. 75 Unit V 1 10 µA µA ±100 nA Max. Unit 4 V 0.018 0.024 Ω Typ. Max. Unit ON (*) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS RDS(on) Static Drain-source On Resistance VGS = 10 V ID = 250 µA Min. Typ. 2 ID = 20 A DYNAMIC Symbol 2/12 Parameter Test Conditions gfs (*) Forward Transconductance VDS = 25 V Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 ID = 20 A Min. 50 S 1760 360 140 pF pF pF STD45NF75 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 37 V ID = 20 A VGS = 10 V RG = 4.7 Ω (Resistive Load, Figure 3) 15 40 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD=60 V ID=40A VGS= 10V 60 13 23 80 nC nC nC Typ. Max. Unit (see test circuit, Figure 4) ns ns SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions Min. VDD = 37 V ID = 20 A VGS = 10 V RG = 4.7Ω, (Resistive Load, Figure 3) 55 12 ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 40 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A di/dt = 100A/µs Tj = 150°C VDD = 30 V (see test circuit, Figure 5) trr Qrr IRRM Test Conditions Min. Typ. VGS = 0 120 410 7.5 Max. Unit 40 160 A A 1.5 V ns nC A (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/12 STD45NF75 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/12 STD45NF75 Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature. . Power Derating vs Tc . Max Id Current vs Tc. 5/12 STD45NF75 Thermal Resistance Rthj-a vs PCB Copper Area Max Power Dissipation vs PCB Copper Area Allowable Iav vs. Time in Avalanche The previous curve gives the safe operating area for unclamped inductive loads, single pulse or repetitive, under the following conditions: PD(AVE) = 0.5 * (1.3 * BVDSS * IAV) EAS(AR) = PD(AVE) * tAV Where: IAV is the Allowable Current in Avalanche PD(AVE) is the Average Power Dissipation in Avalanche (Single Pulse) tAV is the Time in Avalanche To derate above 25 oC, at fixed IAV, the following equation must be applied: IAV = 2 * (Tjmax - TCASE)/ (1.3 * BVDSS * Zth) Where: Zth = K * Rth is the value coming from Normalized Thermal Response at fixed pulse width equal to TAV . 6/12 STD45NF75 SPICE THERMAL MODEL Node Value CTHERM1 7-6 6 * 10-4 CTHERM2 6-5 8 * 10-3 CTHERM3 5-4 2 * 10-2 CTHERM4 4-3 6 * 10-2 CTHERM5 3-2 9.65 * 10-2 CTHERM6 2-1 6 * 10-1 RTHERM1 7-6 0.045 RTHERM2 6-5 0.105 RTHERM3 5-4 0.150 RTHERM4 4-3 0.225 RTHERM5 3-2 0.375 RTHERM6 2-1 0.600 Parameter 7/12 STD45NF75 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 3.1: Switching Time Waveform Fig. 4: Gate Charge Test Circuit Fig. 4.1: Gate Charge Test Waveform 8/12 STD45NF75 Fig. 5: Diode Switching Test Circuit Fig. 5.1: Diode Recovery Times Waveform 9/12 STD45NF75 TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.031 0.6 1 0.023 0.039 A1 C2 A H A2 C DETAIL "A" L2 D = 1 = G 2 = = = E = B2 3 B DETAIL "A" L4 0068772-B 10/12 STD45NF75 11/12 STD45NF75 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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