LH532100B CMOS 2M (256K × 8) MROM FEATURES DESCRIPTION • 262,144 words × 8 bit organization The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 32-PIN DIP 32-PIN SOP • Static operation TOP VIEW OE1/OE1/DC 1 32 VCC A16 2 31 DC A15 3 30 A17 A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE/OE A2 10 23 A10 A1 11 22 CE A0 12 21 D7 D0 13 20 D6 D1 14 19 D5 D2 15 18 D4 GND 16 17 D3 • Mask-programmable OE/OE and OE1/OE1/DC • TTL compatible I/O • Three-state outputs • Single +5 V power supply D1 TOP VIEW D2 D3 D4 32-PIN QFJ GND Figure 1. Pin Connections for DIP and SOP Packages D6 20 19 18 17 16 15 14 D0 22 12 A0 A10 23 11 A1 OE/OE 24 10 A2 A11 25 9 A3 A9 26 8 A4 A8 27 7 A5 A13 28 6 A6 A14 29 5 A7 VCC 30 31 32 1 2 3 4 A12 13 CE A15 21 A16 D7 OE1/OE1/DC • JEDEC standard EPROM pinout (DIP) 532100B-1 A17 • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 450-mil QFJ (PLCC) 32-pin, 8 × 20 mm2 TSOP (Type I) 32-pin, 400-mil TSOP (Type II) D5 • Low-power consumption: Operating: 275 mW (MAX.) Standby: 550 µW (MAX.) DC • Access time: 150 ns (MAX.) 532100B-7 Figure 2. Pin Connections QFJ (PLCC) Package 1 LH532100B CMOS 2M MROM 32-PIN TSOP (Type I) TOP VIEW A11 1 32 OE/OE A9 2 31 A10 A8 3 30 A13 4 A14 32-PIN TSOP (Type II) TOP VIEW OE1/OE1/DC 1 32 VCC A16 2 31 DC CE A15 3 30 A17 29 D7 A12 4 29 A14 5 28 D6 A7 5 28 A13 A17 6 27 D5 A6 6 27 A8 DC 7 26 D4 A5 7 26 A9 VCC 8 25 D3 A4 8 25 A11 OE1/OE1/DC 9 24 GND A3 9 24 OE/OE A16 10 23 D2 A2 10 23 A10 A15 11 22 D1 A1 11 22 CE A12 12 21 D0 A0 12 21 D7 A7 13 20 A0 D0 13 20 D6 A6 14 19 A1 D1 14 19 D5 A5 15 18 A2 D2 15 18 D4 A4 16 17 A3 GND 16 17 D3 532100B-2 NOTE: Reverse bend available on request. Figure 3. Pin Connections for TSOP (Type I) Package 2 Figure 4. Pin Connections for TSOP (Type II) Packages 532100B-3 CMOS 2M MROM LH532100B A17 30 2 3 29 28 ADDRESS BUFFER A12 4 A11 25 A10 23 A9 A8 A7 A6 26 27 5 6 MEMORY MATRIX (262,144 x 8) ADDRESS DECODER A16 A15 A14 A13 A5 7 A4 8 A3 9 A2 10 A1 11 COLUMN SELECTOR A0 12 SENSE AMPLIFIER CE BUFFER CE/CE 22 TIMING GENERATOR OUTPUT BUFFER OE/OE 24 OE BUFFER OE1/OE1/DC 1 13 D0 32 16 VCC GND 14 D1 15 D2 17 D3 18 D4 19 D5 20 D6 21 D7 NOTE: Pin numbers apply to the 32-pin DIP, SOP, QFJ, or TSOP (Type II). 532100B-4 Figure 5. LH532100B Block Diagram PIN DESCRIPTION SIGNAL PIN NAME A0 – A17 Address input D0 – D7 Data output CE OE/OE NOTE SIGNAL OE1/OE1/DC Chip Enable input Output Enable input 1 PIN NAME Output Enable input/ Don’t Care connection VCC Power supply (+5 V) GND Ground NOTE 1 NOTE: 1. Active levels of OE/OE and OE1/OE1/DC are mask-programmable. Selecting DC allows the outputs to be active for both high and low levels applied to this pin. It is recommended to apply either a HIGH or a LOW to the DC pin. TRUTH TABLE CE OE/OE OE1/OE1 MODE D0 – D7 SUPPLY CURRENT H X X Non selected High-Z Standby (ISB) L L/H X Non selected High-Z Operating (ICC) L X L/H Non selected High-Z Operating (ICC) L H/L H/L Selected DOUT Operating (ICC) NOTE: X = H or L 3 LH532100B CMOS 2M MROM ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC – 0.3 to +7.0 V Input voltage VIN – 0.3 to VCC + 0.3 V Output voltage VOUT – 0.3 to VCC + 0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg – 65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER Input ‘Low’ voltage SYMBOL CONDITIONS MIN. VIL TYP. MAX. UNIT –0.3 0.8 V 2.2 VCC + 0.3 V 0.4 V Input ‘High’ voltage VIH Output ‘Low’ voltage VOL I OL = 2.0 mA Output ‘High’ voltage VOH I OH = –400 µA Input leakage current | ILI | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 ICC1 t RC = tRC (MIN.) 50 ICC2 t RC = 1 µs 45 mA 2 ICC3 t RC = tRC (MIN.) 45 t RC = 1 µs mA 3 ICC4 40 ISB1 CE = V IL, CE = VIH 3 mA ISB2 CE = 0.2 V, CE = V CC – 0.2 V 100 µA 10 pF 10 pF Operating current Standby current Input capacitance Output capacitance CIN 2.4 V f = 1 MHz T A = 25°C COUT NOTES: 1. CE/OE/OE1 = VIH, OE/OE1 = VIL 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT Read cycle time tRC 150 Address access time tAA 150 ns Chip enable access time tACE 150 ns 70 ns NOTE ns Output enable delay time tOE 10 Output hold time tOH 10 CE to output in High-Z tCHZ 70 ns OE to output in High-Z tOHZ 70 ns ns NOTE: 1. This is the time required for the outputs to become high-impedance. 4 NOTE 1 CMOS 2M MROM LH532100B AC TEST CONDITIONS PARAMETER Input voltage amplitude RATING 0.6 V to 2.4 V Input rise/fall time 10 ns Input reference level 1.5 V Output reference level 0.8 V and 2.2 V Output load condition 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. tRC A0 - A17 tAA (NOTE) CE tACE tCHZ (NOTE) OE/OE1 OE/OE1 tOE (NOTE) D0 - D7 tOHZ tOH DATA VALID NOTE: The output data becomes valid when the last intervals tAA, tACE, or tOE have concluded. 532100B-5 Figure 6. Timing Diagram 5 LH532100B CMOS 2M MROM PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 16 0.30 [0.012] 0.20 [0.008] 41.30 [1.626] 40.70 [1.602] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 32 17 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32SOP 32-pin, 525-mil SOP 6 CMOS 2M MROM LH532100B 32TSOP (Type I) (TSOP032-P-0820) 0.30 [0.012] 0.10 [0.004] 0.50 [0.020] TYP. 32 17 18.60 [0.732] 18.20 [0.717] 1 20.30 [0.799] 19.70 [0.776] 19.00 [0.748] 16 8.20 [0.323] 7.80 [0.307] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32TSOP 2 32-pin, 8 × 20 mm TSOP (Type I) 32TSOP (Type II) (TSOP032-P-0400) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 32 17 10.40 [0.409] 12.30 [0.484] 10.00 [0.394] 11.30 [0.445] 1 11.00 [0.433] 10.60 [0.417] 16 21.20 [0.835] 20.80 [0.819] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.4375 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32TSOP400 32-pin, 400-mil TSOP (Type II) 7 LH532100B CMOS 2M MROM 32QFJ (QFJ032-P-R450) 29 21 20 30 11.40 [0.449] 1 4 12.50 [0.492] 12.30 [0.484] 10.90 [0.429] 10.10 [0.398] 14 5 13 14.00 [0.551] 15.10 [0.594] 14.90 [0.587] 0.25 [0.010] 1.20 [0.047] 1.20 [0.047] 1.27 [0.050] TYP. 3.50 [0.138] 2.30 [0.091] 3.10 [0.122] 1.90 [0.075] 0.56 [0.022] 0.36 [0.014] 13.50 [0.531] 12.70 [0.500] MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT 32QFJ450 32-pin, 450-mil QFJ (PLCC) ORDERING INFORMATION LH532100B Device Type X Package D N U T S SR 32-pin, 600-mil DIP (DIP032-P-0600) 32-pin, 525-mil SOP (SOP032-P-0525) 32-pin, 450-mil QFJ (PLCC) (QFJ032-P-R450) 32-pin, 8 x 20 mm2 TSOP (Type I) (TSOP032-P-0820) 32-pin, 400-mil TSOP (Type II) (TSOP032-P-0400) 32-pin, 400-mil TSOP (Type II) Reverse bend (TSOP032-P-0400) CMOS 2M (256K x 8) Mask-Programmable ROM Example: LH532100BD (CMOS 2M (256K x 8) Mask-Programmable ROM, 32-pin, 600-mil DIP) 532100B-6 8