LH530800A-Y FEATURES CMOS 1M (128K × 8) 3 V-Drive MROM PIN CONNECTIONS • 131,072 words × 8 bit organization • Access times: 500 ns (MAX.) at 2.6 V ≤ VCC < 4.5 V 150 ns (MAX.) at 4.5 V ≤ VCC ≤ 5.5 V • Low-power consumption: Operating: 193 mW (MAX.) Standby: 550 µW (MAX.) • Static operation • Three-state outputs • Mask-programmable control pin: Pin 24 = OE/OE • Wide range power supply: 2.6 V to 5.5 V • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP DESCRIPTION TOP VIEW 32-PIN DIP 32-PIN SOP NC 1 32 Vcc A16 2 31 NC A15 3 30 NC A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE/OE A2 10 23 A10 A1 11 22 CE A0 12 21 D7 D0 13 20 D6 D1 14 19 D5 D2 15 18 D4 GND 16 17 D3 530800A-Y-1 Figure 1. Pin Connections for DIP and SOP Packages The LH530800A-Y is a 1M-bit mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. 1 LH530800A-Y CMOS 1M Mask-Programmable ROM A16 1 A15 2 A14 28 A10 22 A9 25 A8 26 A7 4 A6 5 A5 6 A4 A3 A2 A1 MEMORY MATRIX (131,072 x 8) ADDRESS DECODER ADDRESS BUFFER A13 27 A12 3 A11 24 COLUMN SELECTOR 7 8 9 10 A0 11 SENSE AMPLIFIER CE BUFFER CE 21 TIMING GENERATOR OUTPUT BUFFER OE BUFFER OE/OE 23 30 31 VCC 15 GND 12 D0 13 D1 14 D2 16 D3 17 D4 18 D5 19 D6 20 D7 530800A-Y-2 Figure 2. LH530800A-Y Block Diagram PIN DESCRIPTION SIGNAL A0 - A16 D0 - D7 CE OE/OE PIN NAME NOTE SIGNAL Address input Data Output VCC GND NC Chip enable input Output enable input PIN NAME NOTE Power supply Ground Non connection 1 NOTE: 1. Active levels of OE/OE are mask-programmable. TRUTH TABLE CE OE/OE D0 - D7 SUPPLY CURRENT NOTE H L L X L/H H/L High-Z High-Z DOUT Standby (ISB) Operating (ICC) Operating (ICC) 1 NOTE: 1. X = H or L ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage 2 SYMBOL RATING UNIT VCC -0.3 to +7.0 V CMOS 1M Mask-Programmable ROM Input voltage LH530800A-Y VIN -0.3 to VCC +0.3 V Output voltage VOUT -0.3 to VCC +0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg -65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. VCC 2.6 Supply voltage TYP. MAX. UNIT 5.5 V DC CHARACTERISTICS (VCC = 2.6 V to 5.5 V, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Input ‘Low’ voltage VIL -0.3 0.4 V Input ‘High’ voltage VIH 0.8 × VCC VCC + 0.3 V Output ‘Low’ voltage VOL 0.4 V IOL = 400 µA Output ‘High’ voltage VOH IOH = -100 µA Input leakage current | ILI | VIN = 0 V to V CC 10 µA Output leakage current | ILO | VOUT = 0 V to V CC 10 µA 1 ICC1 tRC = 150 ns 35 mA 2 Operating current ICC2 tRC = 500 ns 18 mA 3 ICC3 tRC = 500 ns 12 mA 4 ISB1 CE = VIH 2 mA ISB2 CE = VCC - 0.2 V 100 CIN f = 1 MHz TA = 25°C 10 µA pF 10 pF UNIT NOTE Standby current Input capacitance Output capacitance COUT 0.8 × VCC NOTE V NOTES: 1. CE/OE = VIH, OE = VIL 2. 4.5 V ≤ VCC ≤ 5.5 V, outputs open 3. 3.4 V < VCC < 4.5 V, outputs open 4. 2.6 V ≤ VCC ≤ 3.4 V, outputs open AC CHARACTERISTICS (TA = 0 to +70°C) PARAMETER SYMBOL 2.6 V ≤ VCC < 4.5 V MIN. MAX. 500 4.5 V ≤ VCC ≤ 5.5 V MIN. MAX. Read cycle time tRC 150 Address access time tAA 500 150 ns Chip enable access time tACE 500 150 ns Output enable delay time tOE 200 80 ns 10 ns 10 ns Output hold time tOH CE to output in High-Z tCHZ 150 80 ns OE to output in High-Z tOHZ 150 80 ns 1 NOTE: 1. This is the time required for the output to become high-impedance. 3 LH530800A-Y CMOS 1M Mask-Programmable ROM AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input rise/fall time 0.4 V to (0.8 × VCC) V 10 ns Input/output reference level Output load condition 1.5 V 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the V CC and the GND pin. tRC A0 - A16 tAA (NOTE) CE tACE (NOTE) tCHZ tOE tOHZ OE OE (NOTE) D 0 - D7 tOH DATA VALID NOTE: Data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. Figure 3. Timing Diagram 4 530800A-Y-4 CMOS 1M Mask-Programmable ROM LH530800A-Y PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 16 0.30 [0.012] 0.20 [0.008] 41.30 [1.626] 40.70 [1.602] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 32 17 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32SOP 32-pin, 525-mil SOP 5 LH530800A-Y CMOS 1M Mask-Programmable ROM ORDERING INFORMATION LH530800A Device Type X Package -Y Low-Voltage Operation D 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) CMOS 1M (128K x 8) Mask-Programmable ROM Example: LH530800AD-Y (CMOS 1M (128K x 8) Mask-Programmable ROM, Low-Voltage Operation, 32-pin, 600-mil DIP) 6 530800A-Y-3