PRELIMINARY LH538700A FEATURES • 1,048,576 words × 8 bit organization • Access time: 100 ns (MAX.) CMOS 8M (1M × 8) MROM PIN CONNECTIONS TOP VIEW 32-PIN DIP 32-PIN SOP • Power consumption: Operating: 550 mW (MAX.) Standby: 550 µW (MAX.) • Static operation • TTL compatible I/O A19 1 32 VCC A16 2 31 A18 A15 3 30 A17 A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 • Three-state outputs A3 9 24 OE A2 10 23 A10 • Single +5 V power supply A1 11 22 CE • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 400-mil TSOP (Type II) A0 12 21 D7 D0 13 20 D6 D5 D1 14 19 D2 15 18 D4 GND 16 17 D3 538700A-1 DESCRIPTION The LH538700A is an 8M-bit mask-programmable ROM organized as 1,048,576 × 8 bits. It is fabricated using silicon-gate CMOS process technology. Figure 1. Pin Connections for DIP and SOP Packages 32-PIN TSOP (Type II) TOP VIEW A19 1 32 VCC A16 2 31 A18 A15 3 30 A17 A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 D7 D0 13 20 D6 D1 14 19 D5 D2 15 18 D4 GND 16 17 D3 NOTE: Reverse bend available on request. 538700A-2 Figure 2. Pin Connections for TSOP Package 1 LH538700A PRELIMINARY CMOS 8M MROM A19 1 A18 31 A17 30 A12 4 A11 25 A10 23 A9 A8 A7 A6 26 27 5 6 MEMORY MATRIX (1,048,576 x 8) ADDRESS DECODER ADDRESS BUFFER A16 2 A15 3 A14 29 A13 28 A5 7 A4 8 A3 9 A2 10 COLUMN SELECTOR A1 11 A0 12 SENSE AMPLIFIER CE BUFFER CE 22 TIMING GENERATOR OUTPUT BUFFER OE BUFFER OE 24 32 16 VCC GND 13 D0 14 D1 15 D2 17 D3 18 D4 19 D5 20 D6 21 D7 538700A-3 Figure 3. LH538700A Block Diagram PIN DESCRIPTION SIGNAL SIGNAL PIN NAME A0 – A19 Address input OE Output enable input D0 – D7 Data output VCC Power supply (+5 V) Chip enable input GND Ground CE 2 PIN NAME CMOS 8M MROM PRELIMINARY LH538700A TRUTH TABLE CE OE DATA OUTPUT SUPPLY CURRENT H X High-Z Standby L H High-Z Operating L L Output Operating NOTE: X = H or L. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC – 0.3 to +7.0 V Input voltage VIN –0.3 to VCC +0.3 V Output voltage VOUT –0.3 to VCC +0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg – 65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0°C to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT Input ‘Low’ voltage VIL –0.3 0.8 V Input ‘High’ voltage VIH 2.2 VCC + 0.3 V 0.4 V NOTE Output ‘Low’ voltage VOL I OL = 2.0 mA Output ‘High’ voltage VOH I OH = – 400 µA Input leakage current | ILI | V IN = 0 V to VCC Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 ICC1 t RC = 100 ns 100 mA 2 ICC2 t RC = 1 µs 90 mA 2 ISB1 CE = V IH 3 mA ISB2 CE = V CC – 0.2 V 100 µA CIN f = 1 MHz T A = 25°C 10 pF 10 pF Operating current Standby current Input capacitance Output capacitance COUT 2.4 V 10 µA NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 3 LH538700A PRELIMINARY CMOS 8M MROM AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER Read cycle time SYMBOL MIN. tRC 100 MAX. UNIT NOTE ns Address access time tAA 100 ns Chip enable access time tACE 100 ns Output enable delay time tOE Output hold time tOH CE to output in High-Z tCHZ 40 ns 1 OE to output in High-Z tOHZ 40 ns 1 50 5 ns ns NOTE: 1. This is the time required for the output to become high-impedance. AC TEST CONDITIONS PARAMETER Input voltage amplitude RATING 0.4 V to 2.6 V Input rise/fall time 10 ns Input/output reference level 1.5 V Output load condition 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the V CC pin and the GND pin. tRC A0 - A19 tAA (NOTE) CE tCHZ tACE (NOTE) OE tOHZ tOE (NOTE) D 0 - D7 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. Figure 4. Timing Diagram 4 538700A-4 CMOS 8M MROM PRELIMINARY LH538700A PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 16 0.30 [0.012] 0.20 [0.008] 41.30 [1.626] 40.70 [1.602] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 32 17 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32SOP 32-pin, 525-mil SOP 5 LH538700A PRELIMINARY CMOS 8M MROM 32TSOP (Type II) (TSOP032-P-0400) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 32 17 10.40 [0.409] 12.30 [0.484] 10.00 [0.394] 11.30 [0.445] 1 11.00 [0.433] 10.60 [0.417] 16 21.20 [0.835] 20.80 [0.819] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.4375 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32TSOP400 32-pin, 400-mil TSOP (Type II) ORDERING INFORMATION LH538700A Device Type X Package D N S SR 32-pin, 600-mil DIP (DIP032-P-0600) 32-pin, 525-mil SOP (SOP032-P-0525) 32-pin, 400-mil TSOP (Type II) (TSOP032-P-0400) 32-pin, 400-mil TSOP (Type II) Reverse bend (TSOP032-P-0400) CMOS 8M (1M x 8) Mask-Programmable ROM Example: LH538700AD (CMOS 8M (1M x 8) Mask-Programmable ROM, 32-pin, 600-mil DIP) 538700A-5 6