LH530800A FEATURES • 131,072 words × 8 bit organization • Access time: 150 ns (MAX.) CMOS 1M (128K × 8) MROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW • Power consumption: Operating: 192.5 mW (MAX.) Standby: 550 µW (MAX.) NC 1 32 Vcc A16 2 31 NC A15 3 30 NC A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 • Static operation • TTL compatible I/O • Three-state outputs A4 8 25 A11 A3 9 24 OE/OE A2 10 23 A10 A1 11 22 CE A0 12 21 D7 D0 13 20 D6 D1 14 19 D5 D2 15 18 D4 GND 16 17 D3 • Single +5 V power supply • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 450-mil QFJ (PLCC) • JEDEC standard EPROM pinout (DIP) 530800A-1 Figure 1. Pin Connections for DIP and SOP Packages VCC 3 2 1 32 31 30 NC NC 4 NC A16 TOP VIEW A15 32-PIN QFJ A12 A7 5 29 A14 A6 6 28 A13 A5 7 27 A8 A4 8 26 A9 A3 9 25 A11 A2 10 24 OE/OE A1 11 23 A10 A0 12 22 CE D0 13 21 D7 D6 D5 D4 D3 GND 14 15 16 17 18 19 20 D2 The LH530800A is a mask-programmable ROM organized as 131,072 × 8 bits (1,048,576 bits). It is fabricated using silicon-gate CMOS process technology. D1 DESCRIPTION 530800A-7 Figure 2. Pin Connections for QFJ (PLCC) Package 1 LH530800A CMOS 1M Mask-Programmable ROM A16 2 A15 3 A14 29 A10 23 A9 26 A8 27 A7 5 A6 6 MEMORY MATRIX (131,072 x 8) ADDRESS DECODER ADDRESS BUFFER A13 28 A12 4 A11 25 A5 7 COLUMN SELECTOR A4 8 A3 9 A2 10 A1 11 A0 12 SENSE AMPLIFIER CE BUFFER CE 22 TIMING GENERATOR OUTPUT BUFFER OE BUFFER OE/OE 24 32 16 VCC GND 13 D0 14 D1 15 D2 17 D3 18 D4 19 D5 20 D6 21 D7 530800A-2 Figure 3. LH530800A Block Diagram PIN DESCRIPTION SIGNAL PIN NAME A0 - A16 Address input D0 - D7 Data Output CE OE/OE NOTE Chip enable input 1 Output enable input 1 SIGNAL PIN NAME VCC Power supply (+5 V) GND Ground NC No connection NOTE: 1. Active level of OE/OE is mask-programmable. TRUTH TABLE CE OE/OE MODE D0 - D7 SUPPLY CURRENT NOTE H X Non selected High-Z Standby (ISB) 1 L L/H Non selected High-Z Operating (ICC) L H/L Selected DOUT Operating (ICC) NOTE: 1. X = H or L. 2 NOTE CMOS 1M Mask-Programmable ROM LH530800A ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC –0.3 to +7.0 V Input voltage VIN –0.3 to VCC +0.3 V Output voltage VOUT –0.3 to VCC +0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg –65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Input ‘Low’ voltage VIL –0.3 0.8 V Input ‘High’ voltage V IH 2.2 VCC + 0.3 V Output ‘Low’ voltage 0.4 V 10 µA µA 1 mA 2 mA 3 VOL I OL = 2.0 mA Output ‘High’ voltage VOH I OH = –400 µA Input leakage current | ILI | V IN = 0 V to VCC Output leakage current | ILO | V OUT = 0 V to VCC 10 ICC1 t RC = 150 ns 35 ICC2 t RC = 1 µs 25 Operating current Standby current Input capacitance Output capacitance 2.4 V ICC3 t RC = 150 ns 30 ICC4 t RC = 1 µs 20 ISB1 CE = VIH 2 mA ISB2 CE = VCC - 0.2 V 100 µA f = 1 MHz T A = 25°C 10 pF 10 pF CIN COUT NOTES: 1. CE/OE = VIH or OE = VIL 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC - 0.2 V) or 0.2 V, CE = 0.2 V, outputs open AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. 150 TYP. MAX. UNIT Read cycle time tRC Address access time tAA 150 ns Chip enable time tACE 150 ns Output enable time tOE 70 ns Output hold time tOH NOTE ns 5 ns CE to output in High-Z tCHZ 70 ns OE to output in High-Z tOHZ 70 ns 1 NOTE: 1. This is the time required for the output to become high-impedance. 3 LH530800A CMOS 1M Mask-Programmable ROM AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input rise/fall time 0.6 V to 2.4 V 10 ns Input reference level 1.5 V Output reference level 0.8 V and 2.2 V Output load condition 1TTL +100 pF tRC A0 - A16 tAA (NOTE) CE tACE (NOTE) tCHZ OE OE tOHZ tOE (NOTE) D0 - D7 DATA VALID tOH NOTE: Data becomes valid after tAA, tACE, and tOE from address input, chip enable and output enable, respectively have been met. Figure 4. Timing Diagram 4 530800A-3 CMOS 1M Mask-Programmable ROM LH530800A PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 16 0.30 [0.012] 0.20 [0.008] 41.30 [1.626] 40.70 [1.602] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 32 17 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32SOP 32-pin, 525-mil SOP 5 LH530800A CMOS 1M Mask-Programmable ROM 32QFJ (QFJ032-P-R450) 29 21 20 30 11.40 [0.449] 1 4 12.50 [0.492] 12.30 [0.484] 10.90 [0.429] 10.10 [0.398] 14 5 13 14.00 [0.551] 15.10 [0.594] 14.90 [0.587] 0.25 [0.010] 1.20 [0.047] 1.20 [0.047] 1.27 [0.050] TYP. 3.50 [0.138] 2.30 [0.091] 3.10 [0.122] 1.90 [0.075] 0.56 [0.022] 0.36 [0.014] 13.50 [0.531] 12.70 [0.500] DIMENSIONS IN MM (INCHES) MAXIMUM LIMIT MINIMUM LIMIT 32QFJ450 32-pin, 450-mil QFJ (PLCC) ORDERING INFORMATION LH530800A Device Type X Package D 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) U 32-pin, 450-mil QFJ (PLCC) (QFJ032-P-R450) CMOS 1M (128K x 8) Mask Programmable ROM Example: LH530800AD (CMOS 1M (128K x 8) Mask Programmable ROM, 32-pin, 600-mil DIP) 530800A-6 6