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16-Bit, 5MHz
Sampling A/D Converters
FEATURES
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ANALOG GROUND
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DIGITAL GROUND
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Figure 1. ADS-935 Functional Block Diagram
www.cd4power.com
Page 1 of 8
-Îx
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
+5V Supply (Pins 31, 38)
–5V Supply (Pin 37)
+12V/+15V Supply (pin 40)
–12V/–15V Supply (pin 39)
Digital Inputs (Pins 8, 9, 12, 34, 35)
Analog Input (Pin 3)
Lead Temperature (10 seconds)
PHYSICAL/ENVIRONMENTAL
LIMITS
UNITS
0 to +6
0 to –6
0 to +16V
0 to +16V
–0.3 to +VDD +0.3
±5
+300
Volts
Volts
Volts
Volts
Volts
Volts
°C
PARAMETERS
MIN.
TYP.
MAX.
UNITS
0
–55
—
—
+70
+125
°C
°C
Operating Temp. Range, Case
ADS-935MC
ADS-935MM
Thermal Impedance
Qjc
Qca
Storage Temperature Range
Package Type
Weight
—
—
–65
4
—
°C/Watt
18
—
°C/Watt
—
+150
°C
40-pin, metal-sealed, ceramic TDIP
0.56 ounces (16 grams)
FUNCTIONAL SPECIFICATIONS
(TA = +25°C, ±VCC = ±12/15V, +VDD = ±5V, 5MHz sampling rate, and a minimum 3 minute warm-up ~ unless otherwise specified.)
+25°C
ANALOG INPUT
Input Voltage Range
Unipolar
Bipolar
Input Resistance (Pin 3)
(Pin 2)
Input Capacitance
MIN.
TYP.
0 to +70°C
MAX.
MIN.
TYP.
–55 to +125°C
MAX.
MIN.
TYP.
MAX.
UNITS
—
—
—
—
—
0 to –5.5V
±2.75
400
480
10
—
—
—
—
15
—
—
—
—
—
0 to –5.5V
±2.75
400
480
10
—
—
—
—
15
—
—
—
—
—
0 to –5.5V
±2.75
400
480
10
—
—
—
—
15
Volts
Volts
7
7
pF
+2.0
—
—
—
20
—
—
—
—
50
—
+0.8
+20
–20
—
+2.0
—
—
—
20
—
—
—
—
50
—
+0.8
+20
–20
—
+2.0
—
—
—
20
—
—
—
—
50
—
+0.8
+20
–20
—
Volts
Volts
μA
μA
ns
—
—
–0.95
—
—
—
—
16
16
±1
±0.5
±0.15
±0.1
±0.1
±0.15
—
—
—
+1.0
±0.3
±0.2
±0.2
±0.3
—
—
—
–0.95
—
—
—
—
16
16
±1.5
±0.5
±0.3
±0.2
±0.2
±0.3
—
—
—
+1.0
±0.5
±0.4
±0.4
±0.5
—
—
—
–0.95
—
—
—
—
16
16
±2
±0.5
±0.5
±0.4
±0.4
±0.5
—
—
—
+1.5
±0.8
±0.6
±0.6
±0.8
—
Bits
LSB
LSB
%FSR
%FSR
%FSR
%
Bits
—
—
–87
–82
–82
–80
—
—
–87
–82
–82
–80
—
—
–82
–78
–78
–78
dB
dB
—
—
–86
–81
–81
–80
—
—
–86
–81
–81
–80
—
—
–81
–77
–76
–76
dB
dB
84
83
86
85
—
—
84
83
86
85
—
—
77
77
80
80
—
—
dB
dB
80
79
—
82
81
80
—
—
—
80
79
—
82
81
80
—
—
—
76
76
—
78
75
80
—
—
—
dB
dB
μVrms
—
–87
–85
—
–87
–85
—
–87
–82
dB
—
—
25
15
—
—
—
—
25
25
—
—
—
—
25
15
—
—
MHz
MHz
—
—
—
—
90
±400
4
2
—
—
—
—
—
—
—
—
90
±400
4
2
—
—
—
—
—
—
—
—
90
±400
4
2
—
—
—
—
dB
V/μs
ns
ps rms
—
—
5
80
200
—
—
—
—
—
—
5
80
200
—
—
—
—
—
—
5
90
200
—
—
—
—
ns
ns
MHz
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Start Convert Positive Pulse Width
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity (fin = 10kHz)
Full Scale Absolute Accuracy
Bipolar Zero Error (Tech Note 2)
Bipolar Offset Error (Tech Note 2)
Gain Error (Tech Note 2)
No Missing Codes (fin = 10kHz)
DYNAMIC PERFORMANCE
Peak Harmonics (–0.5dB)
dc to 500kHz
500kHz to 2.45MHz
Total Harmonic Distortion (–0.5dB)
dc to 500kHz
500kHz to 2.45MHz
Signal-to-Noise Ratio
(w/o distortion, –0.5dB)
dc to 500kHz
500kHz to 2.45MHz
Signal-to-Noise Ratio
(& distortion, –0.5dB)
dc to 500kHz
500kHz to 2.45MHz
Noise
Two-Tone Intermodulation
Distortion (fin = 200kHz,
240kHz, fs = 5MHz, –0.5dB)
Input Bandwidth (–3dB)
Small Signal (–20dB input)
Large Signal (–0.5dB input)
Feedthrough Rejection
(fin = 1MHz)
Slew Rate
Aperture Delay Time
Aperture Uncertainty
S/H Acquisition Time
( to ±0.001%FSR, 5.5V step)
Overvoltage Recovery Time
A/D Conversion Rate
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Page 2 of 8
-Îx
DYNAMIC PERFORMANCE (Cont.)
MIN.
+25°C
TYP.
MAX.
MIN.
0 TO +70°C
TYP.
MAX.
—
—
—
+3.2
±30
5
—
—
—
—
—
—
+3.2
±30
5
—
—
—
–55 TO +125°C
MIN.
TYP.
MAX.
UNITS
—
—
—
Volts
ppm/°C
mA
ANALOG OUTPUT
Internal Reference
Voltage
Drift
External Current
+3.2
±30
5
—
—
—
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Output Coding
+2.4
—
—
+2.4
—
—
+2.4
—
—
—
—
+0.4
—
—
+0.4
—
—
+0.4
—
—
–4
—
—
–4
—
—
–4
—
—
+4
—
—
+4
—
—
+4
(Offset) Binary / Complementary (Offset) Binary / Two's Complement / Complementary Two's Complement
Volts
Volts
mA
mA
Power Supply Ranges
+5V Supply
–5V Supply
+12V Supply
–12V Supply
+15V Supply
–15V Supply
+4.75
–4.75
+11.5
–11.5
+14.5
–14.5
+5.0
–5.0
+12.0
–12.0
+15.0
–15.0
+5.25
–5.25
+12.5
–12.5
+15.5
–15.5
+4.75
–4.75
+11.5
–11.5
+14.5
–14.5
+5.0
–5.0
+12.0
–12.0
+15.0
–15.0
+5.25
–5.25
+12.5
–12.5
+15.5
–15.5
+4.9
–4.9
+11.5
–11.5
+14.5
–14.5
+5.0
–5.0
+12.0
–12.0
+15.0
–15.0
+5.25
–5.25
+12.5
–12.5
+15.5
–15.5
Volts
Volts
Volts
Volts
Volts
Volts
Power Supply Currents
+5V Supply
–5V Supply
–12/15V Supply
+12/15V Supply
Power Dissipation
Power Supply Rejection
—
—
—
—
—
—
+200
–100
–65
+85
2.85
—
—
—
—
—
3.1
±0.07
—
—
—
—
—
—
+220
–150
–65
+85
2.85
—
—
—
—
—
3.5
±0.07
—
—
—
—
—
—
+220
–150
—
—
2.85
—
—
—
—
—
3.5
±0.07
mA
mA
mA
mA
Watts
%FSR/%V
POWER REQUIREMENTS
Footnotes:
~ All power supplies must be on before applying a start convert pulse. All
supplies and the clock (START CONVERT) must be present during warm-up
periods. The device must be continuously converting during this time.
This is the time required before the A/D output data is valid once the analog
input is back within the specified range.
When COMP. BITS (pin 35) is low, logic loading "0" will be –350μA.
A 5MHz clock with a 50nsec positive pulse width is used for all production
testing. See Timing Diagram for more details.
The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for
–55°C operation only. The minimum limits are +4.75V and –4.75V when
operating at +125°C.
Effective bits is equal to:
±12V only or ±15V only required.
(SNR + Distortion) – 1.76 +
20 log
Full Scale Amplitude
See table 2a, Setting Output Coding Selection.
Actual Input Amplitude
6.02
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-935
requires careful attention to pc-card layout and power supply
decoupling. The device's analog and digital ground systems
are connected to each other internally. For optimal performance, tie all ground pins (4, 7, 30 and 36) directly to a large
analog ground plane beneath the package.
For the best performance it is recommended to use a single
power source for both the +5V analog and +5V digital supplies.
Bypass all power supplies and the +3.2V reference output to
ground with 4.7μF tantalum capacitors in parallel with 0.1μF
ceramic capacitors. Locate the bypass capacitors as close to
the unit as possible.
2. The ADS-935 achieves its specified accuracies without the
need for external calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using
the adjustment circuitry shown in Figure 2. When using this
circuitry, or any similar offset and gain calibration hardware,
make adjustments following warm-up. To avoid interaction,
always adjust offset before gain. Tie pins 5 and 6 to ANALOG
GROUND (pin 4) if not using offset and gain adjust circuits.
www.cd4power.com
3. Pin 35 (COMP. BITS) is used to select the digital output
coding format of the ADS-935. See Tables 2a and 2b.
When this pin has a TTL logic "0" applied, it complements all
of the ADS-935’s digital outputs.
When pin 35 has a logic "1" applied, the output coding is
complementary (offset) binary. Applying a logic "0" to pin 35
changes the coding to (offset) binary. Using the MSB output
(pin 29) instead of the MSB output (pin 28) changes the
respective output codings to complementary two's
complement and two's complement.
Pin 35 is TTL compatible and can be directly driven with
digital logic in applications requiring dynamic control over
its function. There is an internal pull-up resistor on pin 35
allowing it to be either connected to +5V or left open when a
logic "1" is required.
4. To enable the three-state outputs, connect OUTPUT
ENABLE (pin 34) to a logic "0" (low). To disable, connect pin
34 to a logic "1" (high).
Page 3 of 8
-Îx
5. Applying a start convert pulse while a conversion is in
progress (EOC = logic "1") will initiate a new and probably
inaccurate conversion cycle. Data from both the interrupted
and subsequent conversions will be invalid.
6. Do not enable/disable or complement the output bits or
read from the FIFO during the conversion process (from the
rising edge of EOC to the falling edge of EOC).
7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the
input voltage exceeds that which produces an output of all
1’s or when the input equals or exceeds the voltage that
produces all 0’s. When COMP BITS is activated, the above
conditions are reversed.
INTERNAL FIFO OPERATION
The ADS-935 contains an internal, user-initiated, 18-bit, 16word FIFO memory. Each word in the FIFO contains the 16
data bits as well as the MSB and overflow bits. Pins 8 (FIFO/
DIR) and 9 (FIFO READ) control the FIFO's operation. The
FIFO's status can be monitored by reading pins 10 (FSTAT1)
and 11 (FSTAT2).
When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is
inserted into the digital data path. When pin 8 has a logic "0"
applied, the FIFO is transparent and the output data goes
directly to the output three-state register (whose operation is
controlled by pin 34 (ENABLE)). Read and write commands
to the FIFO are ignored when the ADS-935 is operated in the
"direct" mode. It takes a maximum of 20ns to switch the FIFO
in or out of the ADS-935’s digital data path.
FIFO Write and Read Modes
Once the FIFO has been enabled (pin 8 high), digital data is
automatically written to it, regardless of the status of FIFO
READ (pin 9). Assuming the FIFO is initially empty, it will
accept data (18-bit words) from the next 16 consecutive A/D
conversions. As a precaution, pin 9 (which controls the FIFO's
READ function) should not be low when data is first written to
an empty FIFO.
the FIFO immediately after the first conversion has been
completed and remains there until the FIFO is read.
If the output three-state register has been enabled (logic "0"
applied to pin 34), data from the first conversion will appear at
the output of the ADS-935. Attempting to write a 17th word
to a full FIFO will result in that data, and any subsequent
conversion data, being lost.
Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both
equal to "1"), it can be read by dropping the FIFO READ line
(pin 9) to a logic "0" and then applying a series of 15 rising
edges to the read line. Since the first data word is already
present at the FIFO output, the first read command (the first
rising edge applied to FIFO READ) will bring data from the
second conversion to the output. Each subsequent read
command/rising edge brings the next word to the output lines.
After the 15th rising edge brings the 16th data word to the
FIFO output, the subsequent falling edge on READ will update
the status outputs (after a 20ns maximum delay) to FSTAT1 =
0,
FSTAT2 = 1 indicating that the FIFO is empty.
If a read command is issued after the FIFO empties, the last
word (the 16th conversion) will remain present at the outputs.
FIFO Reset Feature
At any time, the FIFO can be reset to an empty state by putting
the ADS-935 into its "direct" mode (logic "0" applied to pin 8,
FIFO/DIR) and also applying a logic "0" to the FIFO READ
line (pin 9). The empty status of the FIFO will be indicated by
FSTAT1 going to a "0" and FSTAT2 going to a "1". The status
outputs change 40ns after applying the control signals.
FIFO Status, FSTAT1 and FSTAT2
Monitor the status of the data in the FIFO by reading the two
status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11).
CONTENTS
Empty (0 words)
<half full (<8 words)
half-full or more (r8 words)
Full (16 words)
When the FIFO is initially empty, digital data from the first
conversion (the "oldest" data) appears at the output of
FSTAT1
0
0
1
1
FSTAT2
1
0
0
1
Table 1. FIFO Delays
DELAY
PIN
TRANSITION
1
0
1
0
1
0
Direct mode to FIFO enabled
8
FIFO enabled to direct mode
8
FIFO READ to output data valid
9
FIFO READ to status update when changing
from <half full (1 word) to empty
9
FIFO READ to status update when changing
from rhalf full (8 words) to <half full (7 words)
9
FIFO READ to status update when changing
from full (16 words) to rhalf full (15 words)
9
0
Falling edge of EOC to status update when writing
first word into empty FIFO
32
1
Falling edge of EOC to status update when
changing FIFO from <half full (7 words) to
rhalf full (8 words)
32
1
Falling edge of EOC to status update when filling
FIFO with 16th word
32
www.cd4power.com
1
MIN.
TYP.
MAX.
UNITS
–
10
20
ns
–
10
20
ns
–
–
40
ns
–
–
20
ns
–
–
110
ns
–
–
190
ns
–
–
190
ns
0
–
–
110
ns
0
–
–
28
ns
0
1
0
1
1
0
Page 4 of 8
-Îx
CALIBRATION PROCEDURE
Connect the converter per Figure 2. Any offset/gain
calibration procedures should not be implemented until the
device is fully warmed up. To avoid interaction, adjust offset
before gain. The ranges of adjustment for the circuits in
Figure 2 are guaranteed to compensate for the ADS-935’s
initial accuracy errors and may not be able to compensate for
additional system errors.
A/D converters are calibrated by positioning their digital
outputs exactly on the transition point between two adjacent
digital output codes. This is accomplished by connecting
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Zero/Offset Adjust Procedure
1. Apply a train of pulses to the START CONVERT input (pin
12) so that the converter is continuously converting.
2. For zero/offset adjust, apply –42μV to the ANALOG INPUT
(pin 3).
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Gain adjusting is accomplished when the analog input
is at nominal full scale minus 1½ LSB's (+2.749874V or
–5.499874V).
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For the ADS-935, offset adjusting is normally accomplished
when the analog input is 0 minus ½ LSB (–42μV). See Table
2b for the proper bipolar output coding.
Note: Connect pin 5 to ANALOG GROUND (pin 4) for
operation without zero/offset adjustment. Connect pin 6 to
pin 4 for operation without gain adjustment.
K 7
K 7
LED's to the digital outputs and performing adjustments until
certain LED's "flicker" equally between on and off. Other
approaches employ digital comparators or microcontrollers to
detect when the outputs change from one code to the next.
3. For bipolar operation - Adjust the offset potentiometer until
the code flickers between 1000 0000 0000 0000 and 0111
1111 1111 1111 with pin 35 tied high (complementary offset
binary) or between 0111 1111 1111 1111 and 1000 0000
0000 0000 with pin 35 tied low (offset binary).
For unipolar operation - Adjust the offset potentiometer until
all outputs are 1's and the LSB flickers between 0 and 1 with
pin 35 tied high (complementary binary) or until all outputs
are 0's and the LSB flickers between 0 and 1 with pin 35 tied
low (binary).
4. For bipolar, Two's complement coding requires using
BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the trimpot
until the output code flickers between all 0’s and all 1’s.
5.)0/,!2
&OR"IPOLAR
Gain Adjust Procedure
Figure 2. Connection Diagram
Table 2a. Setting Output Coding Selection (Pin 35)
OUTPUT FORMAT
PIN 35 LOGIC LEVEL
Complementary (Offset) Binary
1
(Offset) Binary
0
Complementary Two’s Complement
(Using MSB, pin 29)
1
Two’s Complement
(Using MSB, pin 29)
0
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1. For gain adjust, for bipolar apply +2.749874V and for unipolar mode 5.499874V to the ANALOG INPUT (pin 3).
2. Adjust the gain potentiometer until all output bits are 0’s and
the LSB flickers between a 1 and 0 with pin 35 tied high
(complementary (offset) binary) or until all output bits are 1’s
and the LSB flickers between a 1 and 0 with pin 35 tied low
((offset) binary).
3. For bipolar, Two's complement coding requires using
BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the gain
trimpot until the output code flickers equally between 0111
1111 1111 1111 and 0111 1111 1111 1110.
4. To confirm proper operation of the device, vary the applied
input voltage to obtain the output coding listed in Table 2b.
Page 5 of 8
-Îx
Table 2b. Output Coding
COMP. BINARY
BINARY
COMP. TWO'S COMP.
INPUT
RANGE
UNIPOLAR
MSB
LSB MSB
LSB
0 to –5.5V
SCALE
0 –1 LSB
–0.000084 1111 1111 1111 1111 0000 0000 0000 0000
LSB "1" to "0"
LSB "0" to "1"
0 –1 1/2 LSB
–0.000126
0 – 1/8 FS
–0.687500 1110 0000 0000 00000 0001 1111 1111 1111
0 – 1/4 FS
–1.375000 1100 0000 0000 00000 0011 1111 1111 1111
–1/2 FS – 1/2LSB –2.749958 1000 0000 0000 00000 0111 1111 1111 1111
–1/2 LSB
–2.750000 0111 1111 1111 11111 1000 000 000 00000
–3/4 FS
–4.125000 0100 0000 0000 00000 1011 1111 1111 1111
–7/8 FS
–4.812500 0010 0000 0000 00000 1101 1111 1111 1111
–FS +1 LSB
–5.499916 0000 0000 0000 00011 1111 1111 1111 11100
LSB "0" to "1"
LSB "1" to "0"
–FS + 1/2 LSB
–5.499958
–FS
–5.500000 0000 0000 0000 00000 1111 1111 1111 1111
OFFSET BINARY
COMP. OFF. BIN.
TWO'S COMP.
MSB
LSB
0111 1111 1111 11111
LSB "1" to "0"
0110 0000 0000 00000
0100 0000 0000 00000
0000 0000 0000 00000
1111 1111 1111 1111
1100 0000 0000 00000
1010 0000 0000 00000
1000 0000 0000 00011
LSB "0" to "1"
1000 0000 0000 00000
TWO'S COMP.
MSB
LSB
1000 0000 0000 0000
LSB "0" to "1"
1001 1111 1111 1111
1011 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
0011 1111 1111 1111
0101 1111 1111 1111
0111 1111 1111 1110
LSB "1" to "0"
0111 1111 1111 1111
INPUT
RANGE
BIPOLAR
±2.75V
SCALE
+2.749916
+FS –1 LSB
+2.749874 +FS –1 1/2 LSB
+2.062500
+3/4 FS
+1.375000
+1/2 FS
0.000000
0
–0.000084
–1 LSB
–1.375000
–1/2 FS
–2.062500
–3/4 FS
–2.749916
–FS +1 LSB
–2.749958 –FS + 1/2 LSB
–2.750000
–FS
COMP. TWO'S COMP.
THERMAL REQUIREMENTS
underneath the package. Devices should be soldered to
boards rather than "socketed", and of course, minimal air
flow over the surface can greatly help reduce the package
temperature.
All DATEL sampling A/D converters are fully characterized
and specified over operating temperature (case) ranges of 0 to
+70°C and –55 to +125°C. All room-temperature (TA = +25°C)
production testing is performed without the use of heat sinks or
forced-air cooling. Thermal impedance figures for each device
are listed in their respective specification tables.
In more severe ambient conditions, the package/junction
temperature of a given device can be reduced dramatically
(typically 35%) by using one of DATEL's HS Series heat
sinks. See Ordering Information for the assigned part
number. See page 1-183 of the DATEL Data Acquisition
Components Catalog for more information on the HS Series.
Request DATEL Application Note AN-8, "Heat Sinks for DIP
Data Converters," or contact DATEL directly, for additional
information.
These devices do not normally require heat sinks, however,
standard precautionary design and layout procedures should
be used to ensure devices do not overheat. The ground and
power planes beneath the package, as well as all pcb signal
runs to and from the device, should be as heavy as possible
to help conduct heat away from the package. Electrically
insulating, thermally-conductive "pads" may be installed
N
N+1
N+2
N+3
START
CONVERT
Acquisition
A
q s
Time
e
75ns
5 s typ.
y
20ns
0 s typ.
y
INTERNAL S/H
Hold
od
125ns typ.
p
20ns
2
n typ.
t p
50ns
0 s typ.
y
EOC
110ns typ.
p
Conversion
o v r o Time
Tm
150ns
1
0 s typ.
y
20ns
0 s typ.
y .
OUTPUT
DATA
Data N-4 Valid
Data N-3 Valid
Data N-2 Valid
Invalid
Data
50ns typ.
Data N-1 Valid
Invalid
Data
NOTES:
1. Scale is approximately 20ns per didsion.fs = 5MHz
2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data from the
first conversion to appear at the output of the A/D.
Figure 3. ADS-935 Timing Diagram
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Page 6 of 8
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7
5MHZ
8
14
B1
SG4
SG3
SG2
SG1
26
24
22
20
18
16
14
12
10
8
6
4
2
50
R6
P2
3
2
0.1μF
3
2
J1
4
7
2
6
5
AGND
C13
2.2μF
AGND
C11
2.2μF
L1
1
SG5
20mH
L4
20mH
L3
20mH
L2
+5VA
–5VA
+5VD
+5VF
AGND
2
AGND
OFFSET
ADJUST
AGND
C2
2.2μF
C1
2.2μF
20mH
3.3k
R3
C9
2.2μF
DGND
2.2μF
C7
DGND
C10
1 33pF
2
1
74HCT74
U1
4
+5VF
6
R2
+15V DGND
+5VA
–15V
–5VA
+5VD
3 2 1
DGND
DGND
C6
2.2μF
+5VF
25
23
21
19
17
15
13
11
9
7
5
3
1
AR1
C5
DGND
START CONVERT
7
1
X1
13
8
9
14
74HCT74
U1
10
DGND
11
12
AGND
DGND
2
AGND
+5VF
B2
ANALOG INPUT
AMPLIFIER
OPTION
AGND
R1
3
1
–5VA
R4
20k
+5VA
DGND
SG9
RD
FIF
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
B9
B10
B11
B12
B13
B14
B15
LSB
START
FSTAT2
FSTAT1
READ
FIFO/DIR
DGND
GAIN
OFFSET
AGND
ANA IN
AGND
UUT
U6
2
3
1
–5VA
R5
20k
+5VA
GAIN ADJUST
+5VF
DGND
38
39
40
AGND
12
13
3
EOC
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
+5VD
COMP
3
FST1
7 74HC86
U5
14
74HC86
8
U5
FST2
U5
DGND
+5VF
9
10
2
1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
–5VA
+5VA
DGND
C15
0.1μF
74HC86
B8
B7
B6
B5
B4
B3
B2
MSB
MSB
DGND
+5VD
EOC
OF
ENABLE
COMP
36
-5VA 37
+5VA
–12/–15V
+12/+15V
C4
2.2μF
ADS-935
+3.2VREF
AGND
C3
0.1μF
74HC86
4
U5 6 START
CONVERT
5
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
–15V
–5VA
+15V
+5VA
SG6
SG8
SG7
AB2
AB1
C16
0.1μF
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
DGND
C8
0.1μF
+5VF
DGND
C17
0.1μF
+5VF
AB7
AB6
AB5
AB4
AB3
DGND A
+5VF
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
U2
10
U3
10
1
U4
10
1
11
1
74HCT573
20
11
74HCT573
20
11
74HCT573
20
DGND
19
18
17
16
15
14
13
12
19
18
17
16
15
14
13
12
B9
B10
B11
B12
B13
B14
B15
+5VD
FIF
RD
DGND
COMP
START
B16 (LSB)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1(MSB)
AGND
DGND
1
3
5
7
9
1 2 3
1 2 3
1 2 3
J5
J4
J3
FIFO/DIR
READ
COMPLIM
ENABLE
FST2
FST1
FIF/DIR
N.C.
READ
COMPLIM
ENABLE
DGND
DGND
DGND
DGND
DGND
DGND
DGND
EOC
OVRFLW
1 2 3 J2
2
4
6
8
10
12 11
14 13
16 15
18 17
P1
20 19
22 21
24 23
26 25
28 27
30 29
32 31
B1B MSB
DGND
AGND
C21
2.2μF
+5VA
C12
2.2μF
–5VA
AGND
C14
2.2μF
+5VD
34 33
C20
0.1μF
+5VA
C19
0.1μF
–5VA
DGND
AGND
0.1μF
0.1μF
C18
0.1μF
+5VD
B16 (LSB)
DGND
B8
B7
B6
B5
B4
B3
B2
B1 (MSB)
DGND
19 B1B MSB
18 OVRFLW
17
16
15
14
13
12
-Îx
Preliminary Evaluation Board - Modified ADS-B933 to include ±12V or ±15V Supplies to U6
Figure 4. ADS-935 Evaluation Board Schematic.
Page 7 of 8
-Îx
MECHANICAL DIMENSIONS INCHES (mm)
$IMENSION4OLERANCESUNLESSOTHERWISEINDICATED
PLACEDECIMAL88
PLACEDECIMAL888
,EAD-ATERIAL+OVARALLOY
,EAD&INISHMICROINCHESMINIMUMGOLDPLATING
OVERMICROINCHESNOMINALNICKELPLATING
490
-!8
0).).$%8
/.4/0
-!8
3%!4).'
0,!.%
ORDERING INFORMATION
MODEL
ADS-935MC
935MM
OPERATING
TEMP. RANGE
0 to +70°C
–55 to +125°C
ACCESSORIES
ADS-
ADS-B935
HS-40
Evaluation Board (without ADS-935)
Heat Sink for all ADS-935 models
Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead
Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL.
C&D Technologies Ltd. Milton Keynes, United Kingdom
Tel: 44-(0)-1908-615232 E-mail: [email protected]
C&D Technologies S.a.r.l. Montigny Le Bretonneux, France
Tel: 33-(0)1-34-60-01-01 E-mail: [email protected]
C&D Technologies (DATEL), Inc.
11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: (508) 339-3000
(800) 233-2765 Fax: (508) 339-6356
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E-mail: [email protected]
ISO 9001:2000 REGISTERED
DS-0367
05/05
C&D Technologies GmbH München, Germany
Tel: 49-(0)-89-544334-0 E-mail: [email protected]
C&D Technologies KK
K Tokyo and Osaka, Japan
Tel: 81-3-3779-1031, 6-6354-2025 E-mail: [email protected], [email protected]
C&D Technologies China, Shanghai, China
Tel: 011-86-21-50273678 E-mail: [email protected]
C&D Technologies (DATEL) makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do
not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered C&D Technologies, Inc. trademark.
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