SSM9973GM
Dual N-channel Enhancement-mode Power MOSFETs
BVD2
Simple drive requirement
D2
Lower gate charge
D1
D1
Fast switching characteristics
R
I
G2
S2
Pb-free; RoHS compliant.
SO-8
S1
BVDSS
60V
R DS(ON)
80mΩ
ID
3.9A
G1
DESCRIPTION
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching, ruggedized
device design, low on-resistance and cost-effectiveness.
D2
D1
G2
G1
The SSM9973M is in an SO-8 package, which is widely preferred for
commercial and industrial surface mount applications. This device is
suitable for low voltage applications such as DC/DC converters.
S1
S2
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
Rating
Units
60
V
± 20
V
3
3.9
A
3
2.5
A
Continuous Drain Current
Continuous Drain Current
1
IDM
Pulsed Drain Current
20
A
PD @ TA=25°C
Total Power Dissipation
2
W
Linear Derating Factor
0.016
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
THERMAL DATA
Symbol
Rthj-a
12/10/2004 Rev.2.03
Parameter
Thermal Resistance Junction-ambient
3
www.SiliconStandard.com
Max.
Value
Unit
62.5
°C/W
1 of 5
SSM9973GM
o
ELECTRICAL CHARACTERISTICS @ Tj = 25 C (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
60
-
-
V
BVDSS
Drain-Source Breakdown Voltage
∆ BV DSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
-
0.06
-
V/°C
RDS(ON)
Static Drain-Source On-Resistance2
VGS=10V, ID=3.9A
-
-
80
mΩ
VGS=4.5V, ID=2A
-
-
100
mΩ
VDS=VGS, ID=250uA
1
-
3
V
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VDS=10V, ID=3.9A
-
3.5
-
S
o
VDS=60V, VGS=0V
-
-
1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=48V ,VGS=0V
-
-
25
uA
Gate-Source Leakage
VGS= ± 20V
-
-
±100
nA
ID=3.9A
-
8
13
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=250uA
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=48V
-
2
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
4
-
nC
VDS=30V
-
8
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=1A
-
4
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω , VGS=10V
-
20
-
ns
tf
Fall Time
RD=30Ω
-
6
-
ns
Ciss
Input Capacitance
VGS=0V
-
700
1120
pF
Coss
Output Capacitance
VDS=25V
-
80
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
50
-
pF
Min.
Typ.
SOURCE-DRAIN DIODE
Symbol
Parameter
2
Test Conditions
Max. Units
VSD
Forward On Voltage
IS=3.9A, VGS=0V
-
-
1.2
V
trr
Reverse Recovery Time
IS=3.9A, VGS=0V,
-
28
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
35
-
nC
Notes:
1.Pulse width limited by maximum junction temperature.
2.Pulse width <300us, duty cycle <2%.
3.Surface-mounted on 1 in2 copper pad of FR4 board ; 135°C/W when mounted on minimum copper pad.
12/10/2004 Rev.2.03
www.SiliconStandard.com
2 of 5
SSM9973GM
40
30
30
25
20
15
10
20
15
10
V G =3.0V
5
V G =3.0V
5
0
0
0
1
2
3
4
5
6
7
8
0
1
V DS , Drain-to-Source Voltage (V)
4
5
6
7
8
2.5
I D =3.9A
I D =3.9A
o
T A =25 C
V G =10V
2.0
Normalized RDS(ON)
90
85
RDS(ON) (mΩ )
3
Fig 2. Typical Output Characteristics
95
80
75
1.5
1.0
0.5
70
0.0
3
5
7
9
11
-50
0
Fig 3. On-Resistance vs. Gate Voltage
3
2
VGS(th) (V)
2.5
o
T j =150 C
100
150
Fig 4. Normalized On-Resistance
vs. Junction Temperature
4
2
50
T j , Junction Temperature ( o C)
V GS , Gate-to-Source Voltage (V)
IS(A)
2
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
T j =25 o C
1
1.5
1
0
0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-50
0
Fig 5. Forward Characteristic of
Reverse Diode
50
100
150
T j ,Junction Temperature ( o C)
V SD , Source-to-Drain Voltage (V)
12/10/2004 Rev.2.03
10V
6.0V
5.0V
4.5V
T A =150 o C
25
ID , Drain Current (A)
ID , Drain Current (A)
10V
6.0V
5.0V
4.5V
T A =25 o C
35
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
www.SiliconStandard.com
3 of 5
SSM9973GM
VGS , Gate to Source Voltage (V)
14
f=1.0MHz
10000
I D =3.9A
12
V DS =30V
V DS =38V
V DS =48V
10
1000
Ciss
C (pF)
8
6
100
Coss
4
Crss
2
0
0
4
8
12
16
10
20
1
5
Fig 7. Gate Charge Characteristics
13
17
21
25
29
Fig 8. Typical Capacitance Characteristics
1
Normalized Thermal Response (R thja)
100
10
ID (A)
9
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
1ms
1
10ms
100ms
1s
0.1
o
T A =25 C
Single Pulse
Duty factor=0.5
0.2
0.1
0.1
0.05
PDM
0.02
t
T
0.01
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
0.01
Single Pulse
Rthja=135℃
℃ /W
DC
0.01
0.001
0.1
1
10
100
1000
0.0001
0.001
0.01
V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
12/10/2004 Rev.2.03
Charge
Q
Fig 12. Gate Charge Waveform
www.SiliconStandard.com
4 of 5
SSM9973GM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
12/10/2004 Rev.2.03
www.SiliconStandard.com
5 of 5