SSM6679GM
P-CHANNEL ENHANCEMENT MODE
POWER MOSFET
PRODUCT SUMMARY
D
D
Simple Drive Requirement
Low On-resistance
Fast Switching Characteristic
D
D
G
SO-8
S
S
BVDSS
-30V
RDS(ON)
9mΩ
ID
-14A
S
DESCRIPTION
The advanced power MOSFETs from Silicon Standard Corp.
provide the designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.
D
G
The SO-8 package is universally preferred for all commercialindustrial surface mount applications and suited for low voltage
applications such as DC/DC converters.
S
Pb-free; RoHS-compliant
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID@TA=25℃
ID@TA=70℃
Rating
Units
-30
V
± 25
V
3
-14
A
3
-8.9
A
Continuous Drain Current
Continuous Drain Current
1
IDM
Pulsed Drain Current
-50
A
PD@TA=25℃
Total Power Dissipation
2.5
W
Linear Derating Factor
0.02
W/℃
TSTG
Storage Temperature Range
-55 to 150
℃
TJ
Operating Junction Temperature Range
-55 to 150
℃
THERMAL DATA
Symbol
Rthj-a
08/10/2007 Rev.1.00
Parameter
Thermal Resistance Junction-ambient
3
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Max.
Value
Unit
50
℃/W
1
SSM6679GM
ELECTRICAL CHARACTERISTICS
o
(TJ=25 C unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
-30
-
-
V
BVDSS
Drain-Source Breakdown Voltage
ΔBVDSS/ΔTj
Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=-1mA
-
-0.03
-
V/℃
RDS(ON)
Static Drain-Source On-Resistance2
VGS=-10V, ID=-14A
-
-
9
mΩ
VGS=-4.5V, ID=-11A
-
-
13
mΩ
VDS=VGS, ID=-250uA
-1
-
-3
V
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VDS=-10V, ID=-14A
-
26
-
S
o
VDS=-30V, VGS=0V
-
-
-1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=-24V, VGS=0V
-
-
-25
uA
Gate-Source Leakage
VGS= ± 25V
-
-
±100
nA
ID=-14A
-
37
60
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=-250uA
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=-24V
-
3
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=-4.5V
-
25
-
nC
VDS=-15V
-
13
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=-1A
-
11
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω,VGS=-10V
-
58
-
ns
tf
Fall Time
RD=15Ω
-
43
-
ns
Ciss
Input Capacitance
VGS=0V
-
2860 4580
pF
Coss
Output Capacitance
VDS=-25V
-
950
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
640
-
pF
Min.
Typ.
IS=-2A, VGS=0V
-
-
-1.2
V
SOURCE-DRAIN DIODE
Symbol
VSD
Parameter
Test Conditions
2
Forward On Voltage
2
Max. Units
trr
Reverse Recovery Time
IS=-14A, VGS=0V,
-
48
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
46
-
nC
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board ; 125 ℃/W when mounted on Min. copper pad.
08/10/2007 Rev.1.00
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2
SSM6679GM
280
150
-10V
-7.0V
T A = 25 C
-ID , Drain Current (A)
240
200
-5.0V
160
-10V
-7.0V
-5.0V
T A = 150 o C
-ID , Drain Current (A)
o
-4.5V
120
80
-4.5V
100
50
V G = -3.0 V
V G = -3.0 V
40
0
0
0
1
2
3
4
0
5
1
2
3
4
5
6
-V DS , Drain-to-Source Voltage (V)
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
14
1.8
I D = -11 A
T A =25 ℃
I D = -14 A
V G =-10V
1.6
Normalized R DS(ON)
RDS(ON) (mΩ)
12
10
1.4
1.2
1.0
8
0.8
0.6
6
3
5
7
9
-50
11
0
50
100
150
T j , Junction Temperature ( o C)
-V GS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
14
3
12
10
-VGS(th) (V)
2
-IS(A)
8
T j =25 o C
T j =150 o C
6
1
4
2
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-50
-V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
08/10/2007 Rev.1.00
0
50
100
150
T j , Junction Temperature ( o C)
Fig 6. Gate Threshold Voltage v.s.
Junction Temperature
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3
SSM6679GM
f=1.0MHz
10000
-VGS , Gate to Source Voltage (V)
12
I D = - 14 A
V DS = -24V
10
Ciss
C (pF)
8
6
Coss
1000
Crss
4
2
100
0
0
20
40
60
1
80
5
9
Q G , Total Gate Charge (nC)
Fig 9. Gate Charge Characteristics
17
21
25
29
Fig 10. Typical Capacitance Characteristics
1
Normalized Thermal Response (Rthja)
100
1ms
10
10ms
-ID (A)
13
-V DS , Drain-to-Source Voltage (V)
1
100ms
1s
0.1
o
T A =25 C
Single Pulse
DC
0.01
Duty factor=0.5
0.2
0.1
0.1
0.05
0.02
PDM
0.01
t
0.01
T
Single Pulse
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja=125oC/W
0.001
0.1
1
10
100
0.0001
0.001
0.01
-V DS , Drain-to-Source Voltage (V)
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 7. Maximum Safe Operating Area
Fig 8. Effective Transient Thermal Impedance
VG
VDS
90%
QG
-4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Charge
Fig 11. Switching Time Waveform
08/10/2007 Rev.1.00
Q
Fig 12. Gate Charge Waveform
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4
SSM6679GM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
08/10/2007 Rev.1.00
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5