NEC 2SK3294-ZJ

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK3294
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
ORDERING INFORMATION
The 2SK3294 is N-channel MOS FET device that features a
low on-state resistance and excellent switching characteristics,
and designed for high voltage applications such as DC/DC
converter, actuator driver.
PART NUMBER
PACKAGE
2SK3294
TO-220AB
2SK3294-S
TO-262
2SK3294-ZJ
TO-263(MP-25ZJ)
FEATURES
• Gate voltage rating ±30 V
• Low on-state resistance
(TO-220AB)
RDS(on) = 160 mΩ MAX. (VGS = 10 V, ID = 10 A)
• Low input capacitance
Ciss = 1500 pF TYP. (VDS = 10 V, VGS = 0 V)
• Avalanche capability rated
• Built-in gate protection diode
• Surface mount device available
ABSOLUTE MAXIMUM RATINGS (T A = 25°C)
(TO-262)
Drain to Source Voltage (VGS = 0 V)
VDSS
250
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±30
V
Drain Current (DC) (TC = 25°C)
ID(DC)
±20
A
ID(pulse)
±60
A
Drain Current (Pulse)
Note1
Total Power Dissipation (TC = 25°C)
PT1
100
W
Total Power Dissipation (TA = 25°C)
PT2
1.5
W
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
−55 to +150
°C
Single Avalanche Current
Note2
Single Avalanche Energy
Note2
IAS
20
A
EAS
150
mJ
(TO-263)
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, VDD = 150 V, RG = 25 Ω, VGS = 20 V→0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D14061EJ1V0DS00 (1st edition)
Date Published August 2001 NS CP (K)
Printed in Japan
©
1999,2001
2SK3294
ELECTRICAL CHARACTERISTICS (T A = 25°C)
Characteristics
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
100
µA
±10
µA
4.5
V
Zero Gate Voltage Drain Current
IDSS
VDS = 250 V, VGS = 0 V
Gate Leakage Current
IGSS
VGS = ±30 V, VDS = 0 V
Gate Cut-off Voltage
VGS(off)
VDS = 10 V, ID = 1 mA
2.5
Forward Transfer Admittance
| yfs |
VDS = 10 V, ID = 10 A
6.0
Drain to Source On-state Resistance
RDS(on)
VGS = 10 V, ID = 10 A
120
Input Capacitance
Ciss
VDS = 10 V
1500
pF
Output Capacitance
Coss
VGS = 0 V
360
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
220
pF
Turn-on Delay Time
td(on)
VDD = 125 V , ID = 10 A
24
ns
Rise Time
tr
VGS = 10 V
78
ns
Turn-off Delay Time
td(off)
RG = 10 Ω
110
ns
Fall Time
tf
60
ns
Total Gate Charge
QG
VDD = 200 V
57
nC
Gate to Source Charge
QGS
VGS = 10 V
8
nC
Gate to Drain Charge
QGD
ID = 20 A
36
nC
Body Diode Forward Voltage
VF(S-D)
IF = 20 A, VGS = 0 V
1.0
V
Reverse Recovery Time
trr
IF = 20 A, VGS = 0 V
340
ns
Reverse Recovery Charge
Qrr
di/dt = 50 A/µs
2.1
µC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
S
mΩ
160
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
PG.
50 Ω
VDD
VGS = 20 V → 0 V
RG
PG.
VGS
VGS
Wave Form
0
90%
ID
VGS
0
ID
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
2
IG = 2 mA
RL
50 Ω
VDD
10%
0 10%
Wave Form
τ
VDD
PG.
90%
BVDSS
VDS
ID
90%
VDD
ID
IAS
VGS
10%
Data Sheet D14061EJ1V0DS
tr td(off)
td(on)
ton
tf
toff
2SK3294
TYPICAL CHARACTERISTICS (T A = 25°C)
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
100
60
10
ID - Drain Current - A
ID - Drain Current - A
50
40
30
20
Tch = 125˚C
75˚C
25˚C
-25˚C
1
0.1
0.01
10
0
10
5
0
VGS = 10 V
Pulsed
15
20
VDS = 10 V
Pulsed
0.001
0
VDS - Drain to Source Voltage - V
|yfs| - Forward Transfer Admittance - S
VGS(off) - Gate Cut-off Voltage - V
4.0
3.0
2.0
1.0
0
25
50
75
100 125 150
4A
200
100
0
4
8
12
16
VGS - Gate to Source Voltage - V
20
RDS(on) - Drain to Source On-state Resistance - mΩ
RDS(on) - Drain to Source On-state Resistance -mΩ
ID = 20 A
10 A
0
10
12
VDS = 10 V
Pulsed
Tch = −25˚C
25˚C
75˚C
125˚C
10
1
0.1
0.01
0.01
0.1
10
1
100
ID- Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
500
Pulsed
300
8
100
Tch - Channel Temperature - ˚C
400
6
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
VDS = 10 V
ID = 1 mA
−50 −25
4
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
5.0
2
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
500
VGS = 10 V
Pulsed
400
300
200
100
0
0.1
1
10
100
ID - Drain Current - A
Data Sheet D14061EJ1V0DS
3
2SK3294
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
RDS (on) - Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
100
ISD - Diode Forward Current - A
400
300
ID = 20 A
200
10 A
100
0
−50
0
VGS = 10 V
Pulsed
100
150
50
VGS = 10 V
10
0V
1
0.1
Pulsed
0.01
0.0
0.5
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
1000
td(on), tr, td(off), tf - Switching Time - ns
Ciss, Coss, Crss - Capacitance - pF
10000
Ciss
1000
Coss
Crss
VGS = 0 V
f = 1 MHz
10
0.1
10
100
tr
td(off)
100
tf
td(on)
10
1
0.1
1
1.5
VSD - Source to Drain Voltage - V
Tch - Channel Temperature - ˚C
100
1.0
VDD = 125 V
VGS = 10 V
RG = 10 Ω
10
100
1
1000
ID - Drain Current - A
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
VDS - Drain to Source Voltage - V
trr - Reverse Recovery Time - ns
1000
100
10
1
0.1
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
12
360
VGS
10
300
VDD = 200 V
125 V
8
240
50 V
10
VDS
2
60
100
ID - Drain Current - A
4
4
120
di/dt = 50 A/ µs
VGS = 0 V
1
6
180
Data Sheet D14061EJ1V0DS
ID = 20 A
0
0
10
20
30
40
QG - Gate Charge - nC
50
0
60
VGS - Gate to Source Voltage - V
VDS - Drain to Source Voltage - V
2SK3294
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
140
100
80
60
40
20
0
0
20
40
60
80
120
100
80
60
40
20
0
100 120 140 160
0
20
40
60
80
100 120 140 160
TC - Case Temperature - ˚C
Tch - Channel Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
ID(pulse)
)
(on
DS
R
d
ite
Lim
ID(DC)
10
Po
we
r
0.1
PW
10
0µ
s
1m
3m s
10 s
m
DC s
Di
ss
ipa
tio
n
1
=1
0µ
s
Lim
ite
d
TC = 25˚C
Single Pulse
1
10
100
1000
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100
Rth(ch-A) = 83.3˚C/W
rth(t) - Transient Thermal Resistance - ˚C/W
ID - Drain Current - A
100
10
1
Rth(ch-C) = 1.25˚C/W
0.1
0.01
10 µ
Single Pulse
100 µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - sec
Data Sheet D14061EJ1V0DS
5
2SK3294
SINGLE AVALANCHE ENERGY
DERATING FACTOR
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
IAS = 20 A
EA
S=
10
15
0m
J
1
0.01
VDD = 150 V
VGS = 20 V → 0 V
RG = 25 Ω
0.1
1
Energy Derating Factor - %
IAS - Single Avalanche Current - A
100
10
L - Inductive Load - mH
6
VDD = 150 V
RG = 25 Ω
VGS = 20 V → 0 V
IAS ≤ 20 A
100
80
60
40
20
0
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - ˚C
Data Sheet D14061EJ1V0DS
2SK3294
PACKAGE DRAWINGS (Unit: mm)
4.8 MAX.
3.0±0.3
10.6 MAX.
φ 3.6±0.2
10 TYP.
1.3±0.2
4
1
1 2 3
3
12.7 MIN.
6.0 MAX.
1.3±0.2
1.3±0.2
0.75±0.3
2.54 TYP.
0.5±0.2
0.75±0.1
2.54 TYP.
2
1.3±0.2
0.5±0.2
2.8±0.2
2.54 TYP.
2.8±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
2.54 TYP.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
3)TO-263 (MP-25ZJ)
4.8 MAX.
12.7 MIN.
4
15.5 MAX.
5.9 MIN.
10.0 TYP.
1.0±0.5
2)TO-262
8.5±0.2
1)TO-220AB (MP-25)
EQUIVALENT CIRCUIT
4.8 MAX.
10 TYP.
Drain
1.3±0.2
2
3
5.7±0.4
1
8.5±0.2
1.0±0.5
4
1.4±0.2
0.7±0.2
.
YP
R
0.5
2.54 TYP.
2.8±0.2
2.54 TYP.
Body
Diode
Gate
T
R
0.8
Gate
Protection
Diode
.
P
TY
Source
0.5±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
Data Sheet D14061EJ1V0DS
7
2SK3294
• The information in this document is current as of August, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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M8E 00. 4