AD AD1881A

a
AC’97 SoundMAX® Codec
AD1881A
AC’97 2.1 FEATURES
Variable Sample Rate
True Line-Level Output
Supports Secondary Codec Modes
ENHANCED FEATURES
Mobile Low Power Mixer Mode
Digital Audio Mixer Mode
Full Duplex Variable 8 kHz to 48 kHz Sampling Rate
with 1 Hz Resolution
PHAT™ Stereo 3D Stereo Enhancement
Split Power Supplies (3.3 V Digital/5 V Analog)
Extended 6-Bit Master Volume Control
Audio Amp Power-Down Signal
AC’97 FEATURES
Designed for AC’97 Analog I/O Component
48-Lead LQFP Package
Multibit ⌺⌬ Converter Architecture for Improved
S/N Ratio Greater than 90 dB
16-Bit Stereo Full-Duplex Codec
Four Analog Line-Level Stereo Inputs for Connection
from LINE, CD, VIDEO, and AUX
Two Analog Line-Level Mono Inputs for Speakerphone
and PC BEEP
Mono MIC Input Switchable from Two External
Sources
High Quality CD Input with Ground Sense
Stereo Line-Level Output
Mono Output for Speakerphone or Internal Speaker
Power Management Support
FUNCTIONAL BLOCK DIAGRAM
CS0 CS1
EAPD
MODE
AD1881A
MODE/SYNCHRONIZER
MIC1
0dB/
20dB
MIC2
LINE_IN
SELECTOR
AUX
CD
VIDEO
PGA
16-BIT
⌺⌬ A/D
CONVERTER
PGA
16-BIT
⌺⌬ A/D
CONVERTER
RESET
PHONE_IN
SYNC
SAMPLE
RATE
GENERATORS
MV
⌺
G
A
M
⌺
LNLVL_OUT_L
⌺
G
A
M
G
A
M
G
A
M
G
A
M
G
A
M
AC LINK
MONO_OUT
SDATA_OUT
⌺
POP
LINE_OUT_L
PHAT
STEREO
MV
⌺
⌺
⌺
⌺
⌺
⌺
NC
D
A
M
LINE_OUT_R
MV
⌺
BIT_CLK
PHAT
STEREO
⌺
⌺
⌺
⌺
⌺
⌺
NC
G
A
M
16-BIT
⌺⌬ D/A
CONVERTER
G
A
M
16-BIT
⌺⌬ D/A
CONVERTER
⌺
SDATA_IN
⌺
POP
LNLVL_OUT_R
A
M
PC_BEEP
G = GAIN
A = ATTENUATE
M = MUTE
MV = MASTER VOLUME
NC = NO CONNECT
OSCILLATORS
XTL_OUT
XTL_IN
SoundMAX is a registered trademark and PHAT is a trademark of Analog Device, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD1881A–SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature
Digital Supply (VDD)
Analog Supply (VCC)
Sample Rate (FS)
Input Signal
25
3.3
5.0
48
1008
°C
V
V
kHz
Hz
DAC Test Conditions
Calibrated
–3 dB Attenuation Relative to Full-Scale
Input 0 dB
10 kΩ Output Load
ADC Test Conditions
Calibrated
0 dB Gain
Input –3.0 dB Relative to Full-Scale
ANALOG INPUT
Parameter
Min
Input Voltage (RMS Values Assume Sine Wave Input)
LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP
MIC with +20 dB Gain (M20 = 1)
MIC with 0 dB Gain (M20 = 0)
Input Impedance*
Input Capacitance*
Typ
Max
Unit
1
2.83
0.1
0.283
1
2.83
20
5
7.5
V rms
V p-p
V rms
V p-p
V rms
V p-p
kΩ
pF
Typ
Max
Unit
80
dB
dB
dB
dB
dB
Max
Unit
MASTER VOLUME
Parameter
Min
Step Size (0 dB to –94.5 dB); LINE_OUT_L, LINE_OUT_R
Output Attenuation Range Span*
Step Size (0 dB to –46.5 dB); MONO_OUT
Output Attenuation Range Span*
Mute Attenuation of 0 dB Fundamental*
1.5
–94.5
1.5
–46.5
PROGRAMMABLE GAIN AMPLIFIER—ADC
Parameter
Min
Step Size (0 dB to 22.5 dB)
PGA Gain Range Span
Typ
1.5
22.5
dB
dB
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Parameter
Min
Signal-to-Noise Ratio (SNR)
CD to LINE_OUT
Other to LINE_OUT
Step Size (+12 dB to –34.5 dB): (All Steps Tested)
MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC
Input Gain/Attenuation Range: MIC, LINE, AUX, CD, VIDEO, PHONE_IN, DAC
Step Size (0 dB to –45 dB): (All Steps Tested) PC_BEEP
Input Gain/Attenuation Range: PC_BEEP
Typ
Max
Unit
90
90
dB
dB
1.5
–46.5
3.0
–45
dB
dB
dB
dB
*Guaranteed, not tested.
Specifications subject to change without notice.
–2–
REV. 0
AD1881A
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Parameter
Min
Passband
Passband Ripple
Transition Band
Stopband
Stopband Rejection
Group Delay
Group Delay Variation Over Passband
0
Typ
0.4 × FS
0.6 × FS
–74
Max
Unit
0.4 × FS
± 0.09
0.6 × FS
12/FS
0.0
Hz
dB
Hz
Hz
dB
sec
µs
Max
Unit
∞
ANALOG-TO-DIGITAL CONVERTERS
Parameter
Min
Typ
Resolution
Total Harmonic Distortion (THD)
16
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted)
Signal-to-Intermodulation Distortion* (CCIF Method)
ADC Crosstalk*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
LINE_IN to Other
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error
87
85
0.02
–74
Bits
%
dB
dB
dB
–100
–90
–90
–85
± 10
± 0.5
± 10.5
dB
dB
%
dB
mV
Typ
Max
Unit
DIGITAL-TO-ANALOG CONVERTERS
Parameter
Min
Resolution
Total Harmonic Distortion (THD) LINE_OUT, LNLVL_OUT
16
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted)
Signal-to-Intermodulation Distortion* (CCIF Method)
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L,
Measure L_OUT)
Total Audible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)*
90
85
± 10
0.02
–74
± 0.7
–80
–40
Bits
%
dB
dB
dB
%
dB
dB
dB
ANALOG OUTPUT
Parameter
Min
Full-Scale Output Voltage
(LINE_OUT, LNLVL_OUT)
Output Impedance*
External Load Impedance*
Output Capacitance*
External Load Capacitance
VREF
VREF_OUT
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
*Guaranteed, not tested.
Specifications subject to change without notice.
REV. 0
–3–
Typ
Max
1
2.83
500
10
15
2.0
2.2
2.2
±5
100
2.5
Unit
V rms
V p-p
Ω
kΩ
pF
pF
V
V
mV
AD1881A–SPECIFICATIONS
STATIC DIGITAL SPECIFICATIONS
Parameter
Min
High Level Input Voltage (VIH ): Digital Inputs
Low Level Input Voltage (VIL )
High Level Output Voltage (VOH ), IOH = –0.5 mA
Low Level Output Voltage (VOL ), IOL = +0.5 mA
Input Leakage Current
Output Leakage Current
0.65 × DVDD
Typ
Max
0.1 × DVDD
+10
+10
V
V
V
V
µA
µA
Max
Unit
5.25
3.6
V
V
mW
mA
mA
dB
Max
Unit
0.35 × DVDD
0.9 × DVDD
–10
–10
Unit
POWER SUPPLY
Parameter
Min
Power Supply Range – Analog
Power Supply Range – Digital (3.3 V)
Power Dissipation – 5 V/3.3 V
Analog Supply Current – 5 V
Digital Supply Current – 3.3 V
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
4.75
3.0
Typ
280
40
23
40
CLOCK SPECIFICATIONS*
Parameter
Min
Typ
Input Clock Frequency
Recommended Clock Duty Cycle
45
24.576
50
55
MHz
%
POWER-DOWN MODE
Parameter
Set Bits
DVDD (3.3 V)
Typ
AVDD (5 V)
Typ
Unit
ADC
DAC
ADC and DAC
ADC + DAC + Mixer (Analog CD On)
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Analog CD Only (AC-Link On)
Analog CD Only (AC-Link Off)
Standby
PR0
PR1
PR1, PR0
LPMIX, PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
LPMIX, PR5, PR1, PR0
LPMIX, PR1, PR0, PR4, PR5
PR5, PR4, PR3, PR2, PR1, PR0
17
17
4
4
20
17
17
4
4
0
0
30
26
20
12
18
12
8
2
12
12
0.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*Guaranteed, not tested.
Specifications subject to change without notice.
–4–
REV. 0
AD1881A
TIMING PARAMETERS 1 (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter2
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to HI-Z Delay (ATE Test Mode)
Propagation Delay
RESET Rise Time
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
50
NOTES
1
Guaranteed, not tested.
2
Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.
REV. 0
–5–
Typ
Max
833
80
19.5
162.8
12.288
81.4
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
36.62
36.62
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
5
5
2
2
2
2
2
2
2
2
0
15
40.69
40.69
48.0
20.8
2.5
4
4
4
4
4
4
4
4
750
44.76
44.76
10
10
10
10
10
10
10
10
10
25
15
50
Unit
ns
µs
ns
µs
ns
MHz
ns
ps
ns
ns
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
AD1881A
tRST_LOW
BIT_CLK
tRST2CLK
RESET
tRISECLK
BIT_CLK
tFALLCLK
SYNC
Figure 1. Cold Reset
tRISESYNC
tFALLSYNC
SDATA_IN
tRISEDIN
tRST2CLK
tSYNC_HIGH
SYNC
tFALLDIN
SDATA_OUT
BIT_CLK
tRISEDOUT
Figure 2. Warm Reset
tFALLDOUT
Figure 5. Signal Rise and Fall Time
tCLK_LOW
BIT_CLK
SYNC
tCLK_HIGH
tCLK_PERIOD
SLOT 1
SLOT 2
WRITE
TO 0x26
DATA
PR4
BIT_CLK
tSYNC_LOW
SDATA_OUT
SYNC
DON’T
CARE
tS2_PDOWN
tSYNC_HIGH
tSYNC_PERIOD
SDATA_IN
NOTE: BIT_CLK NOT TO SCALE
Figure 3. Clock Timing
Figure 6. AC Link Low Power Mode Timing
tSETUP
RESET
BIT_CLK
SDATA_OUT
SYNC
tSETUP2RST
SDATA_IN, BIT_CLK
SDATA_OUT
HI-Z
tOFF
tHOLD
Figure 7. ATE Test Mode
Figure 4. Data Setup and Hold
–6–
REV. 0
AD1881A
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
Parameter
Power Supplies
Digital (VDD)
Analog (VCC)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
Min
Max
Temperature
Range
Unit
Model
–0.3
–0.3
–0.3
–0.3
0
–65
+3.6
+6.0
VCC + 0.3
VDD + 0.3
+70
+150
AD1881AJST 0°C to 70°C
V
V
V
V
°C
°C
␪JA
␪JC
␪CA
LQFP
76.2°C/W
17°C/W
59.2°C/W
MONO_OUT
LNLVL_OUT_L
AVDD2
AVSS2
LNLVL_OUT_R
NC
NC
NC
CS0
EAPD/CHAIN_IN
CS1
MODE
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 1
36 LINE_OUT_R
PIN 1
IDENTIFIER
35 LINE_OUT_L
XTL_OUT 3
34 CX3D
DVSS1 4
33 RX3D
32 FILT_L
AD1881A
31 FILT_R
TOP VIEW
(Not to Scale)
30 AFILT2
SDATA_IN 8
29 AFILT1
DVDD2 9
28 VREFOUT
SYNC 10
RESET 11
27 VREF
26 AVSS1
25 AV
DD1
PC_BEEP 12
NC = NO CONNECT
–7–
LINE_IN_R
MIC2
LINE_IN_L
MIC1
CD_R
CD_GND_REF
VIDEO_L
VIDEO_R
CD_L
AUX_R
PHONE_IN
AUX_L
13 14 15 16 17 18 19 20 21 22 23 24
REV. 0
ST-48
Package
PIN CONFIGURATION
48-Lead LQFP
BIT_CLK 6
DVSS2 7
48-Lead LQFP
Ambient Temperature Rating
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1881A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
SDATA_OUT 5
Package
Option
ENVIRONMENTAL CONDITIONS
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in t he
operational section of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
XTL_IN 2
Package
Description
WARNING!
ESD SENSITIVE DEVICE
AD1881A
PIN FUNCTION DESCRIPTIONS
Digital I/O
Pin Name
LQFP
I/O
Description
XTL_IN
XTL_OUT
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
2
3
5
6
8
10
11
I
O
I
O
O
I
I
Crystal (or Clock) Input, 24.576 MHz.
Crystal Output.
AC-Link Serial Data Output, AD1881A Input Stream.
AC-Link Bit Clock. 12.288 MHz Serial Data Clock. Daisy Chain Output Clock.
AC-Link Serial Data Input. AD1881A Output Stream.
AC-Link Frame Sample Sync 48 kHz Fixed Rate.
AC-Link Reset. AD1881A Master H/W Reset.
Miscellaneous Connections
Pin Name
LQFP
I/O
Description
CS0
CS1
EAPD
MODE
45
46
47
48
I
I
O
I
Chip Select 0.
Chip Select 1.
External Amp Power-Down Control Signal, Default LO, Active HI
MODE Select.
Analog I/O
These signals connect the AD1881A component to analog sources and sinks, including microphones and speakers.
Pin Name
LQFP
I/O
Description
PC_BEEP
PHONE_IN
AUX_L
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_GND_REF
CD_ R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
LINE_OUT_L
LINE_OUT_R
MONO_OUT
LNLVL_OUT_L
LNLVL_OUT_R
12
13
14
15
16
17
18
19
20
21
22
23
24
35
36
37
39
41
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
PC Beep. PC Speaker Beep Passthrough.
Phone. From Telephony Subsystem Speakerphone or Handset.
Auxiliary Input Left Channel.
Auxiliary Input Right Channel.
Video Audio Left Channel.
Video Audio Right Channel.
CD Audio Left Channel.
CD Audio Analog Ground Reference for Pseudo-Differential CD Input.
CD Audio Right Channel.
Microphone 1. Desktop Microphone Input.
Microphone 2. Second Microphone Input.
Line In Left Channel.
Line In Right Channel.
Line Out Left Channel.
Line Out Right Channel.
Monaural Output to Telephony Subsystem Speakerphone.
Line-Level Output Left Channel.
Line-Level Output Right Channel.
Filter/Reference
These signals are connected to resistors, capacitors, or specific voltages.
Pin Name
LQFP
I/O
Description
VREF
VREFOUT
AFILT1
AFILT2
FILT_R
FILT_L
RX3D
CX3D
27
28
29
30
31
32
33
34
O
O
O
O
O
O
O
I
Voltage Reference Filter.
Voltage Reference Output 5 mA Drive (Intended for MIC Bias).
Antialiasing Filter Capacitor—ADC Right Channel.
Antialiasing Filter Capacitor—ADC Left Channel.
AC-Coupling Filter Capacitor—ADC Right Channel.
AC-Coupling Filter Capacitor—ADC Left Channel.
3D PHAT Stereo Enhancement—Capacitor.
3D PHAT Stereo Enhancement—Capacitor.
–8–
REV. 0
AD1881A
Power and Ground Signals
Pin Name
LQFP
Type
Description
DVDD1
DVSS1
DVSS2
DVDD2
AVDD1
AVSS1
AVDD2
AVSS2
1
4
7
9
25
26
38
42
I
I
I
I
I
I
I
I
Digital VDD 3.3 V
Digital GND
Digital GND
Digital VDD 3.3 V
Analog VDD 5.0 V
Analog GND
Analog VDD 5.0 V
Analog GND
Pin Name
LQFP
Type
Description
NC
NC
NC
40
43
44
No Connects
0
MS
1
0x20
0dB/20dB
M20 0x0E
LS (4)
RS (4)
GM 0x1C
LSLIM
(3)
RSIM(3)
LINE_IN
AUX
LS (1)
RS (1)
CD
LS (2)
RS (2)
VIDEO
PHONE_IN
GM 0x1C
LS/RS
(7)
RIM
LSIM(5)
STEREO MIX (L)
MONO MIX
S
E
L
E
C
T
O
R
GM 0X1C
LIM
IM
16-BIT
⌺⌬ A/D
GM 0X1C
RIM
IM
16-BIT
⌺⌬ A/D
LS/RS (6)
STEREO MIX (R)
MONO_OUT
AD1881A
LS/RS (0)
0X74
MIC2
RESET
RS (5)
MV
S 0x1A
MIX
0x20
⌺
SYNC
GA 0x0C
⌺
GA 0x0E GA 0x10
⌺
PHV
GA 0x12
LAV
RAV
GA 0x14
LVV
RVV
PCM DAC RATE 0x2C
SR1
0x7A
PCM ADC RATE 0x32
SR0
0x78
MCV
LLV
RLA
GA 0x16
LCV
RCV
M 0x0E
M 0x10
M 0x16
M 0x12
M 0x14
MCM
LM
CM
AM
VM
LPBK
0x20
M 0x0C
PHM
LNLVL_OUT_L
AC LINK
MIC1
No Connect
No Connect
No Connect
BIT_CLK
SDATA_OUT
SDATA_IN
LINE_OUT_L
0x02
02
MM
LMV
0x22
⌺
PHAT
0x20
⌺
⌺
⌺
⌺
⌺
GAM 0x18
LOV
OM
⌺
LINE_OUT_R
0x02
02
0x22
MM
LMV
DP
⌺
PHAT
⌺
0x20
⌺
⌺
⌺
⌺
LNLVL_OUT_R
GAM 0x18
16-BIT
⌺⌬ D/A
M 0x0A
PCM
A 0x0A
PC_BEEP
⌺
0x20
POP
NC
ROV
OM
POP
0x20
16-BIT
⌺⌬ D/A
NC
DAM
DP
POP
0x20
G = GAIN
A = ATTENUATE
M = MUTE
MV = MASTER VOLUME
PCV
OSCILLATORS
XTL_OUT
Figure 8. Block Diagram Register Map
REV. 0
–9–
XTL_IN
AD1881A
PRODUCT OVERVIEW
Analog-to-Digital Signal Path
The AD1881A meets the Audio Codec ’97 2.0 and 2.1 Extensions. In
addition, the AD1881A SoundMAX Codec is designed to meet all
requirements of the Audio Codec ’97, Component Specification, Revision 1.03, © 1996, Intel Corporation, found at www.Intel.com.
The AD1881A also includes some other Codec enhanced features such as the built-in PHAT Stereo 3D enhancement.
The selector sends left and right channel information to the
programmable gain amplifier (PGA). The PGA following the
selector allows independent gain control for each channel entering
the ADC from 0 dB to +22.5 dB in 1.5 dB steps. Each channel
of the ADC is independent, and can process left and right channel data at different sample rates.
The AD1881A is an analog front end for high performance PC
audio applications. The AC’97 architecture defines a 2-chip
audio solution comprising a digital audio controller, plus a high
quality analog component that includes Digital-to-Analog
Converters (DACs), Analog-to-Digital Converters (ADCs),
mixer and I/O.
Sample Rates and D2S
The main architectural features of the AD1881A are the high
quality analog mixer section, two channels of Σ∆ ADC conversion,
two channels of Σ∆ DAC conversion with Data Direct Scrambling (D2S) rate generators. The AD1881A’s left channel ADC
and DAC are compatible for modem applications supporting irrational sample rates and modem filtering requirements.
FUNCTIONAL DESCRIPTION
This section overviews the functionality of the AD1881A and
is intended as a general introduction to the capabilities of the
device. Detailed reference information may be found in the
descriptions of the Indexed Control Registers.
The AD1881A default mode sets the Codec to operate at 48 kHz
sample rates. The converter pairs may process left and right
channel data at different sample rates. The AD1881A sample
rate generator allows the Codec to instantaneously change and
process sample rates from 8 kHz to 48 kHz with a resolution
of 1 Hz. The in-band integrated noise and distortion artifacts
introduced by rate conversions are below –90 dB. The AD1881A
uses a 4-bit D/A structure and Data Directed Scrambling (D2S)
to enhance noise immunity on motherboards and in PC enclosures, and to suppress idle tones below the device’s quantization
noise floor. The D2S process pushes noise and distortion artifacts
caused by errors in the multibit DAC to frequencies beyond the
auditory response of the human ear and then filters them.
Digital-to-Analog Signal Path
The analog output of the DAC may be gained or attenuated from
+12 dB to –34.5 dB in 1.5 dB steps, and summed with any of
the analog input signals. The summed analog signal enters the
Master Volume stage where each channel of the mixer output may
be attenuated from 0 dB to –94.5 dB in 1.5 dB steps or muted.
Analog Inputs
The Codec contains a stereo pair of Σ∆ ADCs. Inputs to the
ADC may be selected from the following analog signals: telephony (PHONE_IN), mono microphone (MIC1 or MIC2),
stereo line (LINE_IN), auxiliary line input (AUX), stereo CD
ROM (CD), stereo audio from a video source (VIDEO) and
post-mixed stereo or mono line output (LINE_OUT).
Line-Level Outputs
The AD1881A offers a true line-level output for notebook docking station and home theater applications. The line-level output
does not change with master volume settings.
Host-Based Echo Cancellation Support
Analog Mixing
PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD and VIDEO
can be mixed in the analog domain with the stereo output from the
DACs. Each channel of the stereo analog inputs may be independently gained or attenuated from +12 dB to –34.5 dB in 1.5 dB
steps. The summing path for the mono inputs (PHONE_IN, MIC1,
and MIC2 to LINE_OUT) duplicates mono channel data on both
the left and right LINE_OUT. Additionally, the PC attention signal (PC_BEEP) may be mixed with the line output. A switch
allows the output of the DACs to bypass the PHAT Stereo
3D enhancement.
The AD1881A supports time correlated I/O data format by presenting MIC data on the left channel of the ADC and the mono
summation of left and right output on the right channel. The
ADC is splittable; left and right ADC data can be sampled at
different rates.
Power Management Modes
The AD1881A is designed to meet ACPI power consumption
requirements through flexible power management control of all
internal resources.
Digital Audio Mode
The AD1881A is designed with a Digital Audio Mode (DAM)
that allows mixing of all analog inputs independent of the DAC
output signal path. Mixed analog input signals may be sent to
the ADCs for processing by the controller or the host, and may
be used during simultaneous capture and playback at different
sample rates.
–10–
REV. 0
AD1881A
Indexed Control Registers
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
00h
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0410h
02h
Master Volume
MM
X
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 X
X
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h
04h
Reserved
X
X
X
X
X
X
X
X
X
X
X
X
06h
Master Volume Mono
MMM
X
X
X
X
X
X
X
X
X
X
MMV MMV MMV MMV MMV
X
X
X
X
4
2
2
1
0
X
X
X
X
X
8000h
08h
Reserved
X
X
X
X
X
X
X
X
X
X
X
X
0Ah
PC Beep Volume
PCM
X
X
X
X
X
X
X
X
X
X
PCV3 PCV2 PCV1 PCV0 X
8000h
0Ch
Phone In Volume
PHM
X
X
X
X
X
X
X
X
X
X
PHV4 PHV3 PHV2 PHV1 PHV0
8008h
0Eh
MIC Volume
MCM
X
X
X
X
X
X
X
X
M20
X
MCV4 MCV3 MCV2 MCV1 MCV0 8008h
10h
Line In Volume
LM
X
X
LLV4 LLV3 LLV2 LLV1 LLV0 X
X
X
RLV4 RLV3 RLV2 RLV1 RLV0
8808h
12h
CD Volume
CVM
X
X
LCV4 LCV3 LCV2 LCV1 LCV0 X
X
X
RCV4 RCV3 RCV2 RCV1 RCV0
8808h
14h
Video Volume
VM
X
X
LVV4 LVV3 LVV2 LVV1 LVV0 X
X
X
RVV4 RVV3 RVV2 RVV1 RVV0
8808h
16h
Aux Volume
AM
X
X
LAV4 LAV3 LAV2 LAV1 LAV0 X
X
X
RAV4 RAV3 RAV2 RAV1 RAV0
8808h
18h
PCM Out Vol
OM
X
X
LOV4 LOV3 LOV2 LOV1 LOV0 X
X
X
ROV4 ROV3 ROV2 ROV1 ROV0
8808h
1Ah
Record Select
X
X
X
X
X
X
X
X
X
X
0000h
1Ch
Record Gain
IM
X
X
X
LIM3 LIM2 LIM1 LIM0 X
X
X
X
RIM3 RIM2 RIM1 RIM0
8000h
1Eh
Reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
20h
General Purpose
POP
X
3D
X
X
X
MIX
MS
LPBK X
X
X
X
X
X
X
0000h
22h
3D Control
X
X
X
X
X
X
X
X
X
X
X
X
DP3
DP2
DP1
DP0
0000h
26h
Power-Down Cntrl/Stat
EAPD
X
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
DAC
ADC
000Xh
28h
Extended Audio ID
ID1
ID0
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
0001h
2Ah
Extended Audio Stat/Ctrl
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
0000h
2Ch/
PCM DAC Rate (SR1)
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
BB80h
PCM ADC Rate (SR0)
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
BB80h
34h
Reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
5ah
Vendor Reserved**
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
72h
Reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
74h
Serial Configuration
SLOT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7X0Xh
DAM
DMS
DLSR X
ALSR MOD SRX
SRX
X
X
DRSR X
ARSR
0404h
EN
10D7
8D7
S6
S5
S4
S3
S2
S0
4144h
LS2
LS1
LS0
RS2
RS1
RS0
X
(7Ah)*
32h /
(78h)*
70h
16
76h
Misc. Control Bits
DAC
LPMI X
Z
X
7Ch
Vendor ID1
F7
F6
F5
F4
F3
F2
F1
F0
S7
7Eh
Vendor ID2
T7
T6
T5
T4
T3
T2
T1
T0
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
*Indicates Aliased register for AD1819, AD1819A backward compatibility.
**Vendor Reserved registers should not be written.
REV. 0
–11–
S1
5348h
AD1881A
Reset (Index 00h)
Reg
Name
Num
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
00h
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0410h
Reset
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except
74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo
Enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1881A based on the following:
Bit = 1
Function
AD1881A
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
Dedicated MIC PCM In Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out/True Line-Level Out
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
0
0
0
0
1
0
0
0
0
0
SE[4:0] Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Master Volume Registers (Index 02h)
Reg
Num
Name
D15
D14
D13
02h
Master
Volume
MM
MM
X
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 X
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
X
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h
RMV[5:0]
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of –94.5 dB.
LMV[5:0]
Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to
a maximum attenuation of –94.5 dB.
MM
Master Volume Mute. When this bit is set to “1,” the channel is muted.
MM
xMV5 . . . xMV0
Function
0
0
0
1
00 0000
01 1111
11 1111
xx xxxx
0 dB Attenuation
–46.5 dB Attenuation
–94.5 dB Attenuation
–∞ dB Attenuation
Master Volume Mono (Index 06h)
Reg
Num
Name
06h
Master Volume
MMM X
Mono
D15
D14 D13 D12 D11 D10 D9
D9
X
X
X
X
X
D8
D8
X
D7
D7
D6
D6
X
X
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
MMV4 MMV3 MMV2 MMV1 MMV0 8000h
MMV[4:0]
Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of –46.5 dB.
MMM
Mono Master Volume Mute. When this bit is set to “1,” the channel is muted.
–12–
REV. 0
AD1881A
PC Beep Register (Index 0Ah)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
0Ah
PC_BEEP Volume
PCM
X
X
X
X
X
X
X
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
X
PCV3 PCV2 PCV1 PCV0 X
Default
8000h
PCV[3:0]
PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output
from 0 dB to a maximum attenuation of –45 dB. The PC Beep is routed to Left and Right Line outputs even when
the RESET pin is asserted. This is so that Power on Self-Test (POST) codes can be heard by the user in case of a
hardware problem with the PC.
PCM
PC Beep Mute. When this bit is set to “1,” the channel is muted.
PCM
PCV3 . . . PCV0
Function
0
0
1
0000
1111
xxxx
0 dB Attenuation
–45 dB Attenuation
–∞ dB Attenuation
Phone Volume (Index 0Ch)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
0Ch
Phone Volume
PHM
X
X
X
X
X
X
X
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
PHV4 PHV3 PHV2 PHV1 PHV0 8008h
PHV[4:0]
Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
PHM
Phone Mute. When this bit is set to “1,” the channel is muted.
MIC Volume (Index 0Eh)
Reg
Name
Num
0Eh
D15
D14
Mic Volume MCM X
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
X
X
X
X
X
X
M20
X
MCV4
MCV3
MCV2
MCV1
MCV0
8008h
MCV[4:0]
MIC Volume Gain. Allows setting the MIC Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
M20
Microphone 20 dB Gain Block
0 = Disabled; Gain = 0 dB.
1 = Enabled; Gain = 20 dB.
MCM
MIC Mute. When this bit is set to “1,” the channel is muted.
Line In Volume (Index 10h)
Reg
Name
Num
10h
D15
Line InVolume LM
LM
D14
D13
D12
D11
D10
D9
D9
D8
D8
X
X
LLV4 LLV3 LLV2 LLV1 LLV0
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
X
X
RLV4
RLV3
RLV2
RLV1
RLV0
8808h
RLV[4:0]
Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LLV[4:0]
Line In Volume Left. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LM
Line In Mute. When this bit is set to “1,” the channel is muted.
REV. 0
–13–
AD1881A
CD Volume (Index 12h)
Reg
Name
Num
12h
D15
D14
CD Volume CVM X
D13
D12
D11
D10
D9
D9
D8
D8
X
LCV4 LCV3 LCV2 LCV1 LCV0
D7
D7
X
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
X
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0]
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LCV[4:0]
Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
CVM
CD Volume Mute. When this bit is set to “1,” the channel is muted.
Video Volume (Index 14h)
Reg
Name
Num
14h
D15
Video Volume VM
VM
D14
D13
D12
D11
D10
D9
D9
D8
D8
X
X
LVV4 LVV3 LVV2 LVV1 LVV0
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
X
X
RVV4 RVV3 RVV2 RVV1 RVV0 8808h
RVV[4:0]
Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LVV[4:0]
Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
VM
Video Mute. When this bit is set to “1,” the channel is muted.
AUX Volume (Index 16h)
Reg
Name
Num
D15
D14
D13
D12
16h
AM
AM
X
X
LAV4 LAV3 LAV2 LAV1 LAV0
Aux Volume
D11
D10
D9
D9
D8
D8
D7
D7
X
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
X
RAV4 RAV3 RAV2 RAV1 RAV0 8808h
RAV[4:0]
Right Aux. Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LAV[4:0]
Left Aux. Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
AM
Aux. Mute. When this bit is set to “1,” the channel is muted.
PCM Out Volume (Index 18h)
Reg
Name
Num
18h
PCM Out
Volume
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
OM
OM
X
X
LOV4 LOV3 LOV2 LOV1 LOV0
D7
D7
X
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
X
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
ROV[4:0]
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LOV[4:0]
Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
OM
PCM Out Volume Mute. When this bit is set to “1,” the channel is muted.
Volume Table (Index 0Ch to 18h)
MM
x4 . . . x0
Function
0
0
0
1
00000
01000
11111
xxxxx
+12 dB Gain
0 dB Gain
–34.5 dB Gain
–∞ dB Gain
–14–
REV. 0
AD1881A
Record Select Control Register (Index 1Ah)
Reg
Name
Num
1Ah
D15
Record Select X
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
X
X
X
LS2
LS1
LS0
X
X
X
X
X
RS2
RS1
RS0
0000h
RS[2:0]
Right Record Select
LS[2:0]
Left Record Select.
Used to select the record source independently for right and left. See table for legend.
The default value is 0000h, which corresponds to MIC in.
RS2 . . . RS0
Right Record Source
0
1
2
3
4
5
6
7
MIC
CD_R
VIDEO_R
AUX_R
LINE_IN_R
Stereo Mix (R)
Mono Mix
PHONE_IN
LS2 . . . LS0
Left Record Source
0
1
2
3
4
5
6
7
MIC
CD_L
VIDEO_L
AUX_L
LINE_IN_L
Stereo Mix (L)
Mono Mix
PHONE_IN
Record Gain (Index 1Ch)
Reg
Name
Num
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
1Ch
IM
IM
X
X
X
LIM3
LIM2
LIM1
LIM0
X
X
X
X
RIM3
RIM2
RIM1
RIM0
8000h
Record Gain
RIM[3:0]
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB.
LIM[3:0]
Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB.
IM
Input Mute.
0 = Unmuted,
1 = Muted or –∞ dB gain.
REV. 0
IM
xIM3 . . . xIM0
Function
0
0
1
1111
0000
xxxxx
+22.5 dB Gain
0 dB Gain
–∞ dB Gain
–15–
AD1881A
General Purpose Register (Index 20h)
Reg
Name
Num
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
20h
POP
X
3D
3D
X
X
X
MIX
MS
MS
LPBK
X
X
X
X
X
X
X
0000h
General Purpose
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function
default value is 0000h which is all off.
LPBK
Loopback Control. ADC/DAC Digital Loopback Mode
MS
MIC Select
0 = MIC1.
1 = MIC2.
MIX
Mono Output Select
0 = Mix.
1 = MIC.
3D
3D PHAT Stereo Enhancement
0 = PHAT Stereo is off.
1 = PHAT Stereo is on.
POP
PCM Output Path and Mute. The POP bit controls the optional PCM out 3D bypass path (the pre- and post-3D
PCM out paths are mutually exclusive).
0 = pre-3D.
1 = post-3D.
3D Control Register (Index 22h)
Reg
Name
Num
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
22h
X
X
X
X
X
X
X
X
X
X
X
X
DP3
DP2
DP1
DP0
0000h
3D Control
DP[2:0]
Depth Control. Sets 3D “Depth” PHAT Stereo enhancement according to table below.
DP3 . . . DP0
Depth
0000
0001
.
.
1110
1111
0%
6.67%
.
.
93.33%
100%
–16–
REV. 0
AD1881A
Subsection Ready Register (Index 26h)
Reg
Name
Num
D15
26h
EAPD X
Power-Down Cntrl/Stat
D14 D13 D12 D11 D10 D9
D9
D8
D8
D7
D7
PR5 PR4 PR3 PR2 PR1 PR0 X
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
X
X
REF
ANL
DAC ADC N/A
Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the
AD1881A subsections. If the bit is a one, then that subsection is “ready.” Ready is defined as the subsection able to perform in its
nominal state.
ADC
ADC section ready to transmit data.
DAC
DAC section ready to accept data.
ANL
Analog gain, attenuators and mute blocks, and mixers ready.
REF
Voltage References, VREF and VREFOUT up to nominal level.
PR[5:0]
AD1881A Power-Down Modes. The first three bits are to be used individually rather than in combination with each
other. The last bit PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be
powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until
the reference is up.
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can
either be up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are
both set.
In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in
the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5.
EAPD
External Audio Amp Power Down. Available when programmed as an AC’97 codec.
0 = Pin 47 set to LO state (default).
1 = Pin 47 set to HI state.
Power-Down State
PR5
PR4
PR3
PR2
PR1
PR0
ADC Power-Down
DAC Power-Down
ADC and DAC Power-Down
Mixer Power-Down
ADC + Mixer Power-Down
DAC + Mixer Power-Down
ADC + DAC + Mixer Power-Down
Standby
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
Extended Audio ID Register (Index 28h)
Reg
Name
Num
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
28h
ID1
ID0
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
0000h
Extended Audio ID
Note: The Extended Audio ID is a read only register.
VRA
Variable Rate Audio. VRA = 1 enables Variable Rate Audio.
ID[1:0]
ID1, ID0 is a 2-bit field that indicates the codec configuration: Primary is 00; Secondary is 01, 10, or 11.
REV. 0
–17–
AD1881A
Extended Audio Status and Control Register (Index 2Ah)
Reg
Name
Num
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
2Ah
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
0000h
Extended Audio St/Ctrl
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio
features.
VRA
Variable Rate Audio. VRA = 1 enables Variable Rate Audio mode (sample rate control registers and SLOTREQ
signaling.
PCM DAC Rate Register (Index 2Ch)
Reg
Num
Name
2Ch/(7Ah) PCM DAC Rate
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
SR15
SR14
SR13
SR12
SR11
SR10
SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48k.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 8 kHz (1B80h) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codec
to saturate to 48 kHz if a rate greater than 48 kHz is programmed or to 7.040 kHz if a rate less than 7.040 kHz is
programmed. For all rates, if the value written to the register is supported, that value will be echoed back when read,
otherwise the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D9
32h/(78h)
PCM ADC Rate
SR15
SR14
SR13
SR12
SR11
SR10
SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48k.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 8 kHz (1B80) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codec to
saturate to 48 kHz if a rate greater than 48 kHz is programmed, or to 7.040 kHz if a rate less than 7.040 kHz
is programmed. For all rates, if the value written to the register is supported, that value will be echoed back
when read, otherwise the closest rate supported is returned.
Serial Configuration (Index 74h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
74h
Serial
Configuration
SLOT
16
16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7x0xh
Note: This register is not reset when the reset register (register 00h) is written.
SLOT16
Enable 16-bit slots.
DRQEN and DxRQx are retained only for compatibility with the AD1819. New controller designs should use the VRA bit in register
2Ah and the request bits in the status address slot instead.
If your system uses only a single AD1881A, you can ignore the register mask and the slave 1/slave 2 request bits. If you write to
this register, write ones to all of the register mask bits.
SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.
–18–
REV. 0
AD1881A
Miscellaneous Control Bits (Index 76h)
Reg
Name
Num
D15
D14
D13 D12
76h
DAC
Z
LPMI
X
X
Misc Control Bits
D11
D10
D9
D9
DAM DMS DLSR X
D8
D8
D7
D7
D6
D6
D5
D5
ALSR
MOD
EN
EN
SRX10 SRX8
D7
D7
D7
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
X
X
DRSR
X
ARSR
0404h
ARSR
ADC right sample generator select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch).
DRSR
DAC right sample generator select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch).
SRX8D7
Multiply SR1 rate by 8/7.
SRX10D7
Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set.
MODEN
Modem filter enable (left channel only). Change only when DACs are powered down.
ALSR
ADC left sample generator select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch).
DLSR
DAC left sample generator select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch).
DMS
Digital Mono Select.
0 = Mixer
1 = Left DAC and Right DAC.
DAM
Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output.
LPMIX
Low Power Mixer. Keeps CD to LINE_OUT alive for notebook applications.
DACZ
Zero fill (vs. repeat) if DAC is starved for data.
Sample Rate 0 (Index 78h)
Reg
Name
Num
78h
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D2
D2
D1
D1
D0
D0
Default
Sample Rate 0 SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80H
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48k.
SR0[15:0]
REV. 0
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
–19–
AD1881A
Sample Rate 1 (Index 7Ah)
Reg
Name
Num
7Ah
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
Sample Rate 1 SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48k.
SR1[15:0]
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable
results.
Vendor ID Registers (Index 7Ch–7Eh)
Reg
Name
Num
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
7Ch
F7
F7
F6
F6
F5
F5
F4
F4
F3
F3
F2
F2
F1
F1
F0
F0
S7
S7
S6
S6
S5
S5
S4
S4
S3
S3
S2
S2
S1
S1
S0
S0
4144h
Vendor ID1
S[7:0]
This register is ASCII encoded to “A.”
F[7:0]
This register is ASCII encoded to “D.”
Reg
Num
Name
7Eh
Vendor ID2 T7
T7
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
T6
T6
T5
T5
T4
T4
T3
T3
T2
T2
T1
T1
T0
T0
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
5348h
T[7:0]
This register is ASCII encoded to “S.”
REV[7:0]
Revision Register field.
These bits are read-only and should be verified before accessing vendor defined features.
AD1881A/AD1881 USER VISIBLE DIFFERENCES
• Pin 48 is now MODE pin, no longer CHAIN_CLK.
• AD1881 chaining mode not supported.
• LSB of register 7Eh is 48h instead of 40h.
–20–
REV. 0
AD1881A
APPLICATIONS CIRCUITS
The AD1881A has been designed to require a minimum amount of external circuitry. The recommended applications circuits are
shown in Figure 9. Reference designs for the AD1881A are available and may be obtained by contacting your local Analog Devices’
sales representative or authorized distributor.
+5AVDD
+3.3DVDD
10␮F
10␮F
100nF 100nF
100nF
10k⍀
100nF 100nF
AVSS1 AVSS2 AVDD1 AVDD2
DVDD1 DVDD2 DVSS1 DVSS2
PC_BEEP
100nF
1k⍀
0.33␮F
0.33␮F
LINE_IN_R
LINE_IN_L
RESET
0.33␮F
MIC1
SDATA_OUT
MIC2
SDATA_IN
0.33␮F
0.33␮F
DIGITAL
CONTROLLER
SYNC
CD_R
47⍀
BIT_CLK
0.33␮F
CD_L
47pF
0.33␮F
AD1881A
CD_GND
0.33␮F
VIDEO_L
0.33␮F
CS0
VIDEO_R
CS1
0.33␮F
AUX_L
EAPD 47
AUX_R
MODE 48
0.33␮F
0.33␮F
EAPD
1␮F
PHONE_IN
LNLVL_OUT_L 39
0.33␮F
47k⍀
7 MONO_OUT
1␮F
1␮F
36 LINE_OUT_R
LNLVL_OUT_R 41
1␮F
LINE_OUT_L
47k⍀
47k⍀
47k⍀
47k⍀
AFILT1 AFILT2
FILT_L
FILT_R CX3D
RX3D VREFOUT
33
34
VREF
28
XTL_IN
27
100nF
270pF
NP0
270pF
NP0
1␮F
24.576MHz
2.25VDC
1␮F
47nF
100nF
22pF
NP0
10␮F
TANT
600Z
ANALOG GROUND
Figure 9. Recommended One Codec Application Circuit
–21–
22pF
NP0
DIGITAL GROUND
NOTE: FOR OPTIMAL PERFORMANCE USE A REGULATED ANALOG POWER SUPPLY.
REV. 0
XTL_OUT
AD1881A
CD-ROM CONNECTIONS
The CD-ROM audio output level should be investigated; typical drives generate 2 V rms output and require a voltage divider for
compatibility with the Codec input (1 V rms range). The recommended circuit is basically a group of divide-by-two voltage dividers
as shown on Figure 10.
The CD_GND_REF pin is used to cancel differential ground noise from the CD-ROM. For optimum noise cancellation, this section
of the divider should have approximately half the impedance of the right and left channel section dividers.
VOLTAGE
DIVIDER
C1
R1
4.7k⍀
HEADER FOR
CD ROM AUDIO
(LGGR)
R2
4.7k⍀
+
0.33␮F
1
2
3
4
C2
R3
2.7k⍀
R4
2.7k⍀
4.7k⍀
R6
4.7k⍀
TO CODEC
CD_GND_REF
INPUT
+
0.33␮F
C3
R5
TO CODEC
CD_L INPUT
TO CODEC
CD_R INPUT
+
0.33␮F
Figure 10. Typical CD-ROM Audio Connections
LINE_IN, AUX AND VIDEO INPUT CONNECTIONS
Most of these audio sources also generate 2 V rms audio level and require a –6 dB input voltage divider to be compatible with the
Codec inputs. Figure 11 shows the recommended application circuit. For applications requiring EMC compliance, the EMC components should be configured and selected to provide adequate RF immunity and emissions control.
LINE/AUX/VIDEO
INPUT
EMC
COMPONENTS
L2 600Z
J1
1
2
C1
470pF
VOLTAGE
DIVIDER
C3
R1
4.7k⍀
AC-COUPLING
R2
4.7k⍀
+
0.33␮F
3
4
5
L1 600Z
C2
470pF
C4
R3
4.7k⍀
TO CODEC
RIGHT CHANNEL
INPUT
R4
4.7k⍀
+
0.33␮F
TO CODEC
LEFT CHANNEL
INPUT
Figure 11. LINE_IN, AUX, and Video Input Connections
MICROPHONE CONNECTIONS
The AD1881A contains an internal microphone preamp with 20 dB gain, in most cases a direct microphone connection as shown in
Figure 12 is adequate. If the microphone level is too low, an external preamp can be added as shown in Figure 13. In either case the
microphone bias can be derived from the Codec’s internal reference (VREFOUT) using a 2.2 kΩ resistor. For the preamp circuit, the
VREFOUT signal can also provide the mid-point bias for the amplifier.
To meet the PC99 1.0A requirements, the MIC signal should be placed on the microphone jack tip and the bias on the ring. This
configuration supports electret microphones with three conductor plugs, as well as dynamic microphones with two conductor plugs
(ring and sleeve shorted together).
Additional filtering may be required to limit the microphone response to the audio band of interest.
–22–
REV. 0
AD1881A
EMC COMPONENTS
J1
L1 600Z
1
2
AC-COUPLING
3
4
C3
L2 600Z
5
C2
470pF
MIC INPUT
TO CODEC
MIC1 OR MIC2
INPUT
0.22␮F
C1
470pF
R1
FROM CODEC
VREFOUT
2.2k⍀
Figure 12. Recommended Microphone Input Connections
PREAMP
EMC COMPONENTS
R3
J1
1
2
3
4
L1 600Z
100k⍀
AC-COUPLING
5
C2
470pF
MIC INPUT
R2
10k⍀
C3
L2 600Z
+5AVDD
AC-COUPLING
U1
C3
0.22␮F
C1
470pF
0.22␮F
AD8531
TO CODEC
MIC1 OR MIC2
INPUT
MIC BIAS
R1
FROM CODEC
VREFOUT
2.2k⍀
Figure 13. Microphone with Additional External Preamp (20 dB Gain)
LINE OUTPUT CONNECTIONS
The AD1881A Codec provides stereo LINE_OUT signals at a standard 1 V rms level. These signals must be ac-coupled before they
can be connected to an external load. After the ac-coupling, a minimal resistive load is recommended to keep the capacitors properly
biased and reduce click and pop when plugging stereo equipment into the output jack. The capacitor values should be selected
to provide a desired frequency response, taking into account the nominal impedance of the external load. To meet the PC99
specification for PCs, testing must be performed with a 10 kΩ load, therefore a 1 µF value is recommended to achieve less than
–3 dB roll-off at 20 Hz.
EMC COMPONENTS
STEREO
LINE_OUT JACK
AC-COUPLING
C1
+
L2 600Z
J1
C1
470pF
1␮F
C2
+
L1 600Z
C2
470pF
R1
47k⍀
R2
47k⍀
1␮F
FROM CODEC
LINE_OUT_R
FROM CODEC
LINE_OUT_L
NOTE: IF AN OUTPUT AMP IS USED,
THE AC-COUPLING CAP VALUES WILL
DEPEND ON THE AMP DESIGN.
Figure 14. Recommended LINE_OUT Connections
USING AN EXTERNAL HEADPHONE/POWER AMP
The SSM2250 Power Amplifier is an ideal companion for the AD1881A. The amplifier can provide up to 250 mW output in stereo
mode and up to 1.5 W into a mono speaker connected in a bridge-tied load (BTL) configuration.
The SM2250 has a mode control pin that can be used to switch between the stereo output mode and the mono BTL speaker.
Figure 15 shows a typical PC configuration where the SSM2250 drives a set of stereo headphones or external speakers, as well as an
internal mono speaker. One of the normalizing pins on the stereo jack senses the stereo plug insertion and automatically switches
from driving the internal mono speaker to driving the external stereo load.
To conserve power, the SSM2250 can be shut down by the EAPD pin on the AD1881A, using proper power management software.
This is particularly important for portable applications. In shutdown mode, the SSM2250 consumes only 60 µA.
REV. 0
–23–
AD1881A
5AVDD
R1
100k⍀
C1
1␮F
R2
49.9k⍀
U1
C2
100␮F
R3
FB
1k⍀ 600Z
AD1881A
U2
SSM2250RU
EAPD/CHAIN_IN
NC
R4
49.9k⍀
LEFT IN
LINE_OUT_L
C4
0.33␮F
MONO_OUT
STEREO
3.5mm JACK
C6
470pF
BTL+
LS1
INTERNAL
MONO
SPEAKER
BYPASS
GND
RIGHT IN
C7
0.33␮F
J1
C3
470pF
F2
R5
FB
1k⍀ 600Z
VDO
SE/BTL
R6
49.9k⍀
C5
100␮F
LEFT OUT/BLT
SHUTDOWN
LIN_OUT_R
NC
STEREO
HP/SPEAKER
OUTPUT
F1
RIGHT OUT
NC
NC
C8
0.1␮F
4⍀
NC = NO CONNECT
R7
49.9k⍀
Figure 15. Using the SSM2250 Amplifier for Stereo and Mono Output
GROUNDING AND LAYOUT
To reduce noise and emissions, Analog Devices recommends a split ground plane as shown in Figure 16. The purpose of splitting the
ground plane is to create a low noise analog area that is somewhat isolated from the digital ground current noise generated by the
system’s logic. All the analog circuitry should be placed on the analog ground plane area.
For reference purposes, and to return power supply currents, the analog and digital ground planes must be connected at some point,
ideally a small bridge under or near the Codec should be provided. A 0 Ω resistor or a ferrite bead should also be considered since
these allow some flexibility in optimizing the layout to meet EMC requirements.
DIGITAL
GROUND PLANE
CONNECT SPLIT GROUND
PLANES AT OR NEAR CODEC.
PIN 1
ISOLATION
TRENCH
AD1881A
ANALOG
GROUND PLANE
Figure 16. Recommended Split Ground Plane
ANALOG POWER SUPPLY
To minimize audio noise, the Codec analog power supply (AVDD) should be well decoupled and regulated. In PC systems it is recommended that the analog supply be derived from the 12 V PC power supply using a localized linear voltage regulator. Preferably,
the analog power supply should be connected to the Codec’s analog section using a ferrite bead.
–24–
REV. 0
AD1881A
+
LM78M05CP
IN
OUT
C2
0.1 F
R1
L1
3
600Z
C3
0.1 F
+
5AVDD
C4
10 F
2
C1
10 F
U1
GND
12V
0
Figure 17. Recommended Regulator Circuit for Analog Power Supply
If a power plane layer is being used in the system design, it is recommended that the analog power plane for the Codec also be split
(mirroring the analog ground plane). In this case, the analog power supply ferrite bead should bridge the isolation trench, close to the
Codec location.
REV. 0
–25–
AD1881A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.063 (1.60) MAX
0.354 (9.00) BSC
0.030 (1.45)
(0.75)
0.057
0.018
0.053 (0.45)
(1.35)
0.276 (7.0) BSC
0.276 (7.0) BSC
37
36
48
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0° – 7°
0° MIN
0.007 (0.18)
0.004 (0.09)
12
13
0.020 (0.5)
BSC
25
24
0.011 (0.27)
0.006 (0.17)
PRINTED IN U.S.A.
0.006 (0.15)
0.002 (0.05)
0.354 (9.00) BSC
0.030 (0.75)
0.018 (0.45)
C3747–8–4/00 (rev. 0) 00752
48-Lead Thin Plastic Quad Flatpack (LQFP)
(ST-48)
–26–
REV. 0