19-4438; Rev 0; 1/09 KIT ATION EVALU LE B A IL A AV Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Features The MAX17410 is available in a 48-pin, 7mm x 7mm TQFN package. o Dual-/Single-Phase Interleaved Quick-PWM Controller o ±0.5% VOUT Accuracy Over Line, Load, and Temperature o 7-Bit IMVP6+ DAC o Dynamic Phase Selection Optimizes Active/Sleep Efficiency o Transient Phase Overlap Reduces Output Capacitance o Active Voltage Positioning with Adjustable Gain o Accurate Lossless Current Balance o Accurate Droop and Current Limit o Remote Output and Ground Sense o Adjustable Output Slew-Rate Control o Power-Good Window Comparator o Power Monitor o Programmable Thermal-Fault Protection o Phase Fault Output (PHASEGD) o Drives Large Synchronous Rectifier FETs o 4.5V to 26V Battery Input Range o Output Overvoltage and Undervoltage Protection o Soft-Startup and Soft-Shutdown o Integrated Boost Switches o Low-Profile 7mm x 7mm, 48-Pin TQFN Package Applications Pin Configuration The MAX17410 is a 2-/1-phase interleaved QuickPWM™ step-down VID power-supply controller for notebook IMVP6+ CPUs. True out-of-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. The Quick-PWM control scheme provides instantaneous response to fast load current steps. Active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. The MAX17410 is intended for two different CPU core applications: either bucking down the battery directly to create the core voltage, or bucking down the +5V system supply. The single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, 2-stage conversion (stepping down the +5V system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. A slew-rate controller allows controlled transitions between VID codes. A thermistor-based temperature sensor provides programmable thermal protection. A power monitor provides a buffered analog voltage output proportional to the power delivered to the load. Voltage-Positioned, Step-Down Converters Quick-PWM is a trademark of Maxim Integrated Products, Inc. N.C. BST2 DH2 LX2 PGND2 DL2 VDD DL1 PGND1 39 22 VCC D3 40 21 GND D4 41 20 IN D5 42 19 CSPAVG D6 43 18 CSN1 SHDN 44 17 CSN2 DPRSLPVR 45 16 CCI DPRSTP 46 15 GNDS CLKEN 47 14 OUTS V3P3 48 13 ILIM 3 4 5 6 7 8 9 10 11 12 FB VPS TIME 2 SGND 1 PGDIN MAX17410 PHASEGD *EP = Exposed pad. CSP2 D2 NTC MAX17410GTM+ -40°C to +105°C 48 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. 23 THRM PIN-PACKAGE 38 VRHOT TEMP RANGE 24 D1 PMON PART CSP1 37 PSI Ordering Information 36 35 34 33 32 31 30 29 28 27 26 25 D0 PWRGD Notebook/Desktop Computers DH1 BST1 TOP VIEW Multiphase CPU Core Supply LX1 IMVP6+ Core Supply THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX17410 General Description MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies ABSOLUTE MAXIMUM RATINGS VCC, VDD, V3P3 to GND ...........................................-0.3V to +6V D0–D6, PSI, DPRSLPVR, DPRSTP to GND ..............-0.3V to +6V CSPAVG, CSP_, CSN_, ILIM to GND .......................-0.3V to +6V PWRGD, PHASEGD, VRHOT to GND ......................-0.3V to +6V FB, OUTS, CCI, TIME, PMON to GND........-0.3V to (VCC + 0.3V) PGDIN, NTC, THRM to GND ......................-0.3V to (VCC + 0.3V) CLKEN to GND..........................................-0.3V to (V3P3 + 0.3V) VPS to OUTS .........................................................-0.3V to +0.3V SHDN to GND (Note 1)...........................................-0.3V to +30V IN to GND ...............................................................-0.3V to +30V GNDS, SGND, PGND_ to GND .............................-0.3V to +0.3V DL_ to GND ................................................-0.3V to (VDD + 0.3V) BST_ to VDD............................................................-0.3V to +30V LX_ to BST_ ..............................................................-6V to +0.3V DH_ to LX_ ...............................................-0.3V to (VBST - +0.3V) Continuous Power Dissipation (48-pin, 7mm x 7mm TQFN) Up to +70°C ..............................................................2222mW Derating Above +70°C ..........................................27.8mW/°C Operating Temperature Range .........................-40°C to +105°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +165°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: SHDN may be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Input Voltage Range DC Output Voltage Accuracy Boot Voltage VOUT VCC, VDD 4.5 5.5 V3P3 3.0 3.6 IN 4.5 26 DAC codes from 0.8125V to 1.5000V -0.5 +0.5 DAC codes from 0.3750V to 0.8000V -7 +7 DAC codes from 0 to 0.3625V -20 Measured at FB with respect to GNDS, includes load regulation error (Note 2) VBOOT VCC = 4.5V to 5.5V, VIN = 4.5V to 26V OUTS Input Bias Current VPS floating, TA = +25°C OUTS-to-VPS Resistance +20 1.200 1.209 0.1 -0.1 3.5 SGND-to-AGND Resistance 10 -200 V % +0.1 μA 40 +200 mV 2.5 GNDS Input Range % mV 1.192 Line Regulation Error V GNDS Gain A GNDS VOUT/VGNDS 0.97 1.00 1.03 V/V GNDS Input Bias Current IGNDS V(OUTS, GNDS) = 1.0V -15 -10 -4 μA TIME Regulation Voltage VTIME RTIME = 71.5k 1.985 2.000 2.015 V 2 _______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL TIME Slew-Rate Accuracy On-Time Accuracy t ON Minimum Off-Time t OFF(MIN) CONDITIONS MIN TYP MAX RTIME = 71.5k (12.5mV/μs nominal) -10 +10 RTIME = 35.7k (25mV/μs nominal) to 178k (5mV/μs nominal) -15 +15 Soft-start and soft-shutdown: RTIME = 35.7k (3.125mV/μs nominal) to 178k (0.625mV/μs nominal) -16 +30 Slow: VDPRSTP = VDPRSLPVR = 5V, 1/4 normal slew rate, RTIME = 35.7k (6.25mV/μs nominal) to 178k (1.25mV/μs nominal) -12 +25 VIN = 10V, VFB = 1.0V, VCCI = (1.0V + VDIODE), measured at DH_, 300kHz per phase nominal (Note 3) 300 Measured at DH_ (Note 3) UNITS % 333 366 ns 300 375 ns 3 6 mA BIAS CURRENTS Quiescent Supply Current (VCC) ICC Measured at VCC, VDPRSLPVR = 5V, FB forced above the regulation point Quiescent Supply Current (VDD) IDD Measured at VDD, VDPRSLPVR = 0, FB forced above the regulation point, TA = +25°C 0.02 1 μA Quiescent Supply Current (V3P3) I3P3 Measured at V3P3, FB forced within the CLKEN power-good window, TA = +25°C 0.01 1 μA Quiescent Supply Current (IN) I IN 15 25 μA Shutdown Supply Current (VCC) ICC,SDN Measured at IN, VIN = 10V Measured at VCC, SHDN = GND, TA = +25°C 0.01 1 μA Shutdown Supply Current (VDD) IDD,SDN Measured at VDD, SHDN = GND, TA = +25°C 0.01 1 μA Shutdown Supply Current (V3P3) I3P3,SDN Measured at V3P3, SHDN = GND, TA = +25°C 0.01 1 μA Shutdown Supply Current (IN) IIN,SDN Measured at IN, VIN = 26V, SHDN = GND, VCC = 0V or 5V, TA = +25°C 0.01 0.1 μA mV FAULT PROTECTION Output OvervoltageProtection Threshold Output OvervoltagePropagation Delay VOVP t OVP Skip mode after output reaches the regulation voltage or PWM mode, measured at FB with respect to the voltage target set by the VID code (see Table 4) 250 300 350 Soft-start, soft-shutdown, skip mode, and output has not reached the regulation voltage; measured at FB 1.75 1.80 1.85 Minimum OVP threshold; measured at FB 0.8 FB forced 25mV above trip threshold 10 V μs _______________________________________________________________________________________ 3 MAX17410 ELECTRICAL CHARACTERISTICS (continued) MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output UndervoltageProtection Threshold VUVP Measured at FB with respect to the voltage target set by the VID code; see Table 4 -450 -400 -350 mV Output UndervoltagePropagation Delay tUVP FB forced 25mV below trip threshold CLKEN Startup Delay and Boot Time Period 10 μs Measured from the time when FB reaches the boot target voltage (Note 2) 20 60 100 μs PWRGD Startup Delay Measured at startup from the time when CLKEN goes low 3 6.5 10 ms Lower threshold, falling edge (undervoltage) -350 -300 -250 CLKEN and PWRGD Threshold Measured at FB with respect to the voltage target set by the VID code; see Table 4, 20mV hysteresis (typ) Upper threshold, rising edge (overvoltage) +150 tBOOT mV +200 +250 CLKEN and PWRGD Delay FB forced 25mV outside the PWRGD trip thresholds 10 μs PHASEGD Delay V(CCI, FB) forced 25mV outside trip thresholds 10 μs Measured from the time when FB reaches the target voltage (Note 2) 20 μs PHASEGD Transition Blanking Time (Phase 2 Enable Transitions) Number of DH2 pulses for which PHASEGD is blanked after phase 2 is enabled 32 Pulses CLKEN Output Low Voltage Low state, ISINK = 3mA CLKEN, PWRGD, and PHASEGD Transition Blanking Time (VID Transitions) tBLANK CLKEN Output High Voltage High state, I SOURCE = 3mA PWRGD, PHASEGD Output Low Voltage Low state, I SINK = 3mA PWRGD, PHASEGD Leakage Current High-impedance state; PWRGD, PHASEGD forced to 5V; TA = +25°C CSN_ Pulldown Resistances in Shutdown SHDN = 0, measured after soft-shutdown completed (DL = low) VCC Undervoltage-Lockout Threshold VUVLO(VCC) Rising edge, 65mV typical hysteresis, controller disabled below this level 0.4 V3P3 0.4 V V 0.4 V 1 μA 10 4.05 4.27 4.48 V 40 50 60 μA 0.995 1 1.025 μA/μA THERMAL PROTECTION THRM, NTC Pullup Current ITHRM, INTC VTHRM = VNTC = 1V Ratio of NTC Pullup Current to THRM Pullup Current INTC/ITHRM 4 VTHRM = VNTC = 1V _______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Measured at NTC with respect to THRM, VTHRM = 1V, falling edge; typical hysteresis = 100mV VRHOT Trip Threshold VRHOT Delay t VRHOT VRHOT Output On-Resistance MIN TYP -12 VNTC forced 25mV below VTHRM, VTHRM = 1V, falling edge 2 High-impedance state, VRHOT forced to 5V, TA = +25°C T SHDN MAX UNITS +12 mV 10 RON(VRHOT) Low state VRHOT Leakage Current Thermal-Shutdown Threshold CONDITIONS Typical hysteresis = 15°C μs 8 1 μA °C +160 VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Positive) Current-Limit Threshold Voltage (Negative) Accuracy Current-Limit Threshold Voltage (Zero Crossing) VLIMIT VCSP_ - VCSN_ VTIME - VILIM = 100mV 7 10 13 VTIME - VILIM = 500mV 45 50 55 ILIM = VCC 20 22.5 25 VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT VZERO VAGND - VLX_, DPRSLPVR = 5V CSPAVG, CSP_, CSN_ Common-Mode Input Range ILIM Input Current Measured at CSP2 TA = +25°C [VCSPAVG - (VCSN1 + VCSN2)/2] at IFB = 0 Droop Amplifier Offset Gm(FB) Power Monitor Output Voltage for Typical HFM Conditions 1 VPMON V(OUTS, GNDS) = 1.200V, I PMON = 0μA mV V VCC 0.4 V -0.2 +0.2 μA -0.1 +0.1 μA VCC 1 TA = +25°C -0.5 +0.5 TA = 0°C to +85°C -0.75 +0.75 IFB/[VCSPAVG - (VCSN1 + VCSN2)/2], VFB = VCSN_ = 0.45V to 1.5V mV 2 3 ICSPAVG, TA = +25°C ICSP_, ICSN_ I ILIM Droop Amplifier Transconductance +4 0 Phase 2 Disable Threshold CSPAVG, CSP_, CSN_ Input Current -4 mV 1.180 1.2 1.216 [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 225mV 1.65 1.7 1.743 [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 500mV 0.738 0.765 0.792 mV mS V Power Monitor Gain Referred to Output Voltage V(OUTS, GNDS) APMON/ VOUT [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 225mV, I PMON = 0μA 1.375 1.4167 1.452 V/V Power Monitor Gain Referred to [VCSPAVG - (VCSN1 + VCSN2)/2] APMON/VCS V(CSN, GNDS) = 1.200V, V(TIME, ILIM) = 225mV, I PMON = 0μA 104 113.33 123 V/V _______________________________________________________________________________________ 5 MAX17410 ELECTRICAL CHARACTERISTICS (continued) MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN Measured at PMON IPMON = 0 to 500μA with respect to I PMON = -100μA unloaded voltage -6 Power Monitor Load Regulation Current Balance Amplifier Offset (VCSP1 - VCSN1) - (VCSP2 - VCSN2) at ICCI = 0 -1.0 Current Balance Amplifier Transconductance Gm(CCI) TYP MAX μV/μA 50 ICCI/[(VCSP1 - VCSN1) - (VCSP2 - VCSN2)], VCSN_ = 0.45V to 1.5V UNITS mV +1.0 200 mV μS GATE DRIVERS DH_ Gate-Driver On-Resistance R ON(DH_) DL_ Gate-Driver On-Resistance R ON(DL_) DH_ Gate-Driver Source Current DH_ Gate-Driver Sink Current DL_ Gate-Driver Source Current DL_ Gate-Driver Sink Current Driver Propagation Delay High state (pullup) 0.9 2.5 Low state (pulldown) 0.7 2.0 High state (pullup) 0.7 2.0 Low state (pulldown) 0.25 0.7 IDH_(SOURCE) DH_ forced to 2.5V, BST_ - LX_ forced to 5V IDH_(SINK) 2.2 DH_ forced to 2.5V, BST_ - LX_ forced to 5V IDL_(SOURCE) DL_ forced to 2.5V IDL_(SINK) DL_ forced to 2.5V A A A 8 A DH_ low to DL_ high 20 DL_ low to DH_ high 20 DL_ falling, CDL_ = 3nF DL_ rising, CDL_ = 3nF 20 DH_ falling, CDH_ = 3nF 20 DH_ rising, CDH_ = 3nF 20 ns ns 20 10 R ON(BST_) 2.7 tDL_DH_ DH_ Transition Time 2.7 tDH_DL_ DL_ Transition Time Internal BST_ Switch On-Resistance BST_ - LX_ forced to 5V ns 20 LOGIC AND I/O Logic Input High Voltage VIH SHDN, PGDIN, DPRSLPVR Logic Input Low Voltage VIL SHDN, PGDIN, DPRSLPVR Low-Voltage Logic Input High Voltage VIHLV PSI, D0–D6, DPRSTP Low-Voltage Logic Input Low Voltage VILLV PSI, D0–D6, DPRSTP TA = +25°C, PGDIN Logic Input Current 6 TA = +25°C, SHDN, DPRSLPVR, PSI, DPRSTP, D0–D6 = 0 or 5V 2.3 V 1.0 0.67 V 0.33 -1.5 V -1 -1 _______________________________________________________________________________________ V -0.5 +1 μA Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = -40°C to +105°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Input Voltage Range VCC, VDD 4.5 5.5 V3P3 3.0 3.6 4.5 26 -0.75 +0.75 -10 +10 -25 +25 1.185 1.215 V 3.5 40 IN DAC codes from 0.8125V to 1.5000V DC Output Voltage Accuracy Boot Voltage VOUT Measured at FB with respect to DAC codes from GNDS, includes 0.3750V to 0.8000V load regulation error (Note 2) DAC codes from 0 to 0.3625V VBOOT OUTS to VPS Resistance GNDS Input Range V % mV -200 +200 mV GNDS Gain A GNDS VOUT/VGNDS 0.97 1.03 V/V GNDS Input Bias Current IGNDS V(OUTS, GNDS) = 1.0V -15 -4 μA TIME Regulation Voltage VTIME RTIME = 71.5k V TIME Slew-Rate Accuracy On-Time Accuracy t ON Minimum Off-Time t OFF(MIN) 1.985 2.015 RTIME = 71.5k (12.5mV/μs nominal) -10 +10 RTIME = 35.7k (25mV/μs nominal) to 178k (5mV/μs nominal) -15 +15 Soft-start and soft-shutdown: RTIME = 35.7k (3.125mV/μs nominal) to 178k (0.625mV/μs nominal) -16 +30 Slow: VDPRSTP = VDPRSLPVR = 5V, 1/4 normal slew rate, RTIME = 35.7k (6.25mV/ μs nominal) to 178k (1.25mV/μs nominal) -12 +25 VIN = 10V, VFB = 1.0V, VCCI = (1.0V + VDIODE), measured at DH_, 300kHz per phase nominal (Note 3) 290 Measured at DH_ (Note 3) 333 % 376 ns 375 ns BIAS CURRENTS Quiescent Supply Current (VCC) ICC Measured at VCC, VDPRSLPVR = 5V, FB forced above the regulation point 6 mA Quiescent Supply Current (IN) I IN Measured at IN, VIN = 10V 25 μA _______________________________________________________________________________________ 7 MAX17410 ELECTRICAL CHARACTERISTICS MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = -40°C to +105°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN VOVP Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to the voltage target set by the VID code (see Table 4) TYP MAX UNITS 250 350 mV Soft-start, soft-shutdown, skip mode, and output has not reached the regulation voltage; measured at FB 1.75 1.85 V FAULT PROTECTION Output Overvoltage-Protection Threshold Output Undervoltage-Protection Threshold VUVP Measured at FB with respect to the voltage target set by the VID code (see Table 4) -450 -350 mV CLKEN Startup Delay and Boot Time Period tBOOT Measured from the time when FB reaches the boot target voltage (Note 2) 20 100 μs PWRGD Startup Delay Measured at startup from the time when CLKEN goes low 3 10 ms Lower threshold, falling edge (undervoltage) -350 -250 CLKEN and PWRGD Threshold Measured at FB with respect to the voltage target set by the VID code (see Table 4), 20mV hysteresis (typ) Upper threshold, rising edge (overvoltage) +150 CLKEN Output Low Voltage Low state, ISINK = 3mA CLKEN Output High Voltage High state, I SOURCE = 3mA PWRGD, PHASEGD Output Low Voltage Low state, I SINK = 3mA PWRGD, PHASEGD Leakage Current High-impedance state; PWRGD, PHASEGD forced to 5V; TA = +25°C VCC Undervoltage-Lockout Threshold mV +250 0.4 V3P3 0.4 V V 0.4 V 1 μA VUVLO(VCC) Rising edge, 65mV typical hysteresis, controller disabled below this level 4.0 4.5 V THRM, NTC Pullup Current ITHRM, INTC VTHRM = VNTC = 1V 40 60 μA Ratio of NTC Pullup Current to THRM Pullup Current INTC/ITHRM VTHRM = VNTC = 1V 0.993 1.03 μA/μA -12 +12 mV 8 THERMAL PROTECTION VRHOT Trip Threshold VRHOT Output On-Resistance 8 Measured at NTC with respect to THRM, VTHRM = 1V, falling edge; typical hysteresis = 100mV RON(VRHOT) Low state _______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = -40°C to +105°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Positive) Current-Limit Threshold Voltage (Negative) Accuracy VLIMIT VTIME - VILIM = 100mV 7 13 VTIME - VILIM = 500mV 45 55 ILIM = VCC 20 25 -5 +5 mV 0 2 V 3 VCC 0.4 V -0.75 +0.75 -1 +1 IFB/[VCSPAVG - (VCSN1 + VCSN2)/2], VFB = VCSN- = 0.45V to 1.5V 1.173 1.224 [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 225mV 1.627 1.768 VCSP_ - VCSN_ VLIMIT(NEG) VCSP_ - VCSN_-, nominally -125% of VLIMIT CSPAVG, CSP_, CSN_ Common-Mode Input Range Phase 2 Disable Threshold Measured at CSP2 Droop Amplifier Offset [VCSPAVG - (VCSN1 + VCSN2)/2] at IFB = 0 Droop Amplifier Transconductance Gm(FB) Power Monitor Output Voltage for Typical HFM Conditions VPMON TA = +25°C TA = 0°C to +85°C V(OUTS, GNDS) = 1.200V, IPMON = 0μA [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 500mV mV mV mS V 0.734 0.796 Power Monitor Gain Referred to Output Voltage V(OUTS, GNDS) APMON/VOUT [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 225mV, I PMON = 0μA 1.375 1.452 V/V Power Monitor Gain Referred to [VCSPAVG - (VCSN1 + VCSN2)/2] APMON/VCS V(CSN, GNDS) = 1.200V, V(TIME, ILIM) = 225mV, I PMON = 0μA 104 123 V/V Power Monitor Load Regulation Measured at PMON with respect to unloaded voltage Current Balance Amplifier Offset (VCSP1 - VCSN1) - (VCSP2 - VCSN2) at ICCI = 0 I PMON = 0 to 500μA -6 -1.5 μV/μA +1.5 mV _______________________________________________________________________________________ 9 MAX17410 ELECTRICAL CHARACTERISTICS (continued) MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57kΩ from FB to VPS, [D6–D0] = [0101000]; TA = -40°C to +105°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GATE DRIVERS DH_ Gate-Driver On-Resistance R ON(DH_) DL_ Gate-Driver On-Resistance R ON(DL_) Internal BST_ Switch On-Resistance R ON(BST_) BST_ - LX_ forced to 5V High state (pullup) 2.5 Low state (pulldown) 2.0 High state (pullup) 2.0 Low state (pulldown) 0.7 IBST_ = 10mA 20 LOGIC AND I/O Logic Input High Voltage VIH SHDN, PGDIN, DPRSLPVR Logic Input Low Voltage VIL SHDN, PGDIN, DPRSLPVR Low-Voltage Logic Input High Voltage VIHLV PSI, D0–D6, DPRSTP Low-Voltage Logic Input Low Voltage VILLV PSI, D0–D6, DPRSTP 2.3 V 1.0 0.67 V V 0.33 V Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. The output voltage has a DC regulation higher than the trip level by 50% of the output ripple. When pulse skipping, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DL_ and DH_ pins, with LX_ forced to GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual incircuit times might be different due to MOSFET switching speeds.s 10 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 1.1500V, TA = +25°C, unless otherwise specified.) 7V 90 1.00 0.89 OUTPUT VOLTAGE (V) 1.10 1.05 0.90 MAX17410 toc02 MAX17410 toc01 100 EFFICIENCY (%) OUTPUT VOLTAGE (V) 1.15 1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT(HFM) = 0.875V) 2-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT(HFM) = 1.075V) 80 12V 70 20V MAX17410 toc03 2-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT(HFM) = 1.075V) 0.88 PWM MODE 0.87 0.86 0.85 SKIP MODE 0.84 60 0.83 20 40 30 0.1 1 0 100 5 10 15 20 LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A) 1-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT(LFM) = 0.875V) SWITCHING FREQUENCY vs. LOAD CURRENT NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (VOUT(HFM) = 1.075V) 100 0 20 30 40 NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE AT SKIP MODE (VOUT(HFM) = 1.075V) 0.1 60 SAMPLE SIZE = 100 +85°C +25°C 50 40 30 20 IIN 35 0.8175 0.8165 0.8155 0.8145 21 24 SAMPLE SIZE = 100 +85°C +25°C 25 20 15 10 0 OUTPUT VOLTAGE (V) 18 30 0 0.8135 24 0.8115 INPUT VOLTAGE (V) 21 0.8125 18 0.8105 15 0.8095 12 15 Gm(FB) TRANSCONDUCTANCE DISTRIBUTION 5 0.8085 9 12 40 10 0.8075 DPRSLPVR = VCC 9 INPUT VOLTAGE (V) 70 SAMPLE PERCENTAGE (%) ICC + IDD 1 6 0 0.8125V OUTPUT-VOLTAGE DISTRIBUTION MAX17410 toc07 10 0.01 0 50 LOAD CURRENT (A) 1216 10 1212 0 1208 100 DPRSLPVR = GND PSI = VCC 1204 10 SAMPLE PERCENTAGE (%) 1 LOAD CURRENT (A) MAX17410 toc08 0.1 MAX17410 toc06 DPRSLPVR = VCC DPRSLPVR = GND 1196 30 ICC + IDD 25 50 SKIP MODE PWM MODE 50 1200 40 150 IIN 1192 50 200 75 1188 20V VOUT(HFM) = 1.075V 250 1184 60 300 100 1180 12V VOUT(LFM) = 0.875V 350 SUPPLY CURRENT (mA) 70 MAX17410 toc05 80 400 SWITCHING FREQUENCY (kHz) MAX17410 toc04 7V SUPPLY CURRENT (mA) 10 MAX17410 toc09 10 90 EFFICIENCY (%) 0.82 50 0 1220 0.95 TRANSCONDUCTANCE (μS) ______________________________________________________________________________________ 11 MAX17410 Typical Operating Characteristics Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 1.1500V, TA = +25°C, unless otherwise specified.) CURRENT BALANCE vs. LOAD CURRENT MAX17410 toc10 25 VOUT = 1.075V SOFT-START WAVEFORM (UP TO CLKEN) MAX17410 toc11 0.5 5V 0.4 20 0.2 15 0.1 VCSPN1 - VCSPN2 0 10 -0.1 VCSP1 - VCSN1 -0.2 5 C 0 D 0 -0.4 0 B 0 1.075V -0.3 VCSP2 - VCSN2 A 0 3.3V 0.3 ΔV(CSP-CSN)1,2 (mV) V(CSP-CSN)1,2 (mV) MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies E 0 -0.5 0 5 200μs/div 10 15 20 25 30 35 40 45 50 A. SHDN, 5V/div B. CLKEN, 3.3V/div C. VOUT, 500mV/div LOAD CURRENT (A) MAX17410 toc13 MAX17410 toc12 5V 0 3.3V 0 3.3V 0 3.3V 0 1.075V LOAD-TRANSIENT RESPONSE (HFM MODE) SHUTDOWN WAVEFORM SOFT-START WAVEFORM (UP TO PWRGD) A B C D E 5V 0 3.3V 0 3.3V 0 5V MAX17410 toc14 A 47A B 9A 1.075V 12 A C D 0 1.075V E 0 0 F 0 0 F 0 G 0 G 1ms/div A. SHDN, 10V/div B. CLKEN, 6.6V/div C. PWRGD, 10V/div D. PHASEGD, 10V/div D. ILX1, 10A/div E. ILX2, 10A/div IOUT = 0 B 1V 25A C 5A D 5A 100μs/div E. VOUT, 500mV/div F. ILX1, 10A/div G. ILX2, 10A/div IOUT = 0 A. SHDN, 10V/div B. PWRGD, 10V/div C. CLKEN, 6.6V/div D. DL1, 5V/div 20μs/div E. VOUT, 500mV/div F. ILX1, 10A/div G. ILX2, 10A/div A. IOUT = 9A–47A B. VOUT, 50mV/div ______________________________________________________________________________________ C. ILX1, 10A/div D. ILX2, 10A/div Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies LOAD-TRANSIENT RESPONSE (LFM MODE) MAX17410 toc15 20A MAX17410 toc17 MAX17410 toc16 A 5A ENTERING DEEPER SLEEP EXITING TO NEAREST VID ENTERING DEEPER SLEEP EXITING TO LFM (SLOW C4) 0.875V B 5V A 0 5V 0 1.075V B 5V A 0 5V 0 1.075V B C C 0.675V 0.65V 20A C 0 D 0 D 0 E 0 E 5A 20μs/div A. IOUT = 5A–20A B. VOUT, 20mV/div C. ILX1, 10A/div ENTERING DEEPER SLEEP EXITING TO LFM (FAST C4) D3 10mV DYNAMIC VID CODE CHANGE D0 12.5mV DYNAMIC VID CODE CHANGE MAX17410 toc18 5V 40μs/div A. DPRSTP, 5V/div D. ILX2, 10A/div B. DPRSLPVR, 10V/div E. ILX1, 10A/div C. VOUT, 200mV/div IOUT = 3Av 100μs/div A. DPRSTP, 5V/div D. ILX2, 10A/div B. DPRSLPVR, 10V/div E. ILX1, 10A/div C. VOUT, 200mV/div IOUT = 3A PSI = GND DPRSLPVR = GND MAX17410 toc20 MAX17410 toc19 A 5V A 0 5V 0 1.075V 0 A 0 B C 5V 1.075V B B 1.075V 1.0625V 0.975V 0.65V 0 D 0 E 100μs/div A. DPRSTP, 5V/div D. ILX2, 10A/div B. DPRSLPVR, 10V/div E. ILX1, 10A/div IOUT = 3Av C. VOUT, 200mV/div 0 C 5A C 0 D 5A D 100μs/div 100μs/div A. VID0, 5V/div B. VOUT, 20mV/div C. ILX1, 10A/div D. ILX2, 10A/div A. D3, 5V/div B. VOUT, 50mV/div IOUT, = 10A C. ILX1, 10A/div D. ILX2, 10A/div ______________________________________________________________________________________ 13 MAX17410 Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 1.1500V, TA = +25°C, unless otherwise specified.) Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 1.1500V, TA = +25°C, unless otherwise specified.) MAX17410 POWER MONITOR vs. LOAD CURRENT POWER MONITOR VID TRANSITION RESPONSE MAX17410 POWER MONITOR vs. OUTPUT VOLTAGE 1.0 0.5 MAX17410 toc22 VIN = 12V IOUT = 20A 0.8 POWER MONITOR (V) VOUT = 1.075V MAX17410 toc23 1.0 MAX17410 toc21 1.5 POWER MONITOR (V) MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies A 0 1.075V 0.6 B 0.975V 0.35V 0.4 C 5A 0.2 DPRSLPVR = VCC DPRSLPVR = GND D 5A 0 0 0 5 10 15 20 25 30 35 0 40 LOAD CURRENT (A) 0.3 0.6 0.9 1.2 100μs/div 1.5 A. D3, 5V/div B. VOUT, 50mV/div IOUT = 10A OUTPUT VOLTAGE (V) OUTPUT UNDERVOLTAGE FAULT C. VPMON, 50mV/div D. ILX1, 10A/div E. ILX2, 10A/div BIAS SUPPLY REMOVAL (UVLO RESPONSE) OUTPUT OVERVOLTAGE WAVEFORM MAX17410 toc25 MAX17410 toc24 60A 0 0.875V MAX17410 toc26 5V A A 1.075V B 0 5V A C 0 3.3V B 0 3.3V 3.3V E B 0 5V C 0 0 100μs/div 100μs/div A. IOUT, 100A/div B. VOUT, 500mV/div C. DL, 5V/div D. PWRGD, 3.3V/div E. ILX1, 10A/div 1.075V 0 D 0 25A 14 5V A. VOUT, 500mV/div B. PWRGD, 3.3V/div C. DL1, 5V/div DPRSLPVR = VCC C 0 5V 0 D 0 E 40μs/div A. 5V BIAS SUPPLY, 2V/div D. DL1, 5V/div B. VOUT, 500mV/div E. ILX1, 10A/div C. PWRGD, 3.3V/div IOUT = 5A ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies PIN 1 NAME FUNCTION PWRGD Open-Drain Power-Good Output. After output voltage transitions, except during power-up and powerdown, if FB is in regulation, then PWRGD is high impedance. PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes high if FB is within the PWRGD threshold window. PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions), and continues to be forced high impedance for an additional 20μs after the transition is completed. The PWRGD upper threshold is blanked during any downward output voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-ratecontrolled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. A pullup resistor on PWRGD causes additional finite shutdown current. Power-State Indicator. This low-voltage logic input indicates power usage and sets the operating mode together with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if PSI is forced low, the controller is immediately set to 1-phase forced-PWM mode. The controller returns to 2-phase forced-PWM mode when PSI is forced high. 2 PSI DPRSLPVR PSI 1 1 0 0 0 1 0 1 Mode Very low current (1-phase skip) Low current (approx 3A) (1-phase skip) Intermediate power potential (1-phase PWM) Max power potential (full-phase PWM: 2-phase or 1-phase as set by user at CSP2) The controller is in 2-phase skip mode during startup, but is in 2-phase forced-PWM mode during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. The controller is also in 2-phase skip mode while in boot mode, but is in 2-phase forced-PWM mode during the transition from boot mode to VID mode, irrespective of the DPRSLPVR and PSI logic levels. However, if phase 2 is disabled by connecting CSP2 to VCC, then only phase 1 is active in the above modes. Power Monitor Output: V(PWR) = K PWR x V(OUTS, GNDS) x V(CSPAVG, CSN)/V(TIME, ILIM) 3 PMON where KPWR = 21.25 typical. If ILIM is externally connected to a 5V rail to enable the internal default/preset current-limit threshold, then the V(TIME, ILIM) value to be used in the above equation is 225mV. Do not use the power monitor in any configuration that would cause its output V(PMON) to exceed (VCC - 0.5V). PMON is pulled to ground when the MAX17410 is in shutdown. 4 THRM Resistive Input of Thermal Comparator. Connect a resistor to ground to set the VRHOT threshold. THRM and NTC have matched 50μA current sources, so the resistance value = the NTC resistance at the desired high temperature. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. 5 VRHOT Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. VRHOT is high impedance in shutdown. 6 NTC Thermistor Input of Thermal Comparator. Connect a standard thermistor to ground. THRM and NTC have matched 50μA current sources, so the resistance value = the NTC resistance at the desired high temperature. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. ______________________________________________________________________________________ 15 MAX17410 Pin Description Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410 Pin Description (continued) PIN 7 8 NAME FUNCTION PHASEGD Open-Drain Phase-Good Output. Used to signal the system that one of the two phases either has a fault condition or is not matched with the other. Detection is done by identifying the need for a large (more than 40%) on-time difference between phases to achieve or move towards current balance. PHASEGD is low in shutdown, and when phase 2 is disabled by connecting CSP2 to VCC. PHASEGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions), and when phase 2 is disabled by the DPRSLPVR and/or PSI inputs. When phase 2 is reenabled, PHASEGD stays high impedance for 32 DH2 pulses, after which it monitors the difference between the on-times of the two phases. PHASEGD is also forced high impedance when VFB is below 0.5V. PGDIN Power-Good Logic Input. Indicates the power status of other system rails and used for supply sequencing. Connect this pin to the 5V supply rail or float it if the feature is not needed. During startup, after soft-starting to the boot voltage, the output voltage remains at VBOOT, and the CLKEN and PWRGD outputs remain high and low, respectively, as long as the PGDIN input stays low. When PGDIN later goes high, the output is allowed to transition to the voltage set by the VID code, and CLKEN is allowed to go low. During normal operation, if PGDIN goes low, the controller immediately forces CLKEN high and PWRGD low, and slews the output to the boot voltage while in 2-phase skip mode at 1/8 the normal slew rate set by the TIME resistor. The output then stays at the boot voltage until the controller is turned off or power cycled, or until PGDIN goes high again. Feedback Voltage Input, and Output of the Voltage-Positioning Transconductance Amplifier. The voltage at the FB pin is compared with the slew-rate-controlled target voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator (slow, accurate regulation loop). Having sufficient ripple signal at FB that is in-phase with the sum of the inductor currents is essential for cycle-by-cycle stability. 9 FB Connect resistor RFB between FB and VPS to set the droop based on the voltage-positioning gain requirements: RFB = RDROOP/[RSENSE x Gm(FB)] where RDROOP is the desired voltage-positioning slope, Gm(FB) = 1.2mS typ, and RSENSE is the effective current-sense resistance that is used to provide the (CSPAVG, CSN_) current-sense voltage. If lossless sensing (inductor DCR sensing) is used, consider using a thermistor as part of the CSPAVG filter network to minimize the temperature dependence of the voltage-positioning slope. FB is high impedance in shutdown. 10 VPS 11 SGND Internally Shorted to OUTS Through a 10 Resistance Internally Shorted SGND (Pin 11) to AGND (Pin 21) Slew-Rate Adjustment Pin. The total resistance RTIME from TIME to GND sets the internal slew rate. SLEW RATE = (12.5mV/μs) x (71.5k/RTIME) where RTIME is between 35.7k and 178k. 12 13 16 TIME ILIM This “normal” slew rate applies to transitions into and out of the low-power pulse-skipping modes and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is always 1/8 of normal. If DPRSLPVR and DPRSTP are both high, then the slew rate is reduced to 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew rate defined above. Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_, CSN_) are precisely 1/10 the differential voltage V(TIME, ILIM) over a 0.1V to 0.5V range of V(TIME, ILIM). The valley negative current-limit thresholds are typically -125% of the corresponding valley positive current-limit thresholds. Connect ILIM to VCC to get the default current-limit threshold setting of 22.5mV typ. ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies PIN NAME FUNCTION 14 OUTS Output Remote Sense. Internally shorted to VPS through a 10 resistance. OUTS is also the voltage feedback input to the power monitor. 15 GNDS Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load. GNDS internally connects to a transconductance amplifier that fine tunes the output voltage— compensating for voltage drops from the regulator ground to the load ground. 16 CCI 17 CSN2 Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. 18 CSN1 Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Current-Balance Compensation. Connect a 470pF capacitor between CCI and the positive side of the feedback remote-sense input (or between CCI and GND). CCI is internally forced low in shutdown. 19 CSPAVG Positive Input of the Output Current-Sense Averaging Network. This input should be connected to the positive current-sense averaging network (see the standard 2-phase IMVP6+ application circuit of Figure 1) and is utilized for load line control and power monitoring (input of the transconductance amplifiers used for FB and PMON). 20 IN Input Sense for On-Time Control. An internal resistor sets the switching frequency to 300kHz per phase. IN is high impedance in shutdown. 21 GND Analog Ground Connect 22 VCC 23 CSP2 Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum. Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive side of the output current-sensing resistor, or to the filtering capacitor if the DC resistance of the output inductor is used for current sensing. This pin is utilized for current limit and current balance only. 24 CSP1 Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of the output current-sensing resistor, or to the filtering capacitor if the DC resistance of the output inductor is used for current sensing. This pin is utilized for current limit and current balance only. 25 N.C. No Connection. Not internally connected. 26 BST2 Phase 2 Boost Flying Capacitor Connection. BST2 is the internal upper supply rail for the DH2 high-side gate driver. An internal switch between VDD and BST2 charges the BST2 - LX2 flying capacitor while the low-side MOSFET is on (DL2 pulled high). 27 DH2 Phase 2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown. 28 LX2 Phase 2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also used as an input to phase 2’s zero-crossing comparator. 29 PGND2 Connect CSP2 to VCC to disable phase 2 and use the MAX17410 as a single-phase controller. In this configuration, connect LX2 to GND, connect BST2 to VDD, CSN2 to CSN1, and float DH2, DL2, CCI, and PHASEGD. Power Ground. PGND2 is the internal lower supply rail for the DL2 low-side gate driver. 30 DL2 Phase 2 Low-Side Gate-Driver Output. DL2 swings from PGND2 to VDD. DL2 is forced low in shutdown. DL2 is forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL2 is forced low in skip mode after detecting an inductor current zero crossing. 31 VDD Supply Voltage Input for the DL_ Drivers. VDD is also the supply voltage used to internally recharge the BST_ - LX_ flying capacitor during the times the respective DL_ are high. Connect VDD to the 4.5V to 5.5V system supply voltage. Bypass VDD to GND with a 1μF or greater ceramic capacitor. ______________________________________________________________________________________ 17 MAX17410 Pin Description (continued) Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410 Pin Description (continued) PIN NAME FUNCTION Phase 1 Low-Side Gate-Driver Output. DL1 swings from PGND1 to VDD. DL1 is forced low in shutdown. DL1 is forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL1 is forced low in skip mode after detecting an inductor current zero crossing. 32 DL1 33 PGND1 34 LX1 Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also used as an input to phase 1’s zero-crossing comparator. 35 DH1 Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown. 36 BST1 Phase 1 Boost Flying Capacitor Connection. BST1 is the internal upper supply rail for the DH1 high-side gate driver. An internal switch between VDD and BST1 charges the BST1 - LX1 flying capacitor, while the low-side MOSFET is on (DL1 pulled high). 37–43 D0–D6 Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0–D6 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set by the VID code indicated by the logic-level voltages on D0–D6 (see Table 4). SHDN Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put the IC into the 1μA (max at TA = +25°C) shutdown state. During startup, the output voltage is ramped up at 1/8 the slew rate set by the TIME resistor to the boot voltage. During the transition from normal operation to shutdown, the output voltage is ramped down at 1/8 the slew rate set by the TIME resistor. Forcing SHDN to 11V ~ 13V disables overvoltage protection, undervoltage protection, and thermal shutdown, clears the fault latches, disables transient phase overlap, disables soar suppression, and turns off the internal BST_-to-VDD switches. However, internal diodes still exist between BST_ and VDD in this state. 44 Power Ground. PGND1 is the internal lower supply rail for the DL1 low-side gate driver. 3.3V Logic Input. Indicates power usage and sets the operating mode together with PSI as shown in the truth table below. When DPRSLPVR is forced high, the controller is immediately set to 1phase automatic pulse-skipping mode. The controller returns to forced-PWM mode when DPRSLPVR is forced low and the output is in regulation. The PWRGD upper threshold is blanked during any downward output voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. During this blanking period, the overvoltage fault threshold is changed from a tracking [VID + 300mV] threshold to a fixed 1.8V threshold. 45 DPRSLPVR DPRSLPVR PSI 1 1 0 0 0 1 0 1 Mode Very low current (1-phase skip) Low current (approx 3A) (1-phase skip) Intermediate power potential (1-phase PWM) Max power potential (full-phase PWM: 2-phase or 1-phase as set by user at CSP2) The controller is in 2-phase skip mode during startup, but is in 2-phase forced-PWM mode during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. The controller is in 2-phase skip mode while in boot mode, but is in 2-phase forced-PWM mode during the transition from boot mode to VID mode, irrespective of the DPRSLPVR and PSI logic levels. However, if phase 2 is disabled by connecting CSP2 to VCC, then only phase 1 is active in the above modes. 18 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies PIN NAME FUNCTION Low-Voltage Logic Input Signal. This is usually the logical complement of the DPRSLPVR signal. However, there is a special condition during C4 exit when both DPRSTP and DPRSLPVR could temporarily be simultaneously high. If this happens, the MAX17410 reduces the slew rate to 1/4 the normal (RTIME-based) slew rate for the duration of this condition. The slew rate returns to normal when this condition is exited. Note that only DPRSLPVR and PSI (but not DPRSTP) determine the mode of operation (PWM vs. skip and number of active phases). 46 DPRSTP DPRSLPVR DPRSTP 0 0 0 1 1 1 0 1 Functionality Normal slew rate, 1- or 2-phase forced-PWM mode (DPRSLPVR low DPRSTP is ignored) Normal slew rate, 1- or 2-phase forced-PWM mode (DPRSLPVR low DPRSTP is ignored) Normal slew rate, 1-phase automatic pulse-skipping mode Slew rate reduced to 1/4th of normal, 1-phase automatic pulse-skipping mode 47 CLKEN Clock Enable CMOS Push-Pull Logic Output Powered by V3P3. This inverted logic output indicates when the output voltage sensed at FB is in regulation. CLKEN is forced high in shutdown and during soft-start and soft-stop transitions. CLKEN is forced low during dynamic VID transitions and for an additional 20μs after the transition is completed. CLKEN is the inverse of PWRGD, except for the 5ms PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram (Figure 9). The CLKEN upper threshold is blanked during any downward output voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. 48 V3P3 3.3V Supply Input for the CLKEN CMOS Push-Pull Logic Output. Connect to the 3.0V to 3.6V system supply voltage. — EP Exposed Backplate (Paddle) of Package. Internally connected to analog ground. Connect to the ground plane through a thermally enhanced via. ______________________________________________________________________________________ 19 MAX17410 Pin Description (continued) MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies 37 38 39 40 41 42 43 VID INPUTS 44 ON OFF (VRON) 45 47 48 3.3V D0 D1 D2 D3 D4 D5 D6 VCC GND VDD IN SHDN BST1 DPRSLPVR DH1 CLKEN LX1 V3P3 DL1 10kΩ R4 10kΩ R5 10kΩ PGND1 1 5 7 4.99kΩ PWRGD CSP1 VRHOT PHASEGD PGDIN CSN1 4 THRM CSN2 R1 10Ω 22 21 31 C1 1μF 5V BIAS INPUT C2 1μF AGND 36 R9 0Ω CIN PWR 35 34 NHI C4 0.22μF 32 NLO D1 CCI 100kΩ NTC β = 4700 3.32kΩ PWR 6 N.C. CSP2 3 C8 0.1μF PMON BST2 DH2 13 ILIM LX2 DL2 10kΩ 12 TIME 11 SGND OPEN AGND 10 PGND2 OUTS 0.1μF 18 17 0Ω 0.1μF 2kΩ 0.47μF CORE OUTPUT 16 10kΩ NTC β = 3380 25 0.1μF 23 26 R13 0Ω OPEN 28 30 NHI C8 0.22μF 3.32kΩ 1Ω PWR L2 NLO D1 29 14 COUT 2kΩ 27 R20 10Ω PWR R22 25Ω VCC_SENSE C9 1000pF AGND 15 4.02kΩ 9 1.5kΩ 19 VPS GNDS OPEN COUT = 4 x 330μF/4.5mΩ + 32 x 10μF MLCC 8 NTC 46 DPRSTP 2 PSI 61.9kΩ PWR OPEN CSPAVG AGND 1Ω OPEN 24 COUT MAX17410 AGND OPEN 10kΩ L1 0.36μH 0.82mΩ 33 1000pF AGND INPUT 7V TO 24V 20 FB REMOTE-SENSE INPUTS R21 10Ω C10 1000pF AGND REMOTE-SENSE FILTERS VSS_SENSE R23 25Ω CATCH RESISTORS REQUIRED WHEN CPU PWR NOT POPULATED Figure 1. Standard 2-Phase IMVP6+ Application Circuit 20 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410 MAX17410 BST2 NTC THRM DH2 SECONDARY PHASE DRIVERS VRHOT LX2 DL2 PGND2 BLANK CSP2 EN2 1X CSN2 PHASEGD Q 0.1X TRIG PHASE 2 ON-TIME ONE-SHOT CSP1 CSN1 VCC REF (2.0V) GND CURRENTBALANCE FAULT 1X MINIMUM OFF-TIME 0.1X Q REF 5ms STARTUP DELAY CCI CSN2 TRIG Gm(CCI) ONE SHOT PHASE 1 ON-TIME ONE-SHOT 2.5Ω SGND FB DPRSLPVR ILIM TIME Q CSP1 FB Gm(CCI) TRIG CSN1 IN R-TO-I CONVERTER D0–D6 CSP2 MAIN PHASE DRIVERS R DAC Q DPRSTP BST1 S DH1 SHDN LX1 S PGND1 FAULT TARGET Q Q LX1 Q R 1mV T VDD REF SKIP Gm(CCV) DL1 PGND1 PWRGD TARGET + 200mV TARGET - 300mV 5ms STARTUP DELAY FB V3P3 CSN1 CSN2 EN2 CSPAVG 60μs STARTUP DELAY VCC Gm(FB) SKIP BLANK PHASE CONTROL GNDS CSPAVG, CSN1, CSN2 10Ω PGDIN DRPSLPVR CLKEN PSI OUTS OUTS GNDS POWER MONITOR PMON VPS Figure 2. Functional Diagram ______________________________________________________________________________________ 21 MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Table 1. Component Selection for Standard Applications DESIGN PARAMETERS IMVP6+ SV Circuit IMVP6+ LV Figure 1 Figure 1 7V to 20V 7V to 20V Maximum Load Current 44A (34A) 23A (19A) Transient Load Current 35A (10A/μs) 18A (10A/μs) Load Line -2.1mV/A -4mV/A NEC/Tokin MPC1055LR36 0.36μH, 32A, 0.8m NEC/Tokin MPC1055LR36 0.36μH, 32A, 0.8m High-Side MOSFET (NH) Siliconix 1x Si4386DY 7.8m/9.5m (typ/max) Siliconix 1x Si4386DY 7.8m/9.5m (typ/max) Low-Side MOSFET (NL) Siliconix 2x Si4642DY 3.9m/4.7m (typ/max) Siliconix 2x Si4642DY 3.9m/4.7m (typ/max) Output Capacitors (COUT) 3x 330μF, 6m, 2.5V Panasonic EEFSX0D0D331XR 28x 10μF, 6V ceramic (0805) 3x 330μF, 6m, 2.5V Panasonic EEFSX0D0D331XR 28x 10μF, 6V ceramic (0805) Input Capacitors (CIN) 4x 10μF, 25V ceramic (1210) 4x 10μF, 25V ceramic (1210) Input Voltage Range Inductance (L) TIME-ILIM Resistance (R1) 10k 6.19k ILIM-GND Resistance (R2) 61.9k 64.9k FB Resistance (RFB) 4.02k 7.68k LX-CSP Resistance (R5) 2k 2k 1.50k 1.50k open open 10k NTC B = 3380 TDK NTCG163JH103F 10k NTC B = 3380 TDK NTCG163JH103F 0.47μF, 6V ceramic (0805) 0.47μF, 6V ceramic (0805) CSP-CSN Series Resistance (R6) Parallel NTC Resistance (R7) DCR Sense NTC (NTC1) DCR Sense Capacitance (CSENSE) Table 2. Component Suppliers MANUFACTURER WEBSITE MANUFACTURER WEBSITE AVX Corporation www.avxcorp.com Pulse Engineering www.pulseeng.com BI Technologies www.bitechnologies.com Renesas Technology Corp. www.renesas.com Central Semiconductor Corp. www.centralsemi.com SANYO Electric Co., Ltd. www.sanyodevice.com Fairchild Semiconductor www.fairchildsemi.com Sumida Corp. www.sumida.com International Rectifier www.irf.com Taiyo Yuden www.t-yuden.com KEMET Corp. www.kemet.com TDK Corp. www.component.tdk.com NEC/TOKIN America, Inc. www.nec-tokin.com TOKO America, Inc. www.tokoam.com Panasonic Corp. www.panasonic.com Vishay/Siliconix www.vishay.com 22 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Free-Running, Constant On-Time PWM Controller with Input Feed-Forward The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure 2). This architecture relies on the output filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to the input voltage, and directly proportional to the output voltage or the difference between the main and secondary inductor currents (see the On-Time One-Shot section). Another one-shot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley current-limit threshold, and the minimum off-time one-shot times out. The controller maintains 180° out-ofphase operation by alternately triggering the main and secondary phases after the error comparator drops below the output-voltage set point. Dual 180° Out-of-Phase Operation The two phases in the MAX17410 operate 180° out-ofphase to minimize input and output filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component count—reducing cost, board space, and component power requirements—making the MAX17410 ideal for high-power, cost-sensitive applications. Typically, switching regulators provide power using only one phase instead of dividing the power among several phases. In these applications, the input capacitors must support high instantaneous current requirements. The high RMS ripple current can lower efficiency due to I2R power loss associated with the input capacitor’s effective series resistance (ESR). Therefore, the system typically requires several lowESR input capacitors in parallel to minimize input voltage ripple, to reduce ESR-related power losses, and to meet the necessary RMS ripple current rating. With the MAX17410, the controller shares the current between two phases that operate 180° out-of-phase, so the high-side MOSFETs never turn on simultaneously during normal operation. The instantaneous input current of either phase is effectively halved, resulting in reduced input voltage ripple, ESR power loss, and RMS ripple current (see the Input Capacitor Selection section). Therefore, the same performance may be achieved with fewer or less expensive input capacitors. +5V Bias Supply (VCC and VDD) The Quick-PWM controller requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook’s 95% efficient +5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V bias supply can be generated with an external linear regulator. The +5V bias supply must provide V CC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: ( IBIAS = I CC + fSW Q G(LOW) + Q G(HIGH) ) where ICC is provided in the Electrical Characteristics table, fSW is the switching frequency, and QG(LOW) and Q G(HIGH) are the MOSFET data sheet’s total gatecharge specification limits at VGS = 5V. VIN and VDD can be connected together if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup. Switching Frequency IN (Pin 20) Open-Circuit Protection The MAX17410 input sense (IN) is used to adjust the ontime. An internal resistor sets the switching frequency to 300kHz per phase. IN is high impedance in shutdown. On-Time One-Shot The core of each phase contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFET’s on-time. The one-shot for the main phase varies the ontime in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the V+ input, and proportional to the feedback voltage (VFB): t ( V + 0.075V ) t ON(MAIN) = SW FB VIN where the switching period (tSW = 1/fSW) is set to 3.3μs internally, and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch. ______________________________________________________________________________________ 23 MAX17410 MAX17410 Detailed Description MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies The one-shot for the secondary phase varies the ontime in response to the input voltage and the difference between the main and secondary inductor currents. Two identical transconductance amplifiers integrate the difference between the master and slave current-sense signals. The summed output is internally connected to CCI, allowing adjustment of the integration time constant with a compensation network connected between CCI and FB. The resulting compensation current and voltage are determined by the following equations: I CCI = G m ( VCSP1 - VCSN1) - G m ( VCSP2 - VCSP2 ) VCCI = VFB + I CCIZ CCI where ZCCI is the impedance at the CCI output. The secondary on-time one-shot uses this integrated signal (VCCI) to set the secondary high-side MOSFET’s ontime. When the main and secondary current-sense signals become unbalanced, the transconductance amplifiers adjust the secondary on-time, which increases or decreases the secondary inductor current until the current-sense signals are properly balanced: ⎛V + 0.075V ⎞ t ON(SEC) = t SW ⎜ CCI ⎟⎠ VIN ⎝ ⎛ V + 0.07 ⎛ I CCIZ CCI ⎞ 75V ⎞ = t SW ⎜ FB ⎟⎠ + t SW ⎜⎝ V ⎟ VIN ⎝ IN ⎠ = (Main On-ttime) + ( Secondary Current Balance Correction) This algorithm results in a nearly constant switching frequency and balanced inductor currents despite the lack of a fixed-frequency clock generator. The constant switching frequency allows the inductor ripple-current operating point to remain relatively constant, resulting in easy design methodology and predictable output voltage ripple. On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics table are influenced by switching delays in the external high-side MOSFET. Resistive losses, including the inductor, both MOSFETs, output capacitor ESR, and PCB copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only during forcedPWM operation and dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH rising 24 dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency (per phase) is: fSW = ( VOUT + VDIS ) t ON ( VIN + VDIS - VCHG ) where VDIS is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; VCHG is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PCB resistances; and tON is the on-time as defined in the Electrical Characteristics table. Current Sense The output current of each phase is sensed. Low offset amplifiers are used for current balance, voltagepositioning gain, and current limit. Sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the DC resistance of the output inductor. Using the DC resistance (RDCR) of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor’s DCR must be accounted for in the output-voltage drooperror budget and power monitor. This current-sense method uses an RC filtering network to extract the current information from the output inductor (see Figure 3). The resistive divider used should provide a current-sense resistance (RCS) low enough to meet the current-limit requirements, and the time constant of the RC network should match the inductor’s time constant (L/RCS): ⎛ R2 ⎞ R CS = ⎜ R ⎝ R1 + R2 ⎟⎠ DCR and: R CS = L ⎡1 1 ⎤ + ⎢ C EQ ⎣ R1 R2 ⎥⎦ where RCS is the required current-sense resistance, and RDCR is the inductor’s series DC resistance. Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. To minimize the current-sense error due to the current-sense inputs’ bias current (ICSP_ and ICSN_), choose R1 || R2 to be less than 2kΩ and use the above equation to ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies that results in unwanted offsets in the regulation voltage and results in early current-limit detection. Similar to the inductor DCR sensing method, the RC filter’s time constant should match the L/R time constant formed by the current-sense resistor’s parasitic inductance: L ESL = C EQR1 R SENSE When using a current-sense resistor for accurate outputvoltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (LESL) of the current-sense resistor (see Figure 3). The ESL-induced voltage step does not affect the average current-sense voltage, but results in a significant peak current-sense voltage error where LESL is the equivalent series inductance of the current-sense resistor, RSENSE is current-sense resistance value, C EQ and R1 are the time-constant matching components. INPUT (VIN) DH_ NH CIN SENSE RESISTOR L LESL RSENSE R1 CEQ L CEQR1 = ESL RSENSE LX_ MAX17410 DL_ NL DL COUT PGND CSP_ CSN_ A) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) DH_ NH CIN INDUCTOR L RDCR RCS = LX_ MAX17410 DL_ NL PGND DL R1 R2 CEQ R2 RDCR R1 + R2 COUT L RCS = C × EQ [ R11 + R21 ] CSP_ CSN_ B) LOSSLESS INDUCTOR SENSING FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR. Figure 3. Current-Sense Methods ______________________________________________________________________________________ 25 MAX17410 determine the sense capacitance (C EQ ). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. See the Voltage Positioning and Loop Compensation section for detailed information. MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Current Balance The MAX17410 integrates the difference between the current-sense voltages and adjusts the on-time of the secondary phase to maintain current balance. The current balance now relies on the accuracy of the currentsense resistors instead of the inaccurate, thermally sensitive on-resistance of the low-side MOSFETs. With active current balancing, the current mismatch is determined by the current-sense resistor values and the offset voltage of the transconductance amplifiers: IOS(IBAL) = ILMAIN - ILSEC = VOS(IBAL) R CS where R CS is the effective sense resistance and VOS(IBAL) is the current-balance offset specification in the Electrical Characteristics table. The worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches resulting in different di/dt for the two phases. The time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency. Current Limit The current-limit circuit employs a unique “valley” current-sensing algorithm that uses current-sense resistors between the current-sense inputs (CSP_ to CSN_) as the current-sensing elements. If the current-sense signal of the selected phase is above the current-limit threshold, the PWM controller does not initiate a new cycle until the inductor current of the selected phase drops below the valley current-limit threshold. When either phase trips the current limit, both phases are effectively current limited since the interleaved controller does not initiate a cycle with either phase. Since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the currentsense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. The positive valley current-limit threshold voltage at CSP to CSN equals precisely 1/10th the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV current-sense range). Connect ILIM directly to VCC to set the default current-limit threshold setting of 22.5mV (typ). 26 The negative current-limit threshold (forced-PWM mode only) is nominally -125% of the corresponding valley current-limit threshold. When the inductor current drops below the negative current limit, the controller immediately activates an on-time pulse—DL turns off, and DH turns on—allowing the inductor current to remain above the negative current threshold. Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (CSP_, CSN_). Feedback Adjustment Amplifiers Voltage-Positioning Amplifier (Steady-State Droop) The MAX17410 include a transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier’s input is generated by summing the current-sense inputs, which differentially sense the voltage across either current-sense resistors or the inductor’s DCR. The amplifier’s output connects directly to the regulator’s voltage-positioned feedback input (FB), so the resistance between FB and the output-voltage sense point determines the voltage-positioning gain: VOUT = VTARGET - R FBIFB where the target voltage (VTARGET) is defined in the Nominal Output Voltage Selection section, and the FB amplifier’s output current (IFB) is determined by the average value of the current-sense voltages: IFB = G m(FB) × VCSPAVG-CSN where V CS = V CSPAVG-CSN is the average currentsense voltage between the CSPAVG and the CSN_ pins, and Gm(FB) is typically 1.2mS as defined in the Electrical Characteristics table. Differential Remote Sense The MAX17410 includes differential, remote-sense inputs to eliminate the effects of voltage drops along the PCB traces and through the processor’s power pins. The feedback-sense node connects to the voltage-positioning resistor (RFB). The ground-sense (GNDS) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the voltage-positioning resistor (R FB ), and ground-sense (GNDS) input directly to the processor’s remote-sense outputs as shown in Figure 1. ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Transient Overlap Operation When a transient occurs, the response time of the controller depends on how quickly it can slew the inductor current. Multiphase controllers that remain 180° out-ofphase when a transient occurs actually respond slower than an equivalent single-phase controller. To provide fast transient response, the MAX17410 supports a phase overlap mode that allows the dual regulators to operate in-phase when heavy load transients are detected, effectively reducing the response time. After either high-side MOSFET turns off, if the output voltage does not exceed the regulation voltage when the minimum off-time expires, the controller simultaneously turns on both high-side MOSFETs during the next ontime cycle. This maximizes the total inductor current slew rate. The phases remain overlapped until the output voltage exceeds the regulation voltage after the minimum off-time expires. After the phase overlap mode ends, the controller automatically begins with the opposite phase. For example, if the secondary phase provided the last on-time pulse before overlap operation began, the controller starts switching with the main phase when overlap operation ends. Nominal Output Voltage Selection The nominal no-load output voltage (V TARGET ) is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (VGNDS) as defined in the following equation: VTARGET = VFB = VDAC + VGNDS where VDAC is the selected VID voltage. On startup, the MAX17410 slews the target voltage from ground to the preset boot voltage. DAC Inputs (D0–D6) The digital-to-analog converter (DAC) programs the output voltage using the D0–D6 inputs. D0–D6 are low-voltage (1.0V) logic inputs, designed to interface directly with the CPU. Do not leave D0–D6 unconnected. Changing D0–D6 initiates a transition to a new output voltage level. Change D0–D6 together, avoiding greater than 20ns skew between bits. Otherwise, incorrect DAC readings may cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with the IMVP6/IMVP6+ (Table 4) specifications. Suspend Mode When the processor enters low-power deeper sleep mode, the IMVP6 CPU sets the VID DAC code to a lower output voltage and drives DPRSLPVR high. The MAX17410 responds by slewing the internal target voltage to the new DAC code, switching to single-phase operation, and letting the output voltage gradually drift down to the deeper sleep voltage. During the transition, the MAX17410 blanks both the upper and lower PWRGD and CLKEN thresholds until 20μs after the internal target reaches the deeper sleep voltage. Once the 20μs timer expires, the MAX17410 re-enables the lower PWRGD and CLKEN threshold, but keeps the upper threshold blanked. PHASEGD remains blanked high impedance while DPRSLPVR is high. Table 3. Operating Mode Truth Table INPUTS SHDN DPRSTP DPRSLPVR PSI PHASE OPERATION* GND X X X DISABLED Low-Power Shutdown Mode. DL1 and DL2 forced low, and the controller is disabled. The supply current drops to 1μA (max). X Multiphase Skipping 1/8 RTIME Slew Rate Startup/Boot. When SHDN is pulled high, the MAX17410 begins the startup sequence and ramps the output voltage up to the boot voltage. See Figure 9. Rising X X OPERATING MODE ______________________________________________________________________________________ 27 MAX17410 Integrator Amplifier An integrator amplifier forces the DC average of the FB voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 2), allowing accurate DC output-voltage regulation regardless of the output ripple voltage. The integrator amplifier has the ability to shift the output voltage by ±100mV (typ). The differential input voltage range is at least ±60mV total, including DC offset and AC ripple. The MAX17410 disables the integrator by connecting the amplifier inputs together at the beginning of all VID transitions done in pulse-skipping mode (DPRSLPVR = high). The integrator remains disabled until 20μs after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Table 3. Operating Mode Truth Table (continued) INPUTS SHDN DPRSTP High X High Low X High Low Low High High High Falling High X X X OPERATING MODE High Multiphase Forced-PWM Nominal RTIME Slew Rate Full Power. The no-load output voltage is determined by the selected VID DAC code (D0–D6, Table 4). Low 1-Phase Forced-PWM Nominal RTIME Slew Rate Intermediate Power. The no-load output voltage is determined by the selected VID DAC code (D0–D6, Table 4). When PSI is pulled low, the MAX17410 immediately disables phase 2—DH2, and DL2 pulled low. 1-Phase PulseSkipping Nominal RTIME Slew Rate Deeper Sleep Mode. The no-load output voltage is determined by the selected VID DAC code (D0–D6, Table 4). When DPRSLPVR is pulled high, the MAX17410 immediately enters 1-phase pulse-skipping operation allowing automatic PWM/PFM switchover under light loads. The PWRGD and CLKEN upper thresholds are blanked. DH2 and DL2 are pulled low. X 1-Phase PulseSkipping 1/4th RTIME Slew Rate Deeper Sleep Slow Exit Mode. The no-load output voltage is determined by the selected VID DAC code (D0–D6, Table 4). When DPRSTP is pulled high while DPRSLPVR is already high, the MAX17410 remains in 1-phase pulse-skipping operation allowing automatic PWM/PFM switchover under light loads. The PWRGD and CLKEN upper thresholds are blanked. DH2 and DL2 are pulled low. X Multiphase Forced-PWM 1/8th RTIME Slew Rate Shutdown. When SHDN is pulled low, the MAX17410 immediately pulls PWRGD and PHASEGD low, CLKEN becomes high impedance, all enabled phases are activated, and the output voltage is ramped down to ground. Once the output reaches 0V, the controller enters the low-power shutdown state. See Figure 9. X High X PHASE OPERATION* PSI DPRSLPVR X DISABLED Fault Mode. The fault latch has been set by the MAX17410 UVP or thermal-shutdown protection, or by the OVP protection. The controller will remain in FAULT mode until VCC power is cycled or SHDN toggled. *Multiphase Operation = All enabled phases active. X = Don’t care. Table 4. IMVP6+ Output Voltage VID DAC Codes D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) 0 0 0 0 0 0 0 1.5000 0 0 0 0 1 1 0 1.4250 0 0 0 0 0 0 1 1.4875 0 0 0 0 1 1 1 1.4125 0 0 1 0 0 0 1.4000 0 0 0 0 0 1 0 1.4750 0 0 0 0 0 0 1 1 1.4625 0 0 0 1 0 0 1 1.3875 0 0 0 0 1 0 0 1.4500 0 0 0 1 0 1 0 1.3750 0 0 0 0 1 0 1 1.4375 0 0 0 1 0 1 1 1.3625 28 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) 0 0 0 1 1 0 0 1.3500 0 1 1 0 0 1 1 0.8625 0 0 0 1 1 0 1 1.3375 0 1 1 0 1 0 0 0.8500 0 0 0 1 1 1 0 1.3250 0 1 1 0 1 0 1 0.8375 0 0 0 1 1 1 1 1.3125 0 1 1 0 1 1 0 0.8250 0 0 1 0 0 0 0 1.3000 0 1 1 0 1 1 1 0.8125 0 0 1 0 0 0 1 1.2875 0 1 1 1 0 0 0 0.8000 0 0 1 0 0 1 0 1.2750 0 1 1 1 0 0 1 0.7875 0 0 1 0 0 1 1 1.2625 0 1 1 1 0 1 0 0.7750 0 0 1 0 1 0 0 1.2500 0 1 1 1 0 1 1 0.7625 0 0 1 0 1 0 1 1.2375 0 1 1 1 1 0 0 0.7500 0 0 1 0 1 1 0 1.2250 0 1 1 1 1 0 1 0.7375 0 0 1 0 1 1 1 1.2125 0 1 1 1 1 1 0 0.7250 0 0 1 1 0 0 0 1.2000 0 1 1 1 1 1 1 0.7125 0 0 1 1 0 0 1 1.1875 1 0 0 0 0 0 0 0.7000 0 0 1 1 0 1 0 1.1750 1 0 0 0 0 0 1 0.6875 0 0 1 1 0 1 1 1.1625 1 0 0 0 0 1 0 0.6750 0 0 1 1 1 0 0 1.1500 1 0 0 0 0 1 1 0.6625 0 0 1 1 1 0 1 1.1375 1 0 0 0 1 0 0 0.6500 0 0 1 1 1 1 0 1.1250 1 0 0 0 1 0 1 0.6375 0 0 1 1 1 1 1 1.1125 1 0 0 0 1 1 0 0.6250 0 1 0 0 0 0 0 1.1000 1 0 0 0 1 1 1 0.6125 0 1 0 0 0 0 1 1.0875 1 0 0 1 0 0 0 0.6000 0 1 0 0 0 1 0 1.0750 1 0 0 1 0 0 1 0.5875 0 0 1 0 1 0 0.5750 0 1 0 0 0 1 1 1.0625 1 0 1 0 0 1 0 0 1.0500 1 0 0 1 0 1 1 0.5625 0 1 0 0 1 0 1 1.0375 1 0 0 1 1 0 0 0.5500 0 1 0 0 1 1 0 1.0250 1 0 0 1 1 0 1 0.5375 0 1 0 0 1 1 1 1.0125 1 0 0 1 1 1 0 0.5250 0 1 0 1 0 0 0 1.0000 1 0 0 1 1 1 1 0.5125 0 1 0 1 0 0 1 0.9875 1 0 1 0 0 0 0 0.5000 0 1 0 1 0 1 0 0.9750 1 0 1 0 0 0 1 0.4875 0 1 0 1 0 1 1 0.9625 1 0 1 0 0 1 0 0.4750 0 1 0 1 1 0 0 0.9500 1 0 1 0 0 1 1 0.4625 0 1 0 1 1 0 1 0.9375 1 0 1 0 1 0 0 0.4500 0 1 0 1 1 1 0 0.9250 1 0 1 0 1 0 1 0.4375 0 1 0 1 1 1 1 0.9125 1 0 1 0 1 1 0 0.4250 0 1 1 0 0 0 0 0.9000 1 0 1 0 1 1 1 0.4125 0 1 1 0 0 0 1 0.8875 1 0 1 1 0 0 0 0.4000 0 1 1 0 0 1 0 0.8750 1 0 1 1 0 0 1 0.3875 ______________________________________________________________________________________ 29 MAX17410 Table 4. IMVP6+ Output Voltage VID DAC Codes (continued) MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Table 4. IMVP6+ Output Voltage VID DAC Codes (continued) D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) 1 0 1 1 0 1 0 0.3750 1 1 0 1 1 0 1 0.1375 1 0 1 1 0 1 1 0.3625 1 1 0 1 1 1 0 0.1250 1 0 1 1 1 0 0 0.3500 1 1 0 1 1 1 1 0.1125 1 0 1 1 1 0 1 0.3375 1 1 1 0 0 0 0 0.1000 1 0 1 1 1 1 0 0.3250 1 1 1 0 0 0 1 0.0875 1 0 1 1 1 1 1 0.3125 1 1 1 0 0 1 0 0.0750 1 1 0 0 0 0 0 0.3000 1 1 1 0 0 1 1 0.0625 1 1 0 0 0 0 1 0.2875 1 1 1 0 1 0 0 0.0500 1 1 0 0 0 1 0 0.2750 1 1 1 0 1 0 1 0.0375 1 1 0 0 0 1 1 0.2625 1 1 1 0 1 1 0 0.0250 1 1 0 0 1 0 0 0.2500 1 1 1 0 1 1 1 0.0125 1 1 0 0 1 0 1 0.2375 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0.2250 1 1 1 1 0 0 1 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 0.2125 1 1 1 0 1 0 0 0 0.2000 1 1 1 1 0 1 1 0 1 1 0 1 0 0 1 0.1875 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0 0.1750 1 1 1 0 1 0 1 1 0.1625 1 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0.1500 1 1 1 1 1 1 1 0 Output-Voltage Transition Timing The MAX17410 performs mode transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. At the beginning of an output voltage transition, the MAX17410 blanks both PWRGD thresholds, preventing the PWRGD open-drain output from changing states during the transition. The controller enables the lower PWRGD threshold approximately 20μs after the slewrate controller reaches the target output voltage, but the upper PWRGD threshold is enabled only if the controller remains in forced-PWM operation. If the controller enters pulse-skipping operation, the upper PWRGD threshold remains blanked. The slew rate (set by resistor RTIME) must be set fast enough to ensure that the transition may be completed within the maximum allotted time. The MAX17410 automatically controls the current to the minimum level required to complete the transition in the calculated time. The slew-rate controller uses an internal 30 capacitor and current-source programmed by RTIME to transition the output voltage. The total transition time depends on R TIME , the voltage difference, and the accuracy of the slew-rate controller (CSLEW accuracy). The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit. For all dynamic VID transitions, the transition time (tTRAN) is given by: t TRAN = VNEW - VOLD (dVTARGET / dt ) where dVTARGET/dt = 12.5mV/μs × 71.5kΩ/RTIME is the slew rate, VOLD is the original output voltage, and VNEW is the new target voltage. See the time slew-rate accuracy in the Electrical Characteristics table for slew-rate limits. For soft-start and shutdown, the controller automatically reduces the slew rate to 1/8th. The output voltage tracks the slewed target voltage, making the transitions relatively smooth. The average inductor current per phase required to make an output voltage transition is: ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies C OUT × (dVTARGET / dt ) η TOTAL where dVTARGET/dt is the required slew rate, COUT is the total output capacitance, and ηTOTAL is the number of active phases. Deeper Sleep Transitions When DPRSLPVR goes high, the MAX17410 immediately disables phase 2 (DH2 and DL2 forced low), blanks PHASEGD high impedance, and enters pulse-skipping operation (see Figures 4 and 5). If the VIDs are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. The internal target still ramps as before, and PWRGD remains blanked high impedance until 20μs after the output voltage reaches the internal target. Once this time expires, PWRGD monitors only the lower threshold. Fast C4E Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while the output voltage still exceeds the deeper sleep voltage, the MAX17410 quickly slews (50mV/μs min regardless of RTIME setting) the internal target voltage to the DAC code provided by the processor as long as the output voltage is above the new target. The controller remains in skip mode until the output voltage equals the internal target. Once the internal target reaches the output voltage, phase 2 is enabled. The controller blanks PWRGD, PHASEGD, and CLKEN (forced high impedance) until 20μs after the transition is completed. See Figure 4. ACTUAL VOUT CPU CORE VOLTAGE INTERNAL TARGET VID (D0-D6) DEEPER SLEEP VID DPRSLPVR DPRSTP DO NOT CARE (DPRSLPVR DOMINATES STATE) PSI INTERNAL PWM CONTROL 1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW) FORCED PWM NO PULSES: VOUT > VTARGET DH1 DH2 PWRGD BLANK HIGH-Z BLANK HIGH THRESHOLD ONLY BLANK HI-Z CLKEN BLANK LOW BLANK HIGH THRESHOLD ONLY BLANK LOW PHASEGD BLANK HI-Z (1-PHASE OPERATION) OVP SET TO 1.75V MIN tBLANK 20μs TYP TRACKS INTERNAL TARGET tBLANK 20μs TYP Figure 4. C4E (C4 Early Exit) Transition ______________________________________________________________________________________ 31 MAX17410 IL ≅ MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Standard C4 Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while the output voltage is regulating to the deeper sleep voltage, the MAX17410 immediately activates all enabled phases and ramps the output voltage to the LFM DAC code provided by the processor at the slew rate set by RTIME. The controller blanks PWRGD, PHASEGD, and CLKEN (forced high impedance) until 20μs after the transition is completed. See Figure 5. ACTIVE VID CPU CORE VOLTAGE ACTUAL VOUT LFM VID INTERNAL TARGET DPRSLP VID VID (D0—D6) DEEPER SLEEP VID LFM VID DPRSLPVR DPRSTP DO NOT CARE (DPRSLPVR DOMINATES STATE) PSI INTERNAL PWM CONTROL 1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW) 1-PHASE FORCED PWM NO PULSES: VOUT > VTARGET DH1 DH2 PWRGD BLANK HIGH-Z BLANK HIGH THRESHOLD ONLY BLANK HIGH-Z CLKEN BLANK LOW BLANK HIGH THRESHOLD ONLY BLANK LOW BLANK HIGH-Z (1-PHASE OPERATION) PHASEGD OVP SET TO 1.75V MIN tBLANK 20μs TYP TRACKS INTERNAL TARGET tBLANK 20μs TYP Figure 5. Standard C4 Transition 32 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies the processor at 1/4 the slew rate set by RTIME. The controller blanks PWRGD, PHASEGD, and CLKEN (forced high impedance) until 20μs after the transition is completed. See Figure 6. SLOW SLEW RATE ACTIVE VID ACTUAL VOUT CPU CORE VOLTAGE LFM VID INTERNAL TARGET DPRSLP VID DEEPER SLEEP VID VID (D0–D6) LFM VID SLOW SLEW RATE DPRSLPVR DPRSTP DO NOT CARE (DPRSLPVR DOMINATES STATE) PSI INTERNAL PWM CONTROL 1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW) 1-PHASE FORCED PWM NO PULSES: VOUT > VTARGET DH1 DH2 PWRGD BLANK HIGH-Z BLANK HIGH THRESHOLD ONLY BLANK HIGH-Z CLKEN BLANK LOW BLANK HIGH THRESHOLD ONLY BLANK LOW BLANK HIGH-Z (1-PHASE OPERATION) PHASEGD SET TO 1.75V MIN OVP tBLANK 20μs TYP TRACKS INTERNAL TARGET tBLANK 20μs TYP Figure 6. Slow C4 Transition ______________________________________________________________________________________ 33 MAX17410 Slow C4 Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR high, DPRSTP pulled high) while the output voltage is regulating to the deeper sleep voltage, the MAX17410 remains in 1-phase skip mode and ramps the output voltage to the LFM DAC code provided by MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies PSI Transitions When PSI is pulled low, the MAX17410 immediately disables phase 2 (DH2 and DL2 forced low), blanks PHASEGD high impedance, and enters single-phase PWM operation (see Figure 7). When PSI is pulled high, the MAX17410 enables phase 2. PHASEGD is blanked high impedance for 32 switching cycles on DH2, allowing sufficient time/cycles for phase 1 and 2 to achieve current balance. In a typical IMVP-6 application, the VID is reduced by 1 LSB (12.5mV) when PSI is pulled low, and increased by 1 LSB when PSI is pulled high. Forced-PWM Operation (Normal Mode) During soft-start, soft-shutdown, and normal operation— when the CPU is actively running (DPRSLPVR = low, Table 5)—the MAX17410 operates with the low-noise, forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparators of all active phases, forcing the low-side gate-drive waveforms to constantly be the complement of the high-side gatedrive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output voltage transitions by quickly discharging the output capacitors. Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 10mA to 50mA per phase, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light load conditions, the processor may switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. PSI determines how many phases are active when operating in forced-PWM mode (DPRSLPVR = low). When PSI is pulled low, the main phase remains active but the secondary phase is disabled (DH2 and DL2 forced low). CPU FREQ CPU LOAD VID (D0–D6) CPU CORE VOLTAGE PSI INTERNAL PWM CONTROL 2-PHASE PWM 1-PHASE PWM 2-PHASE PWM PWRGD BLANK HIGH-Z BLANK HIGH-Z CLKEN BLANK LOW BLANK LOW BLANK HIGH-Z PHASEGD tBLANK 20μs TYP tBLANK 20μs TYP 32 DH2 SWITCHING CYCLES Figure 7. PSI Transition 34 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Automatic Pulse-Skipping Switchover In skip mode (DPRSLPVR = high), an inherent automatic switchover to PFM takes place at light loads (Figure 8). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing comparator senses the inductor current across the low-side MOSFETs. Once VLX drops below the zero-crossing comparator threshold (see the Electrical Characteristics table), the comparator forces DL low (Figure 2). This mechanism causes the threshold between pulse-skipping PFM and non-skipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current of each phase is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 8). For a battery ⎞ ⎛t V ⎞⎛V -V ILOAD(SKIP) = η TOTAL ⎜ SW OUT ⎟ ⎜ IN OUT ⎟ ⎝ ⎠⎝ L VIN ⎠ where ηTOTAL is the number of active phases. The switching waveforms may appear noisy and asynchronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs between PFM noise and light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels. Δi VIN - VOUT = Δt L INDUCTOR CURRENT When DPRSLPVR is pulled high, the MAX17410 operates with a single-phase pulse-skipping mode. The pulse-skipping mode enables the driver’s zero-crossing comparator, so the controller pulls DL1 low when its current-sense inputs detect “zero” inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light load conditions to avoid overcharging the output. When pulse-skipping, the controller blanks the upper PWRGD and CLKEN thresholds, and also blanks PHASEGD high impedance. Upon entering pulseskipping operation, the controller temporarily sets the OVP threshold to 1.80V, preventing false OVP faults when the transition to pulse-skipping operation coincides with a VID code change. Once the error amplifier detects that the output voltage is in regulation, the OVP threshold tracks the selected VID DAC code. The MAX17410 automatically uses forced-PWM operation during soft-start and soft-shutdown, regardless of the DPRSLPVR and PSI configuration. input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. The total load current at the PFM/PWM crossover threshold (ILOAD(SKIP)) is approximately: IPEAK ILOAD = IPEAK/2 0 ON-TIME TIME Figure 8. Pulse-Skipping/Discontinuous Crossover Point ______________________________________________________________________________________ 35 MAX17410 Light-Load Pulse-Skipping Operation (Deeper Sleep) MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Power-Up Sequence (POR, UVLO) The MAX17410 is enabled when SHDN is driven high (Figure 9). The reference powers up first. Once the reference exceeds its undervoltage lockout threshold, the internal analog blocks are turned on and masked by a 150μs one-shot delay. The PWM controller then begins switching. Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC undervoltage lockout (UVLO) circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller, V CC above 4.25V and SHDN driven high. With the reference in regulation, the controller ramps the output voltage to the boot voltage (1.2V) at 1/8th the slew rate set by RTIME: t TRAN(START) = 8VBOOT (dVTARGET / dt ) where dVTARGET/dt = 12.5mV/μs x 71.5kΩ/RTIME is the slew rate. The soft-start circuitry does not use a variable current limit, so full output current is available immediately. CLKEN is pulled low approximately 60μs after the MAX17410 reaches the boot voltage. At the same time, the MAX17410 slews the output to the voltage set at the VID inputs at the programmed slew rate. PWRGD and PHASEGD becomes high impedance approximately 5ms after CLKEN is pulled low. The MAX17410 automatically uses forced-PWM operation during soft-start and soft-shutdown, regardless of the DPRSLPVR and PSI configuration. For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 0.5V. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately and forces a high-impedance output. VCC SHDN VID (D0–D6) INVALID CODE INVALID CODE SOFT-START = 1/8 SLEW RATE SET BY RTIME SOFT-SHUTDOWN = 1/8 SLEW RATE SET BY RTIME VCORE INTERNAL PWM CONTROL SKIP FORCED-PWM FORCED-PWM PHASEGD CLKEN PWRGD tBLANK 60μs TYP tBLANK 5ms TYP tBLANK 20μs TYP tBLANK 20μs TYP Figure 9. Power-Up and Shutdown Sequence Timing Diagram 36 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Phase Fault (PHASEGD) The MAX17410 includes a phase fault output that signals the system that one of the two phases either has a fault condition or is not matched with the other. Detection is done by identifying the need for a large ontime difference between phases to achieve or move towards current balance. PHASEGD is forced low when VCCI is below (0.6 x VFB) or above (1.4 x VFB). PHASEGD is high impedance when the controller operates in one-phase mode (DPRSLPVR high, or PSI low and DPRSLPVR low). On exit to two-phase mode, PHASEGD is forced high impedance for 32 switching cycles on DH2. where dVTARGET/dt = 12.5mV/μs x 71.5kΩ/RTIME is the slew rate. Slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion. After the controller reaches the zero target, the MAX17410 shuts down completely—the drivers are disabled (DL1 and DL2 driven high), the reference turns off, and the supply current drops below 1μA. When a fault condition—output UVLO or thermal shutdown—activates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 0.5V. Power Monitor (PMON) The MAX17410 include a single-quadrant multiplier used to determine the actual output power based on the inductor current (the differential CS input) and output voltage (CSN to GNDS). The buffered output of this multiplier is connected to PWR and provides a voltage relative to the output power dissipation: V(PMON) = Kpwr x V(OUTS, GNDS) x V(CSPAVG, CSN) / V(TIME, ILIM) where VCSP - VCSN = ILOAD x RSENSE, and the power monitor scale factor (Kpwr) is typically 21.25. If ILIM is externally connected to a 5V rail to enable the internal default/preset current-limit threshold, then the V(TIME, ILIM) value to be used in the above equation is 225mV. Do not use the power monitor in any configuration that would cause its output V(PMON) to exceed (VCC - 0.5V). PMON is pulled to ground when the MAX17410 is in shutdown. The power monitor allows the system to accurately monitor the CPU’s power dissipation and quickly predict if the system is about to overheat before the significantly slower temperature sensor signals an overtemperature alert. PHASEGD is low in shutdown. PHASEGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions). Temperature Comparator (VRHOT) VRHOT is an open-drain output of the internal comparator. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. VRHOT is high impedance in shutdown. Fault Protection (Latched) Output Overvoltage Protection The overvoltage protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17410 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the set VID DAC voltage by more than 300mV, regardless of the operating state. During pulse-skipping operation (DPRSLPVR = high), the OVP threshold tracks the VID DAC voltage. When the OVP circuit detects an overvoltage fault while in multiphase mode (DPRSLPVR = low, PSI = high), the MAX17410 immediately forces DL1 and DL2 high, pulls DH1 and DH2 low. This action turns on the synchronous-rectifier MOSFETs with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse will blow. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. When an overvoltage fault occurs while in one-phase operation (DPRSLPVR = high, or PSI = low), the MAX17410 immediately forces DL1 high, pulls DH1 low. DL2 and DH2 remain low as phase two was disabled. DL2 is forced high only when the output falls below the UV threshold. Overvoltage protection can be disabled through the nofault test mode (see the No-Fault Test Mode section). ______________________________________________________________________________________ 37 MAX17410 Shutdown When SHDN goes low, the MAX17410 enters low-power shutdown mode. PWRGD is pulled low immediately, and the output voltage ramps down at 1/8th the slew rate set by RTIME: 8VOUT t TRAN(SHDN) = (dVTARGET / dt ) MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Output Undervoltage Protection The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX17410 output voltage is 400mV below the target voltage, the controller activates the shutdown sequence and sets the fault latch. Once the controller ramps down to zero, it forces DL1 and DL2 high, and pulls DH1 and DH2 low. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. UVP can be disabled through the no-fault test mode (see the No-Fault Test Mode section). Thermal-Fault Protection The MAX17410 features a thermal fault-protection circuit. When the junction temperature rises above +160°C, a thermal sensor sets the fault latch and activates the softshutdown sequence. Once the controller ramps down to zero, it forces DL1 and DL2 high, and pulls DH1 and DH2 low. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15°C. Thermal shutdown can be disabled through the no-fault test mode (see the No-Fault Test Mode section). No-Fault Test Mode The latched fault-protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a “no-fault” test mode is provided to disable the fault protection—overvoltage protection, undervoltage protection, and thermal shutdown. Additionally, the test mode clears the fault latch if it has been set. The no-fault test mode is entered by forcing 11V to 13V on SHDN. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large VIN - VOUT differential exists. The high-side gate drivers (DH) source and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH_ floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST_, while the DL_ synchronous-rectifier drivers are powered directly by the 5V bias supply (VDD). Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. 38 There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17410 interprets the MOSFET gates as “off” while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL low is robust, with a 0.25Ω (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces may require rising LX edges do not pull up the low-side MOSFETs’ gate, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold: ⎛C ⎞ VGS(TH) > VIN ⎜ RSS ⎟ ⎝ C ISS ⎠ Typically, adding a 4700pF between DL and power ground (C NL in Figure 10), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. BST_ DH_ (RBST)* INPUT (VIN) CBST NH L LX_ VDD CBYP DL_ NL (CNL)* PGND (RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS. Figure 10. Gate-Drive Circuit ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Multiphase Quick-PWM Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input Voltage Range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. • Maximum Load Current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%. For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase: I ILOAD(PHASE) = LOAD η TOTAL where ηTOTAL is the total number of active phases. • Switching Frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. • Inductor Operating Point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. Inductor Selection The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: ⎛ ⎞ ⎛ VOUT ⎞ VIN - VOUT L = η TOTAL ⎜ ⎟⎜ ⎟ ⎝ fSWILOAD(MAX)LIR ⎠ ⎝ VIN ⎠ where ηTOTAL is the total number of phases. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): ⎛ ILOAD(MAX) ⎞ ⎛ LIR ⎞ IPEAK = ⎜ ⎟ ⎜ 1 + 2 ⎟⎠ ⎝ η TOTAL ⎠ ⎝ Transient Response The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. For a dual-phase controller, the worst-case output sag voltage may be determined by: ______________________________________________________________________________________ 39 MAX17410 Alternatively, shoot-through currents may be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5Ω in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (R BST in Figure 10). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise. MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies ⎤ L ΔILOAD(MAX) ⎢⎜ MIN) ⎥ ⎟⎠ + t OFF(M V ⎝ IN ⎣ ⎦ VSAG = ⎡⎛ ( VIN - 2VOUT ) t SW ⎞ ⎤ - 2t OFF(MIN) ⎥ 2C OUT VOUT ⎢⎜ ⎟ VIN ⎠ ⎢⎣⎝ ⎥⎦ ΔILOAD(MAX) ⎡⎛ VOUT t SW ⎞ ⎤ + t OFF(MIN) ⎥ + ⎢⎜ ⎟ 2C OUT V ⎠ ⎢⎣⎝ ⎥⎦ IN ( ) 2 ⎡⎛ VOUT t SW ⎞ where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics table). The amount of overshoot due to stored inductor energy can be calculated as: VSOAR ≈ ( ΔILOAD(MAX) ) 2 L 2η TOTAL C OUT VOUT where ηTOTAL is the total number of active phases. Setting the Current Limit The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: ⎛ ILOAD(MAX) ⎞ ⎛ LIR ⎞ ILIMIT(LOW) > ⎜ ⎟ ⎜ 1 - 2 ⎟⎠ ⎝ η TOTAL ⎠ ⎝ where ηTOTAL is the total number of active phases, and ILIMIT(LOW) equals the minimum current-limit threshold voltage divided by the current-sense resistor (RSENSE). For the 22.5mV default setting, the minimum currentlimit threshold is 19.5mV. Output Capacitor Selection The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. In CPU VCORE converters and other applications where the output is subject to large load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: (RESR + RPCB ) ≤ ΔI VSTEP LOAD(MAX) 40 In non-CPU applications, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output-ripple voltage. The output-ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. When operating multiphase systems out-of-phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. For multiphase operation, the maximum ESR to meet ripple requirements is: ⎤ ⎡ VINfSWL R ESR ≤ ⎢ ⎥ VRIPPLE η V V V ⎢⎣ ( IN TOTAL OUT ) OUT ⎥⎦ where ηTOTAL is the total number of active phases and fSW is the switching frequency per phase. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types). When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR ≤ SW π where: fESR = 1 2πR EFF C OUT and: R EFF = R ESR + R DROOP + R PCB where COUT is the total output capacitance, RESR is the total equivalent-series-resistance, RDROOP is the voltagepositioning gain, and RPCB is the parasitic board resistance between the output capacitors and sense resistors. ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The multiphase Quick-PWM controllers operate out-ofphase, while the Quick-PWM slave controllers provide selectable out-of-phase or in-phase on-time triggering. Out-of-phase operation reduces the RMS input current by dividing the input current between several staggered stages. For duty cycles less than 100%/ηTOTAL per phase, the IRMS requirements may be determined by the following equation: ⎛ ILOAD ⎞ IRMS = ⎜ ⎟ η TOTAL VOUT ( VIN - η TOTAL VOUT ) ⎝ η TOTAL VIN ⎠ where η TOTAL is the total number of out-of-phase switching regulators. The worst-case RMS current requirement occurs when operating with V IN = 2ηTOTALVOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD/ηTOTAL. For most applications, non-tantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal circuit longevity. Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (R DS(ON)), comes in a moderatesized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur (see the MOSFET Gate Driver section). ______________________________________________________________________________________ 41 MAX17410 For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP capacitors in wide-spread use at the time of publication have typical ESR zero frequencies below 50kHz. In the standard application circuit, the ESR needed to support a 30mVP-P ripple is 30mV/(40A x 0.3) = 2.5mΩ. Four 330μF/2.5V Panasonic SP (type SX) capacitors in parallel provide 1.5mΩ (max) ESR. With a 2mΩ droop and 0.5mΩ PCB resistance, the typical combined ESR results in a zero at 30kHz. Ceramic capacitors have a high ESR zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. Do not put high-value ceramic capacitors directly across the output without verifying that the circuit contains enough voltage positioning and series PCB resistance to ensure stability. When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Doublepulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: 2 ⎞ ⎛V ⎞⎛ I PD (N H Resistive) = ⎜ OUT ⎟ ⎜ LOAD ⎟ R DS(ON) ⎝ VIN ⎠ ⎝ η TOTAL ⎠ where ηTOTAL is the total number of phases. Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in the high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: ⎛ VIN(MAX)ILOADfSW ⎞ ⎛ Q G(SW) ⎞ PD (N H Switching) = ⎜ ⎟⎜ I ⎟ η TOTAL ⎝ ⎠ ⎝ GATE ⎠ + C OSS VIN 2 fSW 2 where COSS is the NH MOSFET’s output capacitance, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.2A, typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x VIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: ⎡ ⎛ V ⎞ ⎤ ⎛ ILOAD ⎞ 2 OUT PD (N L Resistive) = ⎢1− ⎜ ⎟ ⎥⎜ ⎟ R DS(ON) ⎢⎣ ⎝ VIN(MAX) ⎠ ⎥⎦ ⎝ η TOTAL ⎠ 42 The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can “over design” the circuit to tolerate: ΔI ⎛ ⎞ ILOAD = η TOTAL ⎜ I VALLEY(MAX) + INDUCTOR ⎟ ⎝ ⎠ 2 ⎛ ILOAD(MAX)LIR ⎞ = η TOTALI VALLEY(MAX) + ⎜ ⎟ 2 ⎝ ⎠ where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. Select a diode that can handle the load current per phase during the dead times. This diode is optional and can be removed if efficiency is not critical. Boost Capacitors The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1μF ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1μF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs’ gates: C BST = N × Q GATE 200mV where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET’s data sheet. For example, assume (2) IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: C BST = 2 × 24nC = 0.24μF 200mV Selecting the closest standard value, this example requires a 0.22μF ceramic capacitor. ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies Connecting the compensation network to the output (VOUT) allows the controller to feed-forward the output voltage signal, especially during transients. To reduce noise pick-up in applications that have a widely distributed layout, it is sometimes helpful to connect the compensation network to the quiet analog ground rather than VOUT. Voltage Positioning and Loop Compensation Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor’s power dissipation requirements. The controller uses a transconductance amplifier to set the transient and DC output-voltage droop (Figure 2) as a function of the load. This adjustability allows flexibility in the selected current-sense resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall power dissipated. Steady-State Voltage Positioning Connect a resistor (RFB) between FB and VOUT to set the DC steady-state droop (load line) based on the required voltage-positioning slope (RDROOP): R FB = R DROOP R SENSEG m(FB) where the effective current-sense resistance (RSENSE) depends on the current-sense method (see the Current Sense section), and the voltage-positioning amplifier’s transconductance (Gm(FB)) is typically 1.2mS as defined in the Electrical Characteristics table. The controller uses the CSPAVG pin to get the average inductor current from the positive current-sense averaging network. When the inductors’ DCR is used as the current-sense element (RSENSE = RDCR), the current-sense inputs should include an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope. Minimum Input Voltage Requirements and Dropout Performance The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot and the number of phases. For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worstcase values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the on-times. This error is greater at higher frequencies. Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the V SAG equation in the Transient Response section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (ΔIDOWN) as much as it ramps up during the on-time (ΔIUP). The ratio h = ΔIUP/ΔIDOWN is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V SAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: ⎡ VFB - VDROOP + VDIS ⎤ VIN(MIN) = η TOTAL ⎢ ⎥ ⎢⎣1 - η TOTALh × t OFF(MIN)fSW ⎥⎦ + VCHG - VDIS + VDROOP where η TOTAL is the total number of out-of-phase switching regulators, V FB is the voltage-positioning droop, VDIS and VCHG are the parasitic voltage drops in the discharge and charge paths (see the on-time one-shot parameter), tOFF(MIN) is from the Electrical Characteristics table. The absolute minimum input voltage is calculated with h = 1. ______________________________________________________________________________________ 43 MAX17410 Current-Balance Compensation (CCI) The current-balance compensation capacitor (CCCI) integrates the difference between the main and secondary current-sense voltages. The internal compensation resistor (R CCI = 200kΩ) improves transient response by increasing the phase margin. This allows the dynamics of the current-balance loop to be optimized. Excessively large capacitor values increase the integration time constant, resulting in larger current differences between the phases during transients. Excessively small capacitor values allow the current loop to respond cycle-by-cycle but can result in small DC current variations between the phases. Likewise, excessively large resistor values can also cause DC current variations between the phases. Small resistor values reduce the phase margin, resulting in marginal stability in the current-balance loop. For most applications, a 470pF capacitor from CCI to the switching regulator’s output works well. MAX17410 Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate V SAG to be sure of adequate transient response. Dropout Design Example: VFB = 1.4V fSW = 300kHz tOFF(MIN) = 400ns VDROOP = 3mV/A x 30A = 90mV VDROP1 = VDROP2 = 150mV (30A load) h = 1.5 and ηTOTAL = 2 ⎡ 1.4V - 90mV + 150mV ⎤ VIN(MIN) = 2 × ⎢ ⎥ ⎣1 - 2 × (0.4μs × 1.5 × 300kHz) ⎦ + 150mV - 150mV + 90mV = 4.96V Calculating again with h = 1 gives the absolute limit of dropout: ⎡ 1.4V - 90mV + 150mV ⎤ VIN(MIN) = 2 × ⎢ ⎥ ⎣1 - 2 × (0.4μs × 1.0 × 300kHz) ⎦ + 150mV - 150mV + 90mV = 4.07V Therefore, VIN must be greater than 4.1V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 5.0V. Applications Information PCB Layout Guidelines Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Refer to the MAX17410 evaluation kit specification for a layout example and follow these guidelines for good PCB layout: 1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. 44 2) Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the V CC bypass capacitor and GNDS bypass capacitors. 3) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mΩ of excess trace resistance causes a measurable efficiency penalty. 4) Keep the high-current, gate-driver traces (DL_, DH_, LX_, and BST_) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. 5) CSP_ and CSN_ connections for current limiting and voltage positioning must be made using Kelvin sense connections to guarantee the current-sense accuracy. 6) When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. 7) Route high-speed switching nodes away from sensitive analog areas (CCI, FB, CSP_, CSN_, etc.). Layout Procedure 1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copperfilled areas. 2) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). 3) Group the gate-drive components (BST diodes and capacitors, VDD bypass capacitor) together near the controller IC. ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies must meet the GND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the highpower output ground with a short metal trace from GND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical. Package Information Chip Information PROCESS: BiCMOS For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 TQFN-EP T4877+6 21-0144 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 45 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX17410 4) Make the DC-DC controller ground connections as shown in the standard application circuits. This diagram can be viewed as having four separate ground planes: input/output ground, where all the highpower components go; the power ground plane, where the GND pin and VDD bypass capacitor go; the master’s analog ground plane where sensitive analog components, the master’s GND pin, and VCC bypass capacitor go; and the slave’s analog ground plane where the slave’s GND pin and VCC bypass capacitor go. The master’s GND plane must meet the GND plane only at a single point directly beneath the IC. Similarly, the slave’s GND plane